1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch-ag101/ag101.h> 13 14 /* 15 * CPU and Board Configuration Options 16 */ 17 #define CONFIG_ADP_AG101P 18 19 #define CONFIG_USE_INTERRUPT 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 23 #define CONFIG_SYS_GENERIC_GLOBAL_DATA 24 25 /* 26 * Definitions related to passing arguments to kernel. 27 */ 28 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ 29 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ 30 #define CONFIG_INITRD_TAG /* send initrd params */ 31 #define CONFIG_NEEDS_MANUAL_RELOC 32 33 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 34 #define CONFIG_MEM_REMAP 35 #endif 36 37 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 38 #define CONFIG_SYS_TEXT_BASE 0x00500000 39 #else 40 #ifdef CONFIG_MEM_REMAP 41 #define CONFIG_SYS_TEXT_BASE 0x80000000 42 #else 43 #define CONFIG_SYS_TEXT_BASE 0x00000000 44 #endif 45 #endif 46 47 /* 48 * Timer 49 */ 50 #define CONFIG_SYS_CLK_FREQ 39062500 51 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 52 53 /* 54 * Use Externel CLOCK or PCLK 55 */ 56 #undef CONFIG_FTRTC010_EXTCLK 57 58 #ifndef CONFIG_FTRTC010_EXTCLK 59 #define CONFIG_FTRTC010_PCLK 60 #endif 61 62 #ifdef CONFIG_FTRTC010_EXTCLK 63 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 64 #else 65 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 66 #endif 67 68 #define TIMER_LOAD_VAL 0xffffffff 69 70 /* 71 * Real Time Clock 72 */ 73 #define CONFIG_RTC_FTRTC010 74 75 /* 76 * Real Time Clock Divider 77 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 78 */ 79 #define OSC_5MHZ (5*1000000) 80 #define OSC_CLK (4*OSC_5MHZ) 81 #define RTC_DIV_COUNT (0.5) /* Why?? */ 82 83 /* 84 * Serial console configuration 85 */ 86 87 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 88 #define CONFIG_BAUDRATE 38400 89 #define CONFIG_CONS_INDEX 1 90 #define CONFIG_SYS_NS16550_SERIAL 91 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 92 #define CONFIG_SYS_NS16550_REG_SIZE -4 93 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 94 95 /* 96 * Ethernet 97 */ 98 #define CONFIG_FTMAC100 99 100 #define CONFIG_BOOTDELAY 3 101 102 /* 103 * SD (MMC) controller 104 */ 105 #define CONFIG_MMC 106 #define CONFIG_CMD_MMC 107 #define CONFIG_GENERIC_MMC 108 #define CONFIG_DOS_PARTITION 109 #define CONFIG_FTSDC010 110 #define CONFIG_FTSDC010_NUMBER 1 111 #define CONFIG_FTSDC010_SDIO 112 #define CONFIG_CMD_FAT 113 #define CONFIG_CMD_EXT2 114 115 /* 116 * Command line configuration. 117 */ 118 #define CONFIG_CMD_CACHE 119 #define CONFIG_CMD_DATE 120 121 /* 122 * Miscellaneous configurable options 123 */ 124 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 125 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 126 127 /* Print Buffer Size */ 128 #define CONFIG_SYS_PBSIZE \ 129 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 130 131 /* max number of command args */ 132 #define CONFIG_SYS_MAXARGS 16 133 134 /* Boot Argument Buffer Size */ 135 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 136 137 /* 138 * Size of malloc() pool 139 */ 140 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 141 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 142 143 /* 144 * AHB Controller configuration 145 */ 146 #define CONFIG_FTAHBC020S 147 148 #ifdef CONFIG_FTAHBC020S 149 #include <faraday/ftahbc020s.h> 150 151 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 152 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 153 154 /* 155 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 156 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 157 * in C language. 158 */ 159 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 160 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 161 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 162 #endif 163 164 /* 165 * Watchdog 166 */ 167 #define CONFIG_FTWDT010_WATCHDOG 168 169 /* 170 * PMU Power controller configuration 171 */ 172 #define CONFIG_PMU 173 #define CONFIG_FTPMU010_POWER 174 175 #ifdef CONFIG_FTPMU010_POWER 176 #include <faraday/ftpmu010.h> 177 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 178 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 179 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 180 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 181 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 182 FTPMU010_SDRAMHTC_CKE_DCSR | \ 183 FTPMU010_SDRAMHTC_DQM_DCSR | \ 184 FTPMU010_SDRAMHTC_SDCLK_DCSR) 185 #endif 186 187 /* 188 * SDRAM controller configuration 189 */ 190 #define CONFIG_FTSDMC021 191 192 #ifdef CONFIG_FTSDMC021 193 #include <faraday/ftsdmc021.h> 194 195 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 196 FTSDMC021_TP1_TRP(1) | \ 197 FTSDMC021_TP1_TRCD(1) | \ 198 FTSDMC021_TP1_TRF(3) | \ 199 FTSDMC021_TP1_TWR(1) | \ 200 FTSDMC021_TP1_TCL(2)) 201 202 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 203 FTSDMC021_TP2_INI_REFT(8) | \ 204 FTSDMC021_TP2_REF_INTV(0x180)) 205 206 /* 207 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 208 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 209 * C language. 210 */ 211 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 212 FTSDMC021_CR1_DSZ(3) | \ 213 FTSDMC021_CR1_MBW(2) | \ 214 FTSDMC021_CR1_BNKSIZE(6)) 215 216 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 217 FTSDMC021_CR2_IREF | \ 218 FTSDMC021_CR2_ISMR) 219 220 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 221 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 222 CONFIG_SYS_FTSDMC021_BANK0_BASE) 223 224 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 225 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 226 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 227 CONFIG_SYS_FTSDMC021_BANK1_BASE) 228 #endif 229 230 /* 231 * Physical Memory Map 232 */ 233 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 234 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 235 #else 236 #ifdef CONFIG_MEM_REMAP 237 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 238 #else 239 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 240 #endif 241 #endif 242 243 #define PHYS_SDRAM_1 \ 244 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 245 246 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 247 248 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 249 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 250 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 251 #else 252 #ifdef CONFIG_MEM_REMAP 253 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 254 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 255 #else 256 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 257 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 258 #endif 259 #endif 260 261 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 262 263 #ifdef CONFIG_MEM_REMAP 264 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 265 GENERATED_GBL_DATA_SIZE) 266 #else 267 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 268 GENERATED_GBL_DATA_SIZE) 269 #endif /* CONFIG_MEM_REMAP */ 270 271 /* 272 * Load address and memory test area should agree with 273 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 274 */ 275 #define CONFIG_SYS_LOAD_ADDR 0x300000 276 277 /* memtest works on 63 MB in DRAM */ 278 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 279 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 280 281 /* 282 * Static memory controller configuration 283 */ 284 #define CONFIG_FTSMC020 285 286 #ifdef CONFIG_FTSMC020 287 #include <faraday/ftsmc020.h> 288 289 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 290 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 291 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 292 } 293 294 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 295 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 296 FTSMC020_BANK_SIZE_32M | \ 297 FTSMC020_BANK_MBW_32) 298 299 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 300 FTSMC020_TPR_AST(1) | \ 301 FTSMC020_TPR_CTW(1) | \ 302 FTSMC020_TPR_ATI(1) | \ 303 FTSMC020_TPR_AT2(1) | \ 304 FTSMC020_TPR_WTC(1) | \ 305 FTSMC020_TPR_AHT(1) | \ 306 FTSMC020_TPR_TRNA(1)) 307 #endif 308 309 /* 310 * FLASH on ADP_AG101P is connected to BANK0 311 * Just disalbe the other BANK to avoid detection error. 312 */ 313 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 314 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 315 FTSMC020_BANK_SIZE_32M | \ 316 FTSMC020_BANK_MBW_32) 317 318 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 319 FTSMC020_TPR_CTW(3) | \ 320 FTSMC020_TPR_ATI(0xf) | \ 321 FTSMC020_TPR_AT2(3) | \ 322 FTSMC020_TPR_WTC(3) | \ 323 FTSMC020_TPR_AHT(3) | \ 324 FTSMC020_TPR_TRNA(0xf)) 325 326 #define FTSMC020_BANK1_CONFIG (0x00) 327 #define FTSMC020_BANK1_TIMING (0x00) 328 #endif /* CONFIG_FTSMC020 */ 329 330 /* 331 * FLASH and environment organization 332 */ 333 /* use CFI framework */ 334 #define CONFIG_SYS_FLASH_CFI 335 #define CONFIG_FLASH_CFI_DRIVER 336 337 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 338 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 339 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 340 341 /* support JEDEC */ 342 343 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 344 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 345 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 346 #else 347 #ifdef CONFIG_MEM_REMAP 348 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 349 #else 350 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 351 #endif 352 #endif /* CONFIG_MEM_REMAP */ 353 354 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 355 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 356 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 357 358 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 359 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 360 361 /* max number of memory banks */ 362 /* 363 * There are 4 banks supported for this Controller, 364 * but we have only 1 bank connected to flash on board 365 */ 366 #define CONFIG_SYS_MAX_FLASH_BANKS 1 367 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 368 369 /* max number of sectors on one chip */ 370 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 371 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 372 #define CONFIG_SYS_MAX_FLASH_SECT 512 373 374 /* environments */ 375 #define CONFIG_ENV_IS_IN_FLASH 376 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 377 #define CONFIG_ENV_SIZE 8192 378 #define CONFIG_ENV_OVERWRITE 379 380 #endif /* __CONFIG_H */ 381