1 /* 2 * Copyright 2013-2015 Arcturus Networks, Inc. 3 * http://www.arcturusnetworks.com/products/ucp1020/ 4 * based on include/configs/p1_p2_rdb_pc.h 5 * original copyright follows: 6 * Copyright 2009-2011 Freescale Semiconductor, Inc. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * QorIQ uCP1020-xx boards configuration file 13 */ 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #define CONFIG_SYS_GENERIC_BOARD 18 #define CONFIG_DISPLAY_BOARDINFO 19 20 #define CONFIG_FSL_ELBC 21 #define CONFIG_PCI 22 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 23 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 24 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 25 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 26 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 27 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 28 29 #if defined(CONFIG_TARTGET_UCP1020T1) 30 31 #define CONFIG_UCP1020_REV_1_3 32 33 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" 34 #define CONFIG_P1020 35 36 #define CONFIG_TSEC_ENET 37 #define CONFIG_TSEC1 38 #define CONFIG_TSEC3 39 #define CONFIG_HAS_ETH0 40 #define CONFIG_HAS_ETH1 41 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF 42 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE 43 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD 44 #define CONFIG_IPADDR 10.80.41.229 45 #define CONFIG_SERVERIP 10.80.41.227 46 #define CONFIG_NETMASK 255.255.252.0 47 #define CONFIG_ETHPRIME "eTSEC3" 48 49 #ifndef CONFIG_SPI_FLASH 50 #define CONFIG_SPI_FLASH y 51 #endif 52 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 53 54 #define CONFIG_MMC 55 #define CONFIG_SYS_L2_SIZE (256 << 10) 56 57 #define CONFIG_LAST_STAGE_INIT 58 59 #if !defined(CONFIG_DONGLE) 60 #define CONFIG_SILENT_CONSOLE 61 #endif 62 63 #endif 64 65 #if defined(CONFIG_TARGET_UCP1020) 66 67 #define CONFIG_UCP1020 68 #define CONFIG_UCP1020_REV_1_3 69 70 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" 71 #define CONFIG_P1020 72 73 #define CONFIG_TSEC_ENET 74 #define CONFIG_TSEC1 75 #define CONFIG_TSEC2 76 #define CONFIG_TSEC3 77 #define CONFIG_HAS_ETH0 78 #define CONFIG_HAS_ETH1 79 #define CONFIG_HAS_ETH2 80 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF 81 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE 82 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD 83 #define CONFIG_IPADDR 192.168.1.81 84 #define CONFIG_IPADDR1 192.168.1.82 85 #define CONFIG_IPADDR2 192.168.1.83 86 #define CONFIG_SERVERIP 192.168.1.80 87 #define CONFIG_GATEWAYIP 102.168.1.1 88 #define CONFIG_NETMASK 255.255.255.0 89 #define CONFIG_ETHPRIME "eTSEC1" 90 91 #ifndef CONFIG_SPI_FLASH 92 #define CONFIG_SPI_FLASH y 93 #endif 94 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 95 96 #define CONFIG_MMC 97 #define CONFIG_SYS_L2_SIZE (256 << 10) 98 99 #define CONFIG_LAST_STAGE_INIT 100 101 #endif 102 103 #ifdef CONFIG_SDCARD 104 #define CONFIG_RAMBOOT_SDCARD 105 #define CONFIG_SYS_RAMBOOT 106 #define CONFIG_SYS_EXTRA_ENV_RELOC 107 #define CONFIG_SYS_TEXT_BASE 0x11000000 108 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 109 #endif 110 111 #ifdef CONFIG_SPIFLASH 112 #define CONFIG_RAMBOOT_SPIFLASH 113 #define CONFIG_SYS_RAMBOOT 114 #define CONFIG_SYS_EXTRA_ENV_RELOC 115 #define CONFIG_SYS_TEXT_BASE 0x11000000 116 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 117 #endif 118 119 #ifndef CONFIG_SYS_TEXT_BASE 120 #define CONFIG_SYS_TEXT_BASE 0xeff80000 121 #endif 122 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 123 124 #ifndef CONFIG_RESET_VECTOR_ADDRESS 125 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 126 #endif 127 128 #ifndef CONFIG_SYS_MONITOR_BASE 129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 130 #endif 131 132 /* High Level Configuration Options */ 133 #define CONFIG_BOOKE 134 #define CONFIG_E500 135 /* #define CONFIG_MPC85xx */ 136 137 #define CONFIG_MP 138 139 #define CONFIG_FSL_LAW 140 141 #define CONFIG_ENV_OVERWRITE 142 143 #define CONFIG_CMD_SATA 144 #define CONFIG_SATA_SIL 145 #define CONFIG_SYS_SATA_MAX_DEVICE 2 146 #define CONFIG_LIBATA 147 #define CONFIG_LBA48 148 149 #define CONFIG_SYS_CLK_FREQ 66666666 150 #define CONFIG_DDR_CLK_FREQ 66666666 151 152 #define CONFIG_HWCONFIG 153 154 #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ 155 #define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */ 156 #define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */ 157 /* 158 * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details). 159 * there will be one entry in this array for each two (dummy) sensors in 160 * CONFIG_DTT_SENSORS. 161 * 162 * For uCP1020 module: 163 * - only one ADM1021/NCT72 164 * - i2c addr 0x41 165 * - conversion rate 0x02 = 0.25 conversions/second 166 * - ALERT output disabled 167 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg 168 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg 169 */ 170 #define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \ 171 0x02, 0, 1, 0, 85, 1, 0, 85} } 172 173 #define CONFIG_CMD_DTT 174 175 /* 176 * These can be toggled for performance analysis, otherwise use default. 177 */ 178 #define CONFIG_L2_CACHE 179 #define CONFIG_BTB 180 181 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 182 183 #define CONFIG_ENABLE_36BIT_PHYS 184 185 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 186 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 187 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 188 189 #define CONFIG_SYS_CCSRBAR 0xffe00000 190 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 191 192 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 193 SPL code*/ 194 #ifdef CONFIG_SPL_BUILD 195 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 196 #endif 197 198 /* DDR Setup */ 199 #define CONFIG_DDR_ECC_ENABLE 200 #define CONFIG_SYS_FSL_DDR3 201 #ifndef CONFIG_DDR_ECC_ENABLE 202 #define CONFIG_SYS_DDR_RAW_TIMING 203 #define CONFIG_DDR_SPD 204 #endif 205 #define CONFIG_SYS_SPD_BUS_NUM 1 206 #undef CONFIG_FSL_DDR_INTERACTIVE 207 208 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 209 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 210 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 211 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 212 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 213 214 #define CONFIG_NUM_DDR_CONTROLLERS 1 215 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 216 217 /* Default settings for DDR3 */ 218 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 219 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 220 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 221 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 222 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 223 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 224 225 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 226 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 227 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 228 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 229 230 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 231 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 232 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 233 #define CONFIG_SYS_DDR_RCW_1 0x00000000 234 #define CONFIG_SYS_DDR_RCW_2 0x00000000 235 #ifdef CONFIG_DDR_ECC_ENABLE 236 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ 237 #else 238 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 239 #endif 240 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 241 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 242 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 243 244 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 245 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 246 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 247 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 248 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 249 #define CONFIG_SYS_DDR_MODE_1 0x40461520 250 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 251 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 252 253 #undef CONFIG_CLOCKS_IN_MHZ 254 255 /* 256 * Memory map 257 * 258 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 259 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) 260 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 261 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable 262 * (early boot only) 263 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 264 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 265 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 266 */ 267 268 /* 269 * Local Bus Definitions 270 */ 271 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 272 #define CONFIG_SYS_FLASH_BASE 0xec000000 273 274 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 275 276 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 277 | BR_PS_16 | BR_V) 278 279 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 280 281 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 282 #define CONFIG_SYS_FLASH_QUIET_TEST 283 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 284 285 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 286 287 #undef CONFIG_SYS_FLASH_CHECKSUM 288 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 289 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 290 291 #define CONFIG_FLASH_CFI_DRIVER 292 #define CONFIG_SYS_FLASH_CFI 293 #define CONFIG_SYS_FLASH_EMPTY_INFO 294 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 295 296 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 297 298 #define CONFIG_SYS_INIT_RAM_LOCK 299 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 300 /* Initial L1 address */ 301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 304 /* Size of used area in RAM */ 305 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 306 307 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 308 GENERATED_GBL_DATA_SIZE) 309 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 310 311 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ 312 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 313 314 #define CONFIG_SYS_PMC_BASE 0xff980000 315 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 316 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 317 BR_PS_8 | BR_V) 318 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 319 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 320 OR_GPCM_EAD) 321 322 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 323 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 324 #ifdef CONFIG_NAND_FSL_ELBC 325 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 326 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 327 #endif 328 329 /* Serial Port - controlled on board with jumper J8 330 * open - index 2 331 * shorted - index 1 332 */ 333 #define CONFIG_CONS_INDEX 1 334 #undef CONFIG_SERIAL_SOFTWARE_FIFO 335 #define CONFIG_SYS_NS16550 336 #define CONFIG_SYS_NS16550_SERIAL 337 #define CONFIG_SYS_NS16550_REG_SIZE 1 338 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 339 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 340 #define CONFIG_NS16550_MIN_FUNCTIONS 341 #endif 342 343 #define CONFIG_SYS_BAUDRATE_TABLE \ 344 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 345 346 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 347 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 348 349 /* Use the HUSH parser */ 350 #define CONFIG_SYS_HUSH_PARSER 351 352 /* 353 * Pass open firmware flat tree 354 */ 355 #define CONFIG_OF_LIBFDT 356 #define CONFIG_OF_BOARD_SETUP 357 #define CONFIG_OF_STDOUT_VIA_ALIAS 358 359 /* new uImage format support */ 360 #define CONFIG_FIT 361 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 362 363 /* I2C */ 364 #define CONFIG_SYS_I2C 365 #define CONFIG_SYS_I2C_FSL 366 #define CONFIG_SYS_FSL_I2C_SPEED 400000 367 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 368 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 369 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 370 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 371 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 372 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 373 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 374 375 #define CONFIG_RTC_DS1337 376 #define CONFIG_SYS_RTC_DS1337_NOOSC 377 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 378 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 379 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C 380 #define CONFIG_SYS_I2C_IDT6V49205B 0x69 381 382 /* 383 * eSPI - Enhanced SPI 384 */ 385 #define CONFIG_HARD_SPI 386 #define CONFIG_FSL_ESPI 387 388 #define CONFIG_SPI_FLASH_SST 1 389 #define CONFIG_SPI_FLASH_STMICRO 1 390 #define CONFIG_SPI_FLASH_WINBOND 1 391 #define CONFIG_CMD_SF 1 392 #define CONFIG_CMD_SPI 1 393 #define CONFIG_SF_DEFAULT_SPEED 10000000 394 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 395 396 #if defined(CONFIG_PCI) 397 /* 398 * General PCI 399 * Memory space is mapped 1-1, but I/O space must start from 0. 400 */ 401 402 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 403 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" 404 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 405 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 406 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 407 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 408 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 409 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 410 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 411 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 412 413 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 414 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" 415 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 416 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 417 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 418 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 419 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 420 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 421 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 422 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 423 424 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 425 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ 426 #define CONFIG_CMD_PCI 427 #define CONFIG_CMD_NET 428 429 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 430 #define CONFIG_DOS_PARTITION 431 #endif /* CONFIG_PCI */ 432 433 /* 434 * Environment 435 */ 436 #ifdef CONFIG_ENV_FIT_UCBOOT 437 438 #define CONFIG_ENV_IS_IN_FLASH 439 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) 440 #define CONFIG_ENV_SIZE 0x20000 441 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 442 443 #else 444 445 #define CONFIG_ENV_SPI_BUS 0 446 #define CONFIG_ENV_SPI_CS 0 447 #define CONFIG_ENV_SPI_MAX_HZ 10000000 448 #define CONFIG_ENV_SPI_MODE 0 449 450 #ifdef CONFIG_RAMBOOT_SPIFLASH 451 452 #define CONFIG_ENV_IS_IN_SPI_FLASH 453 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */ 454 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */ 455 #define CONFIG_ENV_SECT_SIZE 0x1000 456 457 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 458 /* Address and size of Redundant Environment Sector */ 459 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 460 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 461 #endif 462 463 #elif defined(CONFIG_RAMBOOT_SDCARD) 464 #define CONFIG_ENV_IS_IN_MMC 465 #define CONFIG_FSL_FIXED_MMC_LOCATION 466 #define CONFIG_ENV_SIZE 0x2000 467 #define CONFIG_SYS_MMC_ENV_DEV 0 468 469 #elif defined(CONFIG_SYS_RAMBOOT) 470 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 471 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 472 #define CONFIG_ENV_SIZE 0x2000 473 474 #else 475 #define CONFIG_ENV_IS_IN_FLASH 476 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE) 477 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 478 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 479 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000) 480 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 481 /* Address and size of Redundant Environment Sector */ 482 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 483 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 484 #endif 485 486 #endif 487 488 #endif /* CONFIG_ENV_FIT_UCBOOT */ 489 490 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 491 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 492 493 /* 494 * Command line configuration. 495 */ 496 #include <config_cmd_default.h> 497 498 #define CONFIG_CMD_IRQ 499 #define CONFIG_CMD_PING 500 #define CONFIG_CMD_I2C 501 #define CONFIG_CMD_MII 502 #define CONFIG_CMD_DATE 503 #define CONFIG_CMD_ELF 504 #define CONFIG_CMD_I2C 505 #define CONFIG_CMD_IRQ 506 #define CONFIG_CMD_MII 507 #define CONFIG_CMD_PING 508 #define CONFIG_CMD_REGINFO 509 #define CONFIG_CMD_ERRATA 510 #define CONFIG_CMD_CRAMFS 511 #define CONFIG_CRAMFS_CMDLINE 512 513 /* 514 * USB 515 */ 516 #define CONFIG_HAS_FSL_DR_USB 517 518 #if defined(CONFIG_HAS_FSL_DR_USB) 519 #define CONFIG_USB_EHCI 520 521 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 522 523 #ifdef CONFIG_USB_EHCI 524 #define CONFIG_CMD_USB 525 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 526 #define CONFIG_USB_EHCI_FSL 527 #define CONFIG_USB_STORAGE 528 #endif 529 #endif 530 531 #undef CONFIG_WATCHDOG /* watchdog disabled */ 532 533 #ifdef CONFIG_MMC 534 #define CONFIG_FSL_ESDHC 535 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 536 #define CONFIG_CMD_MMC 537 #define CONFIG_MMC_SPI 538 #define CONFIG_CMD_MMC_SPI 539 #define CONFIG_GENERIC_MMC 540 #endif 541 542 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA) 543 #define CONFIG_CMD_EXT2 544 #define CONFIG_CMD_FAT 545 #define CONFIG_DOS_PARTITION 546 #endif 547 548 /* Misc Extra Settings */ 549 #define CONFIG_CMD_GPIO 1 550 #undef CONFIG_WATCHDOG /* watchdog disabled */ 551 552 /* 553 * Miscellaneous configurable options 554 */ 555 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 556 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 557 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 558 #define CONFIG_SYS_PROMPT "B$ " /* Monitor Command Prompt */ 559 #if defined(CONFIG_CMD_KGDB) 560 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 561 #else 562 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 563 #endif 564 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 565 /* Print Buffer Size */ 566 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 567 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 568 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ 569 570 /* 571 * For booting Linux, the board info and command line data 572 * have to be in the first 64 MB of memory, since this is 573 * the maximum mapped by the Linux kernel during initialization. 574 */ 575 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 576 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 577 578 #if defined(CONFIG_CMD_KGDB) 579 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 580 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 581 #endif 582 583 /* 584 * Environment Configuration 585 */ 586 587 #if defined(CONFIG_TSEC_ENET) 588 589 #if defined(CONFIG_UCP1020_REV_1_2) 590 #define CONFIG_PHY_MICREL_KSZ9021 591 #elif defined(CONFIG_UCP1020_REV_1_3) 592 #define CONFIG_PHY_MICREL_KSZ9031 593 #else 594 #error "UCP1020 module revision is not defined !!!" 595 #endif 596 597 #define CONFIG_CMD_DHCP 598 #define CONFIG_BOOTP_SERVERIP 599 600 #define CONFIG_MII /* MII PHY management */ 601 #define CONFIG_TSEC1_NAME "eTSEC1" 602 #define CONFIG_TSEC2_NAME "eTSEC2" 603 #define CONFIG_TSEC3_NAME "eTSEC3" 604 605 #define TSEC1_PHY_ADDR 4 606 #define TSEC2_PHY_ADDR 0 607 #define TSEC2_PHY_ADDR_SGMII 0x00 608 #define TSEC3_PHY_ADDR 6 609 610 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 611 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 612 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 613 614 #define TSEC1_PHYIDX 0 615 #define TSEC2_PHYIDX 0 616 #define TSEC3_PHYIDX 0 617 618 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 619 620 #endif 621 622 #define CONFIG_HOSTNAME UCP1020 623 #define CONFIG_ROOTPATH "/opt/nfsroot" 624 #define CONFIG_BOOTFILE "uImage" 625 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 626 627 /* default location for tftp and bootm */ 628 #define CONFIG_LOADADDR 1000000 629 630 /* 631 * Autobooting 632 */ 633 #define CONFIG_AUTOBOOT_KEYED 634 #define CONFIG_AUTOBOOT_STOP_STR "\x1b" 635 #define DEBUG_BOOTKEYS 0 636 #undef CONFIG_AUTOBOOT_DELAY_STR 637 #undef CONFIG_BOOTARGS 638 #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ 639 "press \"<Esc>\" to stop\n", bootdelay 640 641 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 642 643 #define CONFIG_BAUDRATE 115200 644 645 #if defined(CONFIG_DONGLE) 646 647 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ 648 #define CONFIG_EXTRA_ENV_SETTINGS \ 649 "bootcmd=run prog_spi_mbrbootcramfs\0" \ 650 "bootfile=uImage\0" \ 651 "consoledev=ttyS0\0" \ 652 "cramfsfile=image.cramfs\0" \ 653 "dtbaddr=0x00c00000\0" \ 654 "dtbfile=image.dtb\0" \ 655 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 656 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 657 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 658 "fileaddr=0x01000000\0" \ 659 "filesize=0x00080000\0" \ 660 "flashmbr=sf probe 0; " \ 661 "tftp $loadaddr $mbr; " \ 662 "sf erase $mbr_offset +$filesize; " \ 663 "sf write $loadaddr $mbr_offset $filesize\0" \ 664 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 665 "protect off $nor_recoveryaddr +$filesize; " \ 666 "erase $nor_recoveryaddr +$filesize; " \ 667 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 668 "protect on $nor_recoveryaddr +$filesize\0 " \ 669 "flashuboot=tftp $ubootaddr $ubootfile; " \ 670 "protect off $nor_ubootaddr +$filesize; " \ 671 "erase $nor_ubootaddr +$filesize; " \ 672 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 673 "protect on $nor_ubootaddr +$filesize\0 " \ 674 "flashworking=tftp $workingaddr $cramfsfile; " \ 675 "protect off $nor_workingaddr +$filesize; " \ 676 "erase $nor_workingaddr +$filesize; " \ 677 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 678 "protect on $nor_workingaddr +$filesize\0 " \ 679 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 680 "kerneladdr=0x01100000\0" \ 681 "kernelfile=uImage\0" \ 682 "loadaddr=0x01000000\0" \ 683 "mbr=uCP1020d.mbr\0" \ 684 "mbr_offset=0x00000000\0" \ 685 "mmbr=uCP1020Quiet.mbr\0" \ 686 "mmcpart=0:2\0" \ 687 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 688 "mmc erase 1 1; " \ 689 "mmc write $loadaddr 1 1\0" \ 690 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ 691 "mmc erase 0x40 0x400; " \ 692 "mmc write $loadaddr 0x40 0x400\0" \ 693 "netdev=eth0\0" \ 694 "nor_recoveryaddr=0xEC0A0000\0" \ 695 "nor_ubootaddr=0xEFF80000\0" \ 696 "nor_workingaddr=0xECFA0000\0" \ 697 "norbootrecovery=setenv bootargs $recoverybootargs" \ 698 " console=$consoledev,$baudrate $othbootargs; " \ 699 "run norloadrecovery; " \ 700 "bootm $kerneladdr - $dtbaddr\0" \ 701 "norbootworking=setenv bootargs $workingbootargs" \ 702 " console=$consoledev,$baudrate $othbootargs; " \ 703 "run norloadworking; " \ 704 "bootm $kerneladdr - $dtbaddr\0" \ 705 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 706 "setenv cramfsaddr $nor_recoveryaddr; " \ 707 "cramfsload $dtbaddr $dtbfile; " \ 708 "cramfsload $kerneladdr $kernelfile\0" \ 709 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 710 "setenv cramfsaddr $nor_workingaddr; " \ 711 "cramfsload $dtbaddr $dtbfile; " \ 712 "cramfsload $kerneladdr $kernelfile\0" \ 713 "prog_spi_mbr=run spi__mbr\0" \ 714 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ 715 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ 716 "run spi__cramfs\0" \ 717 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 718 " console=$consoledev,$baudrate $othbootargs; " \ 719 "tftp $rootfsaddr $rootfsfile; " \ 720 "tftp $loadaddr $kernelfile; " \ 721 "tftp $dtbaddr $dtbfile; " \ 722 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 723 "ramdisk_size=120000\0" \ 724 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 725 "recoveryaddr=0x02F00000\0" \ 726 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 727 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 728 "mw.l 0xffe0f008 0x00400000\0" \ 729 "rootfsaddr=0x02F00000\0" \ 730 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 731 "rootpath=/opt/nfsroot\0" \ 732 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 733 "protect off 0xeC000000 +$filesize; " \ 734 "erase 0xEC000000 +$filesize; " \ 735 "cp.b $loadaddr 0xEC000000 $filesize; " \ 736 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 737 "protect on 0xeC000000 +$filesize\0" \ 738 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 739 "protect off 0xeFF80000 +$filesize; " \ 740 "erase 0xEFF80000 +$filesize; " \ 741 "cp.b $loadaddr 0xEFF80000 $filesize; " \ 742 "cmp.b $loadaddr 0xEFF80000 $filesize; " \ 743 "protect on 0xeFF80000 +$filesize\0" \ 744 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ 745 "sf probe 0; sf erase 0x8000 +$filesize; " \ 746 "sf write $loadaddr 0x8000 $filesize\0" \ 747 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ 748 "protect off 0xec0a0000 +$filesize; " \ 749 "erase 0xeC0A0000 +$filesize; " \ 750 "cp.b $loadaddr 0xeC0A0000 $filesize; " \ 751 "protect on 0xec0a0000 +$filesize\0" \ 752 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 753 "sf probe 1; sf erase 0 +$filesize; " \ 754 "sf write $loadaddr 0 $filesize\0" \ 755 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 756 "sf probe 0; sf erase 0 +$filesize; " \ 757 "sf write $loadaddr 0 $filesize\0" \ 758 "tftpflash=tftpboot $loadaddr $uboot; " \ 759 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 760 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 761 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 762 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 763 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 764 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 765 "ubootaddr=0x01000000\0" \ 766 "ubootfile=u-boot.bin\0" \ 767 "ubootd=u-boot4dongle.bin\0" \ 768 "upgrade=run flashworking\0" \ 769 "usb_phy_type=ulpi\0 " \ 770 "workingaddr=0x02F00000\0" \ 771 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 772 773 #else 774 775 #if defined(CONFIG_UCP1020T1) 776 777 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */ 778 #define CONFIG_EXTRA_ENV_SETTINGS \ 779 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ 780 "bootfile=uImage\0" \ 781 "consoledev=ttyS0\0" \ 782 "cramfsfile=image.cramfs\0" \ 783 "dtbaddr=0x00c00000\0" \ 784 "dtbfile=image.dtb\0" \ 785 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 786 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 787 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 788 "fileaddr=0x01000000\0" \ 789 "filesize=0x00080000\0" \ 790 "flashmbr=sf probe 0; " \ 791 "tftp $loadaddr $mbr; " \ 792 "sf erase $mbr_offset +$filesize; " \ 793 "sf write $loadaddr $mbr_offset $filesize\0" \ 794 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 795 "protect off $nor_recoveryaddr +$filesize; " \ 796 "erase $nor_recoveryaddr +$filesize; " \ 797 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 798 "protect on $nor_recoveryaddr +$filesize\0 " \ 799 "flashuboot=tftp $ubootaddr $ubootfile; " \ 800 "protect off $nor_ubootaddr +$filesize; " \ 801 "erase $nor_ubootaddr +$filesize; " \ 802 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 803 "protect on $nor_ubootaddr +$filesize\0 " \ 804 "flashworking=tftp $workingaddr $cramfsfile; " \ 805 "protect off $nor_workingaddr +$filesize; " \ 806 "erase $nor_workingaddr +$filesize; " \ 807 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 808 "protect on $nor_workingaddr +$filesize\0 " \ 809 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 810 "kerneladdr=0x01100000\0" \ 811 "kernelfile=uImage\0" \ 812 "loadaddr=0x01000000\0" \ 813 "mbr=uCP1020.mbr\0" \ 814 "mbr_offset=0x00000000\0" \ 815 "netdev=eth0\0" \ 816 "nor_recoveryaddr=0xEC0A0000\0" \ 817 "nor_ubootaddr=0xEFF80000\0" \ 818 "nor_workingaddr=0xECFA0000\0" \ 819 "norbootrecovery=setenv bootargs $recoverybootargs" \ 820 " console=$consoledev,$baudrate $othbootargs; " \ 821 "run norloadrecovery; " \ 822 "bootm $kerneladdr - $dtbaddr\0" \ 823 "norbootworking=setenv bootargs $workingbootargs" \ 824 " console=$consoledev,$baudrate $othbootargs; " \ 825 "run norloadworking; " \ 826 "bootm $kerneladdr - $dtbaddr\0" \ 827 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 828 "setenv cramfsaddr $nor_recoveryaddr; " \ 829 "cramfsload $dtbaddr $dtbfile; " \ 830 "cramfsload $kerneladdr $kernelfile\0" \ 831 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 832 "setenv cramfsaddr $nor_workingaddr; " \ 833 "cramfsload $dtbaddr $dtbfile; " \ 834 "cramfsload $kerneladdr $kernelfile\0" \ 835 "othbootargs=quiet\0" \ 836 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 837 " console=$consoledev,$baudrate $othbootargs; " \ 838 "tftp $rootfsaddr $rootfsfile; " \ 839 "tftp $loadaddr $kernelfile; " \ 840 "tftp $dtbaddr $dtbfile; " \ 841 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 842 "ramdisk_size=120000\0" \ 843 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 844 "recoveryaddr=0x02F00000\0" \ 845 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 846 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 847 "mw.l 0xffe0f008 0x00400000\0" \ 848 "rootfsaddr=0x02F00000\0" \ 849 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 850 "rootpath=/opt/nfsroot\0" \ 851 "silent=1\0" \ 852 "tftpflash=tftpboot $loadaddr $uboot; " \ 853 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 854 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 855 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 856 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 857 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 858 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 859 "ubootaddr=0x01000000\0" \ 860 "ubootfile=u-boot.bin\0" \ 861 "upgrade=run flashworking\0" \ 862 "workingaddr=0x02F00000\0" \ 863 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 864 865 #else /* For Arcturus Modules */ 866 867 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */ 868 #define CONFIG_EXTRA_ENV_SETTINGS \ 869 "bootcmd=run norkernel\0" \ 870 "bootfile=uImage\0" \ 871 "consoledev=ttyS0\0" \ 872 "dtbaddr=0x00c00000\0" \ 873 "dtbfile=image.dtb\0" \ 874 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 875 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 876 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 877 "fileaddr=0x01000000\0" \ 878 "filesize=0x00080000\0" \ 879 "flashmbr=sf probe 0; " \ 880 "tftp $loadaddr $mbr; " \ 881 "sf erase $mbr_offset +$filesize; " \ 882 "sf write $loadaddr $mbr_offset $filesize\0" \ 883 "flashuboot=tftp $loadaddr $ubootfile; " \ 884 "protect off $nor_ubootaddr0 +$filesize; " \ 885 "erase $nor_ubootaddr0 +$filesize; " \ 886 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ 887 "protect on $nor_ubootaddr0 +$filesize; " \ 888 "protect off $nor_ubootaddr1 +$filesize; " \ 889 "erase $nor_ubootaddr1 +$filesize; " \ 890 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ 891 "protect on $nor_ubootaddr1 +$filesize\0 " \ 892 "format0=protect off $part0base +$part0size; " \ 893 "erase $part0base +$part0size\0" \ 894 "format1=protect off $part1base +$part1size; " \ 895 "erase $part1base +$part1size\0" \ 896 "format2=protect off $part2base +$part2size; " \ 897 "erase $part2base +$part2size\0" \ 898 "format3=protect off $part3base +$part3size; " \ 899 "erase $part3base +$part3size\0" \ 900 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 901 "kerneladdr=0x01100000\0" \ 902 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ 903 "kernelfile=uImage\0" \ 904 "loadaddr=0x01000000\0" \ 905 "mbr=uCP1020.mbr\0" \ 906 "mbr_offset=0x00000000\0" \ 907 "netdev=eth0\0" \ 908 "nor_ubootaddr0=0xEC000000\0" \ 909 "nor_ubootaddr1=0xEFF80000\0" \ 910 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ 911 "run norkernelload; " \ 912 "bootm $kerneladdr - $dtbaddr\0" \ 913 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ 914 "setenv cramfsaddr $part0base; " \ 915 "cramfsload $dtbaddr $dtbfile; " \ 916 "cramfsload $kerneladdr $kernelfile\0" \ 917 "part0base=0xEC100000\0" \ 918 "part0size=0x00700000\0" \ 919 "part1base=0xEC800000\0" \ 920 "part1size=0x02000000\0" \ 921 "part2base=0xEE800000\0" \ 922 "part2size=0x00800000\0" \ 923 "part3base=0xEF000000\0" \ 924 "part3size=0x00F80000\0" \ 925 "partENVbase=0xEC080000\0" \ 926 "partENVsize=0x00080000\0" \ 927 "program0=tftp part0-000000.bin; " \ 928 "protect off $part0base +$filesize; " \ 929 "erase $part0base +$filesize; " \ 930 "cp.b $loadaddr $part0base $filesize; " \ 931 "echo Verifying...; " \ 932 "cmp.b $loadaddr $part0base $filesize\0" \ 933 "program1=tftp part1-000000.bin; " \ 934 "protect off $part1base +$filesize; " \ 935 "erase $part1base +$filesize; " \ 936 "cp.b $loadaddr $part1base $filesize; " \ 937 "echo Verifying...; " \ 938 "cmp.b $loadaddr $part1base $filesize\0" \ 939 "program2=tftp part2-000000.bin; " \ 940 "protect off $part2base +$filesize; " \ 941 "erase $part2base +$filesize; " \ 942 "cp.b $loadaddr $part2base $filesize; " \ 943 "echo Verifying...; " \ 944 "cmp.b $loadaddr $part2base $filesize\0" \ 945 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 946 " console=$consoledev,$baudrate $othbootargs; " \ 947 "tftp $rootfsaddr $rootfsfile; " \ 948 "tftp $loadaddr $kernelfile; " \ 949 "tftp $dtbaddr $dtbfile; " \ 950 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 951 "ramdisk_size=120000\0" \ 952 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 953 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 954 "mw.l 0xffe0f008 0x00400000\0" \ 955 "rootfsaddr=0x02F00000\0" \ 956 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 957 "rootpath=/opt/nfsroot\0" \ 958 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 959 "sf probe 0; sf erase 0 +$filesize; " \ 960 "sf write $loadaddr 0 $filesize\0" \ 961 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 962 "protect off 0xeC000000 +$filesize; " \ 963 "erase 0xEC000000 +$filesize; " \ 964 "cp.b $loadaddr 0xEC000000 $filesize; " \ 965 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 966 "protect on 0xeC000000 +$filesize\0" \ 967 "tftpflash=tftpboot $loadaddr $uboot; " \ 968 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 969 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 970 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 971 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 972 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 973 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 974 "ubootfile=u-boot.bin\0" \ 975 "upgrade=run flashuboot\0" \ 976 "usb_phy_type=ulpi\0 " \ 977 "boot_nfs= " \ 978 "setenv bootargs root=/dev/nfs rw " \ 979 "nfsroot=$serverip:$rootpath " \ 980 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 981 "console=$consoledev,$baudrate $othbootargs;" \ 982 "tftp $loadaddr $bootfile;" \ 983 "tftp $fdtaddr $fdtfile;" \ 984 "bootm $loadaddr - $fdtaddr\0" \ 985 "boot_hd = " \ 986 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 987 "console=$consoledev,$baudrate $othbootargs;" \ 988 "usb start;" \ 989 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 990 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 991 "bootm $loadaddr - $fdtaddr\0" \ 992 "boot_usb_fat = " \ 993 "setenv bootargs root=/dev/ram rw " \ 994 "console=$consoledev,$baudrate $othbootargs " \ 995 "ramdisk_size=$ramdisk_size;" \ 996 "usb start;" \ 997 "fatload usb 0:2 $loadaddr $bootfile;" \ 998 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 999 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1000 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 1001 "boot_usb_ext2 = " \ 1002 "setenv bootargs root=/dev/ram rw " \ 1003 "console=$consoledev,$baudrate $othbootargs " \ 1004 "ramdisk_size=$ramdisk_size;" \ 1005 "usb start;" \ 1006 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1007 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1008 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1009 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 1010 "boot_nor = " \ 1011 "setenv bootargs root=/dev/$jffs2nor rw " \ 1012 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1013 "bootm $norbootaddr - $norfdtaddr\0 " \ 1014 "boot_ram = " \ 1015 "setenv bootargs root=/dev/ram rw " \ 1016 "console=$consoledev,$baudrate $othbootargs " \ 1017 "ramdisk_size=$ramdisk_size;" \ 1018 "tftp $ramdiskaddr $ramdiskfile;" \ 1019 "tftp $loadaddr $bootfile;" \ 1020 "tftp $fdtaddr $fdtfile;" \ 1021 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" 1022 1023 #endif 1024 #endif 1025 1026 #endif /* __CONFIG_H */ 1027