1 /* 2 * Copyright 2013-2015 Arcturus Networks, Inc. 3 * http://www.arcturusnetworks.com/products/ucp1020/ 4 * based on include/configs/p1_p2_rdb_pc.h 5 * original copyright follows: 6 * Copyright 2009-2011 Freescale Semiconductor, Inc. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * QorIQ uCP1020-xx boards configuration file 13 */ 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #define CONFIG_FSL_ELBC 18 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 19 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 20 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 21 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 22 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 23 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 24 25 #if defined(CONFIG_TARTGET_UCP1020T1) 26 27 #define CONFIG_UCP1020_REV_1_3 28 29 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" 30 31 #define CONFIG_TSEC_ENET 32 #define CONFIG_TSEC1 33 #define CONFIG_TSEC3 34 #define CONFIG_HAS_ETH0 35 #define CONFIG_HAS_ETH1 36 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF 37 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE 38 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD 39 #define CONFIG_IPADDR 10.80.41.229 40 #define CONFIG_SERVERIP 10.80.41.227 41 #define CONFIG_NETMASK 255.255.252.0 42 #define CONFIG_ETHPRIME "eTSEC3" 43 44 #ifndef CONFIG_SPI_FLASH 45 #endif 46 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 47 48 #define CONFIG_SYS_L2_SIZE (256 << 10) 49 50 #define CONFIG_LAST_STAGE_INIT 51 52 #endif 53 54 #if defined(CONFIG_TARGET_UCP1020) 55 56 #define CONFIG_UCP1020 57 #define CONFIG_UCP1020_REV_1_3 58 59 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" 60 61 #define CONFIG_TSEC_ENET 62 #define CONFIG_TSEC1 63 #define CONFIG_TSEC2 64 #define CONFIG_TSEC3 65 #define CONFIG_HAS_ETH0 66 #define CONFIG_HAS_ETH1 67 #define CONFIG_HAS_ETH2 68 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF 69 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE 70 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD 71 #define CONFIG_IPADDR 192.168.1.81 72 #define CONFIG_IPADDR1 192.168.1.82 73 #define CONFIG_IPADDR2 192.168.1.83 74 #define CONFIG_SERVERIP 192.168.1.80 75 #define CONFIG_GATEWAYIP 102.168.1.1 76 #define CONFIG_NETMASK 255.255.255.0 77 #define CONFIG_ETHPRIME "eTSEC1" 78 79 #ifndef CONFIG_SPI_FLASH 80 #endif 81 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 82 83 #define CONFIG_SYS_L2_SIZE (256 << 10) 84 85 #define CONFIG_LAST_STAGE_INIT 86 87 #endif 88 89 #ifdef CONFIG_SDCARD 90 #define CONFIG_RAMBOOT_SDCARD 91 #define CONFIG_SYS_RAMBOOT 92 #define CONFIG_SYS_EXTRA_ENV_RELOC 93 #define CONFIG_SYS_TEXT_BASE 0x11000000 94 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 95 #endif 96 97 #ifdef CONFIG_SPIFLASH 98 #define CONFIG_RAMBOOT_SPIFLASH 99 #define CONFIG_SYS_RAMBOOT 100 #define CONFIG_SYS_EXTRA_ENV_RELOC 101 #define CONFIG_SYS_TEXT_BASE 0x11000000 102 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 103 #endif 104 105 #ifndef CONFIG_SYS_TEXT_BASE 106 #define CONFIG_SYS_TEXT_BASE 0xeff80000 107 #endif 108 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 109 110 #ifndef CONFIG_RESET_VECTOR_ADDRESS 111 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 112 #endif 113 114 #ifndef CONFIG_SYS_MONITOR_BASE 115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 116 #endif 117 118 #define CONFIG_MP 119 120 #define CONFIG_ENV_OVERWRITE 121 122 #define CONFIG_CMD_SATA 123 #define CONFIG_SATA_SIL 124 #define CONFIG_SYS_SATA_MAX_DEVICE 2 125 #define CONFIG_LIBATA 126 #define CONFIG_LBA48 127 128 #define CONFIG_SYS_CLK_FREQ 66666666 129 #define CONFIG_DDR_CLK_FREQ 66666666 130 131 #define CONFIG_HWCONFIG 132 133 #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ 134 #define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */ 135 #define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */ 136 /* 137 * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details). 138 * there will be one entry in this array for each two (dummy) sensors in 139 * CONFIG_DTT_SENSORS. 140 * 141 * For uCP1020 module: 142 * - only one ADM1021/NCT72 143 * - i2c addr 0x41 144 * - conversion rate 0x02 = 0.25 conversions/second 145 * - ALERT output disabled 146 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg 147 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg 148 */ 149 #define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \ 150 0x02, 0, 1, 0, 85, 1, 0, 85} } 151 152 #define CONFIG_CMD_DTT 153 154 /* 155 * These can be toggled for performance analysis, otherwise use default. 156 */ 157 #define CONFIG_L2_CACHE 158 #define CONFIG_BTB 159 160 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 161 162 #define CONFIG_ENABLE_36BIT_PHYS 163 164 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 165 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 166 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 167 168 #define CONFIG_SYS_CCSRBAR 0xffe00000 169 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 170 171 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 172 SPL code*/ 173 #ifdef CONFIG_SPL_BUILD 174 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 175 #endif 176 177 /* DDR Setup */ 178 #define CONFIG_DDR_ECC_ENABLE 179 #define CONFIG_SYS_FSL_DDR3 180 #ifndef CONFIG_DDR_ECC_ENABLE 181 #define CONFIG_SYS_DDR_RAW_TIMING 182 #define CONFIG_DDR_SPD 183 #endif 184 #define CONFIG_SYS_SPD_BUS_NUM 1 185 #undef CONFIG_FSL_DDR_INTERACTIVE 186 187 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 188 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 189 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 190 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 191 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 192 193 #define CONFIG_NUM_DDR_CONTROLLERS 1 194 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 195 196 /* Default settings for DDR3 */ 197 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 198 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 199 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 200 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 201 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 202 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 203 204 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 205 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 206 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 207 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 208 209 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 210 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 211 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 212 #define CONFIG_SYS_DDR_RCW_1 0x00000000 213 #define CONFIG_SYS_DDR_RCW_2 0x00000000 214 #ifdef CONFIG_DDR_ECC_ENABLE 215 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ 216 #else 217 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 218 #endif 219 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 220 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 221 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 222 223 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 224 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 225 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 226 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 227 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 228 #define CONFIG_SYS_DDR_MODE_1 0x40461520 229 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 230 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 231 232 #undef CONFIG_CLOCKS_IN_MHZ 233 234 /* 235 * Memory map 236 * 237 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 238 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) 239 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 240 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable 241 * (early boot only) 242 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 243 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 244 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 245 */ 246 247 /* 248 * Local Bus Definitions 249 */ 250 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 251 #define CONFIG_SYS_FLASH_BASE 0xec000000 252 253 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 254 255 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 256 | BR_PS_16 | BR_V) 257 258 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 259 260 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 261 #define CONFIG_SYS_FLASH_QUIET_TEST 262 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 263 264 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 265 266 #undef CONFIG_SYS_FLASH_CHECKSUM 267 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 268 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 269 270 #define CONFIG_FLASH_CFI_DRIVER 271 #define CONFIG_SYS_FLASH_CFI 272 #define CONFIG_SYS_FLASH_EMPTY_INFO 273 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 274 275 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 276 277 #define CONFIG_SYS_INIT_RAM_LOCK 278 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 279 /* Initial L1 address */ 280 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 281 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 282 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 283 /* Size of used area in RAM */ 284 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 285 286 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 287 GENERATED_GBL_DATA_SIZE) 288 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 289 290 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ 291 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 292 293 #define CONFIG_SYS_PMC_BASE 0xff980000 294 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 295 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 296 BR_PS_8 | BR_V) 297 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 298 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 299 OR_GPCM_EAD) 300 301 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 302 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 303 #ifdef CONFIG_NAND_FSL_ELBC 304 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 305 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 306 #endif 307 308 /* Serial Port - controlled on board with jumper J8 309 * open - index 2 310 * shorted - index 1 311 */ 312 #define CONFIG_CONS_INDEX 1 313 #undef CONFIG_SERIAL_SOFTWARE_FIFO 314 #define CONFIG_SYS_NS16550_SERIAL 315 #define CONFIG_SYS_NS16550_REG_SIZE 1 316 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 317 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 318 #define CONFIG_NS16550_MIN_FUNCTIONS 319 #endif 320 321 #define CONFIG_SYS_BAUDRATE_TABLE \ 322 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 323 324 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 325 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 326 327 /* I2C */ 328 #define CONFIG_SYS_I2C 329 #define CONFIG_SYS_I2C_FSL 330 #define CONFIG_SYS_FSL_I2C_SPEED 400000 331 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 332 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 333 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 334 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 335 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 336 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 337 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 338 339 #define CONFIG_RTC_DS1337 340 #define CONFIG_SYS_RTC_DS1337_NOOSC 341 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 342 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 343 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C 344 #define CONFIG_SYS_I2C_IDT6V49205B 0x69 345 346 /* 347 * eSPI - Enhanced SPI 348 */ 349 #define CONFIG_HARD_SPI 350 351 #define CONFIG_SF_DEFAULT_SPEED 10000000 352 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 353 354 #if defined(CONFIG_PCI) 355 /* 356 * General PCI 357 * Memory space is mapped 1-1, but I/O space must start from 0. 358 */ 359 360 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 361 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" 362 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 363 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 364 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 365 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 366 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 367 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 368 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 369 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 370 371 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 372 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" 373 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 374 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 375 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 376 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 377 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 378 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 379 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 380 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 381 382 #define CONFIG_CMD_PCI 383 384 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 385 #define CONFIG_DOS_PARTITION 386 #endif /* CONFIG_PCI */ 387 388 /* 389 * Environment 390 */ 391 #ifdef CONFIG_ENV_FIT_UCBOOT 392 393 #define CONFIG_ENV_IS_IN_FLASH 394 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) 395 #define CONFIG_ENV_SIZE 0x20000 396 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 397 398 #else 399 400 #define CONFIG_ENV_SPI_BUS 0 401 #define CONFIG_ENV_SPI_CS 0 402 #define CONFIG_ENV_SPI_MAX_HZ 10000000 403 #define CONFIG_ENV_SPI_MODE 0 404 405 #ifdef CONFIG_RAMBOOT_SPIFLASH 406 407 #define CONFIG_ENV_IS_IN_SPI_FLASH 408 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */ 409 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */ 410 #define CONFIG_ENV_SECT_SIZE 0x1000 411 412 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 413 /* Address and size of Redundant Environment Sector */ 414 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 415 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 416 #endif 417 418 #elif defined(CONFIG_RAMBOOT_SDCARD) 419 #define CONFIG_ENV_IS_IN_MMC 420 #define CONFIG_FSL_FIXED_MMC_LOCATION 421 #define CONFIG_ENV_SIZE 0x2000 422 #define CONFIG_SYS_MMC_ENV_DEV 0 423 424 #elif defined(CONFIG_SYS_RAMBOOT) 425 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 426 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 427 #define CONFIG_ENV_SIZE 0x2000 428 429 #else 430 #define CONFIG_ENV_IS_IN_FLASH 431 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE) 432 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 433 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 434 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000) 435 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 436 /* Address and size of Redundant Environment Sector */ 437 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 438 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 439 #endif 440 441 #endif 442 443 #endif /* CONFIG_ENV_FIT_UCBOOT */ 444 445 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 446 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 447 448 /* 449 * Command line configuration. 450 */ 451 #define CONFIG_CMD_IRQ 452 #define CONFIG_CMD_DATE 453 #define CONFIG_CMD_IRQ 454 #define CONFIG_CMD_REGINFO 455 #define CONFIG_CMD_ERRATA 456 #define CONFIG_CMD_CRAMFS 457 458 /* 459 * USB 460 */ 461 #define CONFIG_HAS_FSL_DR_USB 462 463 #if defined(CONFIG_HAS_FSL_DR_USB) 464 #define CONFIG_USB_EHCI 465 466 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 467 468 #ifdef CONFIG_USB_EHCI 469 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 470 #define CONFIG_USB_EHCI_FSL 471 #endif 472 #endif 473 474 #undef CONFIG_WATCHDOG /* watchdog disabled */ 475 476 #ifdef CONFIG_MMC 477 #define CONFIG_FSL_ESDHC 478 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 479 #define CONFIG_MMC_SPI 480 #define CONFIG_CMD_MMC_SPI 481 #define CONFIG_GENERIC_MMC 482 #endif 483 484 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA) 485 #define CONFIG_DOS_PARTITION 486 #endif 487 488 /* Misc Extra Settings */ 489 #undef CONFIG_WATCHDOG /* watchdog disabled */ 490 491 /* 492 * Miscellaneous configurable options 493 */ 494 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 495 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 496 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 497 #if defined(CONFIG_CMD_KGDB) 498 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 499 #else 500 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 501 #endif 502 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 503 /* Print Buffer Size */ 504 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 505 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 506 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ 507 508 /* 509 * For booting Linux, the board info and command line data 510 * have to be in the first 64 MB of memory, since this is 511 * the maximum mapped by the Linux kernel during initialization. 512 */ 513 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 514 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 515 516 #if defined(CONFIG_CMD_KGDB) 517 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 518 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 519 #endif 520 521 /* 522 * Environment Configuration 523 */ 524 525 #if defined(CONFIG_TSEC_ENET) 526 527 #if defined(CONFIG_UCP1020_REV_1_2) 528 #define CONFIG_PHY_MICREL_KSZ9021 529 #elif defined(CONFIG_UCP1020_REV_1_3) 530 #define CONFIG_PHY_MICREL_KSZ9031 531 #else 532 #error "UCP1020 module revision is not defined !!!" 533 #endif 534 535 #define CONFIG_BOOTP_SERVERIP 536 537 #define CONFIG_MII /* MII PHY management */ 538 #define CONFIG_TSEC1_NAME "eTSEC1" 539 #define CONFIG_TSEC2_NAME "eTSEC2" 540 #define CONFIG_TSEC3_NAME "eTSEC3" 541 542 #define TSEC1_PHY_ADDR 4 543 #define TSEC2_PHY_ADDR 0 544 #define TSEC2_PHY_ADDR_SGMII 0x00 545 #define TSEC3_PHY_ADDR 6 546 547 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 548 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 549 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 550 551 #define TSEC1_PHYIDX 0 552 #define TSEC2_PHYIDX 0 553 #define TSEC3_PHYIDX 0 554 555 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 556 557 #endif 558 559 #define CONFIG_HOSTNAME UCP1020 560 #define CONFIG_ROOTPATH "/opt/nfsroot" 561 #define CONFIG_BOOTFILE "uImage" 562 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 563 564 /* default location for tftp and bootm */ 565 #define CONFIG_LOADADDR 1000000 566 567 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 568 569 #define CONFIG_BAUDRATE 115200 570 571 #if defined(CONFIG_DONGLE) 572 573 #define CONFIG_EXTRA_ENV_SETTINGS \ 574 "bootcmd=run prog_spi_mbrbootcramfs\0" \ 575 "bootfile=uImage\0" \ 576 "consoledev=ttyS0\0" \ 577 "cramfsfile=image.cramfs\0" \ 578 "dtbaddr=0x00c00000\0" \ 579 "dtbfile=image.dtb\0" \ 580 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 581 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 582 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 583 "fileaddr=0x01000000\0" \ 584 "filesize=0x00080000\0" \ 585 "flashmbr=sf probe 0; " \ 586 "tftp $loadaddr $mbr; " \ 587 "sf erase $mbr_offset +$filesize; " \ 588 "sf write $loadaddr $mbr_offset $filesize\0" \ 589 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 590 "protect off $nor_recoveryaddr +$filesize; " \ 591 "erase $nor_recoveryaddr +$filesize; " \ 592 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 593 "protect on $nor_recoveryaddr +$filesize\0 " \ 594 "flashuboot=tftp $ubootaddr $ubootfile; " \ 595 "protect off $nor_ubootaddr +$filesize; " \ 596 "erase $nor_ubootaddr +$filesize; " \ 597 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 598 "protect on $nor_ubootaddr +$filesize\0 " \ 599 "flashworking=tftp $workingaddr $cramfsfile; " \ 600 "protect off $nor_workingaddr +$filesize; " \ 601 "erase $nor_workingaddr +$filesize; " \ 602 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 603 "protect on $nor_workingaddr +$filesize\0 " \ 604 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 605 "kerneladdr=0x01100000\0" \ 606 "kernelfile=uImage\0" \ 607 "loadaddr=0x01000000\0" \ 608 "mbr=uCP1020d.mbr\0" \ 609 "mbr_offset=0x00000000\0" \ 610 "mmbr=uCP1020Quiet.mbr\0" \ 611 "mmcpart=0:2\0" \ 612 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 613 "mmc erase 1 1; " \ 614 "mmc write $loadaddr 1 1\0" \ 615 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ 616 "mmc erase 0x40 0x400; " \ 617 "mmc write $loadaddr 0x40 0x400\0" \ 618 "netdev=eth0\0" \ 619 "nor_recoveryaddr=0xEC0A0000\0" \ 620 "nor_ubootaddr=0xEFF80000\0" \ 621 "nor_workingaddr=0xECFA0000\0" \ 622 "norbootrecovery=setenv bootargs $recoverybootargs" \ 623 " console=$consoledev,$baudrate $othbootargs; " \ 624 "run norloadrecovery; " \ 625 "bootm $kerneladdr - $dtbaddr\0" \ 626 "norbootworking=setenv bootargs $workingbootargs" \ 627 " console=$consoledev,$baudrate $othbootargs; " \ 628 "run norloadworking; " \ 629 "bootm $kerneladdr - $dtbaddr\0" \ 630 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 631 "setenv cramfsaddr $nor_recoveryaddr; " \ 632 "cramfsload $dtbaddr $dtbfile; " \ 633 "cramfsload $kerneladdr $kernelfile\0" \ 634 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 635 "setenv cramfsaddr $nor_workingaddr; " \ 636 "cramfsload $dtbaddr $dtbfile; " \ 637 "cramfsload $kerneladdr $kernelfile\0" \ 638 "prog_spi_mbr=run spi__mbr\0" \ 639 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ 640 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ 641 "run spi__cramfs\0" \ 642 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 643 " console=$consoledev,$baudrate $othbootargs; " \ 644 "tftp $rootfsaddr $rootfsfile; " \ 645 "tftp $loadaddr $kernelfile; " \ 646 "tftp $dtbaddr $dtbfile; " \ 647 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 648 "ramdisk_size=120000\0" \ 649 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 650 "recoveryaddr=0x02F00000\0" \ 651 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 652 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 653 "mw.l 0xffe0f008 0x00400000\0" \ 654 "rootfsaddr=0x02F00000\0" \ 655 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 656 "rootpath=/opt/nfsroot\0" \ 657 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 658 "protect off 0xeC000000 +$filesize; " \ 659 "erase 0xEC000000 +$filesize; " \ 660 "cp.b $loadaddr 0xEC000000 $filesize; " \ 661 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 662 "protect on 0xeC000000 +$filesize\0" \ 663 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 664 "protect off 0xeFF80000 +$filesize; " \ 665 "erase 0xEFF80000 +$filesize; " \ 666 "cp.b $loadaddr 0xEFF80000 $filesize; " \ 667 "cmp.b $loadaddr 0xEFF80000 $filesize; " \ 668 "protect on 0xeFF80000 +$filesize\0" \ 669 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ 670 "sf probe 0; sf erase 0x8000 +$filesize; " \ 671 "sf write $loadaddr 0x8000 $filesize\0" \ 672 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ 673 "protect off 0xec0a0000 +$filesize; " \ 674 "erase 0xeC0A0000 +$filesize; " \ 675 "cp.b $loadaddr 0xeC0A0000 $filesize; " \ 676 "protect on 0xec0a0000 +$filesize\0" \ 677 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 678 "sf probe 1; sf erase 0 +$filesize; " \ 679 "sf write $loadaddr 0 $filesize\0" \ 680 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 681 "sf probe 0; sf erase 0 +$filesize; " \ 682 "sf write $loadaddr 0 $filesize\0" \ 683 "tftpflash=tftpboot $loadaddr $uboot; " \ 684 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 685 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 686 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 687 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 688 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 689 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 690 "ubootaddr=0x01000000\0" \ 691 "ubootfile=u-boot.bin\0" \ 692 "ubootd=u-boot4dongle.bin\0" \ 693 "upgrade=run flashworking\0" \ 694 "usb_phy_type=ulpi\0 " \ 695 "workingaddr=0x02F00000\0" \ 696 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 697 698 #else 699 700 #if defined(CONFIG_UCP1020T1) 701 702 #define CONFIG_EXTRA_ENV_SETTINGS \ 703 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ 704 "bootfile=uImage\0" \ 705 "consoledev=ttyS0\0" \ 706 "cramfsfile=image.cramfs\0" \ 707 "dtbaddr=0x00c00000\0" \ 708 "dtbfile=image.dtb\0" \ 709 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 710 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 711 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 712 "fileaddr=0x01000000\0" \ 713 "filesize=0x00080000\0" \ 714 "flashmbr=sf probe 0; " \ 715 "tftp $loadaddr $mbr; " \ 716 "sf erase $mbr_offset +$filesize; " \ 717 "sf write $loadaddr $mbr_offset $filesize\0" \ 718 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 719 "protect off $nor_recoveryaddr +$filesize; " \ 720 "erase $nor_recoveryaddr +$filesize; " \ 721 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 722 "protect on $nor_recoveryaddr +$filesize\0 " \ 723 "flashuboot=tftp $ubootaddr $ubootfile; " \ 724 "protect off $nor_ubootaddr +$filesize; " \ 725 "erase $nor_ubootaddr +$filesize; " \ 726 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 727 "protect on $nor_ubootaddr +$filesize\0 " \ 728 "flashworking=tftp $workingaddr $cramfsfile; " \ 729 "protect off $nor_workingaddr +$filesize; " \ 730 "erase $nor_workingaddr +$filesize; " \ 731 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 732 "protect on $nor_workingaddr +$filesize\0 " \ 733 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 734 "kerneladdr=0x01100000\0" \ 735 "kernelfile=uImage\0" \ 736 "loadaddr=0x01000000\0" \ 737 "mbr=uCP1020.mbr\0" \ 738 "mbr_offset=0x00000000\0" \ 739 "netdev=eth0\0" \ 740 "nor_recoveryaddr=0xEC0A0000\0" \ 741 "nor_ubootaddr=0xEFF80000\0" \ 742 "nor_workingaddr=0xECFA0000\0" \ 743 "norbootrecovery=setenv bootargs $recoverybootargs" \ 744 " console=$consoledev,$baudrate $othbootargs; " \ 745 "run norloadrecovery; " \ 746 "bootm $kerneladdr - $dtbaddr\0" \ 747 "norbootworking=setenv bootargs $workingbootargs" \ 748 " console=$consoledev,$baudrate $othbootargs; " \ 749 "run norloadworking; " \ 750 "bootm $kerneladdr - $dtbaddr\0" \ 751 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 752 "setenv cramfsaddr $nor_recoveryaddr; " \ 753 "cramfsload $dtbaddr $dtbfile; " \ 754 "cramfsload $kerneladdr $kernelfile\0" \ 755 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 756 "setenv cramfsaddr $nor_workingaddr; " \ 757 "cramfsload $dtbaddr $dtbfile; " \ 758 "cramfsload $kerneladdr $kernelfile\0" \ 759 "othbootargs=quiet\0" \ 760 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 761 " console=$consoledev,$baudrate $othbootargs; " \ 762 "tftp $rootfsaddr $rootfsfile; " \ 763 "tftp $loadaddr $kernelfile; " \ 764 "tftp $dtbaddr $dtbfile; " \ 765 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 766 "ramdisk_size=120000\0" \ 767 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 768 "recoveryaddr=0x02F00000\0" \ 769 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 770 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 771 "mw.l 0xffe0f008 0x00400000\0" \ 772 "rootfsaddr=0x02F00000\0" \ 773 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 774 "rootpath=/opt/nfsroot\0" \ 775 "silent=1\0" \ 776 "tftpflash=tftpboot $loadaddr $uboot; " \ 777 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 778 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 779 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 780 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 781 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 782 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 783 "ubootaddr=0x01000000\0" \ 784 "ubootfile=u-boot.bin\0" \ 785 "upgrade=run flashworking\0" \ 786 "workingaddr=0x02F00000\0" \ 787 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 788 789 #else /* For Arcturus Modules */ 790 791 #define CONFIG_EXTRA_ENV_SETTINGS \ 792 "bootcmd=run norkernel\0" \ 793 "bootfile=uImage\0" \ 794 "consoledev=ttyS0\0" \ 795 "dtbaddr=0x00c00000\0" \ 796 "dtbfile=image.dtb\0" \ 797 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 798 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 799 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 800 "fileaddr=0x01000000\0" \ 801 "filesize=0x00080000\0" \ 802 "flashmbr=sf probe 0; " \ 803 "tftp $loadaddr $mbr; " \ 804 "sf erase $mbr_offset +$filesize; " \ 805 "sf write $loadaddr $mbr_offset $filesize\0" \ 806 "flashuboot=tftp $loadaddr $ubootfile; " \ 807 "protect off $nor_ubootaddr0 +$filesize; " \ 808 "erase $nor_ubootaddr0 +$filesize; " \ 809 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ 810 "protect on $nor_ubootaddr0 +$filesize; " \ 811 "protect off $nor_ubootaddr1 +$filesize; " \ 812 "erase $nor_ubootaddr1 +$filesize; " \ 813 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ 814 "protect on $nor_ubootaddr1 +$filesize\0 " \ 815 "format0=protect off $part0base +$part0size; " \ 816 "erase $part0base +$part0size\0" \ 817 "format1=protect off $part1base +$part1size; " \ 818 "erase $part1base +$part1size\0" \ 819 "format2=protect off $part2base +$part2size; " \ 820 "erase $part2base +$part2size\0" \ 821 "format3=protect off $part3base +$part3size; " \ 822 "erase $part3base +$part3size\0" \ 823 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 824 "kerneladdr=0x01100000\0" \ 825 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ 826 "kernelfile=uImage\0" \ 827 "loadaddr=0x01000000\0" \ 828 "mbr=uCP1020.mbr\0" \ 829 "mbr_offset=0x00000000\0" \ 830 "netdev=eth0\0" \ 831 "nor_ubootaddr0=0xEC000000\0" \ 832 "nor_ubootaddr1=0xEFF80000\0" \ 833 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ 834 "run norkernelload; " \ 835 "bootm $kerneladdr - $dtbaddr\0" \ 836 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ 837 "setenv cramfsaddr $part0base; " \ 838 "cramfsload $dtbaddr $dtbfile; " \ 839 "cramfsload $kerneladdr $kernelfile\0" \ 840 "part0base=0xEC100000\0" \ 841 "part0size=0x00700000\0" \ 842 "part1base=0xEC800000\0" \ 843 "part1size=0x02000000\0" \ 844 "part2base=0xEE800000\0" \ 845 "part2size=0x00800000\0" \ 846 "part3base=0xEF000000\0" \ 847 "part3size=0x00F80000\0" \ 848 "partENVbase=0xEC080000\0" \ 849 "partENVsize=0x00080000\0" \ 850 "program0=tftp part0-000000.bin; " \ 851 "protect off $part0base +$filesize; " \ 852 "erase $part0base +$filesize; " \ 853 "cp.b $loadaddr $part0base $filesize; " \ 854 "echo Verifying...; " \ 855 "cmp.b $loadaddr $part0base $filesize\0" \ 856 "program1=tftp part1-000000.bin; " \ 857 "protect off $part1base +$filesize; " \ 858 "erase $part1base +$filesize; " \ 859 "cp.b $loadaddr $part1base $filesize; " \ 860 "echo Verifying...; " \ 861 "cmp.b $loadaddr $part1base $filesize\0" \ 862 "program2=tftp part2-000000.bin; " \ 863 "protect off $part2base +$filesize; " \ 864 "erase $part2base +$filesize; " \ 865 "cp.b $loadaddr $part2base $filesize; " \ 866 "echo Verifying...; " \ 867 "cmp.b $loadaddr $part2base $filesize\0" \ 868 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 869 " console=$consoledev,$baudrate $othbootargs; " \ 870 "tftp $rootfsaddr $rootfsfile; " \ 871 "tftp $loadaddr $kernelfile; " \ 872 "tftp $dtbaddr $dtbfile; " \ 873 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 874 "ramdisk_size=120000\0" \ 875 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 876 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 877 "mw.l 0xffe0f008 0x00400000\0" \ 878 "rootfsaddr=0x02F00000\0" \ 879 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 880 "rootpath=/opt/nfsroot\0" \ 881 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 882 "sf probe 0; sf erase 0 +$filesize; " \ 883 "sf write $loadaddr 0 $filesize\0" \ 884 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 885 "protect off 0xeC000000 +$filesize; " \ 886 "erase 0xEC000000 +$filesize; " \ 887 "cp.b $loadaddr 0xEC000000 $filesize; " \ 888 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 889 "protect on 0xeC000000 +$filesize\0" \ 890 "tftpflash=tftpboot $loadaddr $uboot; " \ 891 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 892 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 893 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 894 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 895 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 896 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 897 "ubootfile=u-boot.bin\0" \ 898 "upgrade=run flashuboot\0" \ 899 "usb_phy_type=ulpi\0 " \ 900 "boot_nfs= " \ 901 "setenv bootargs root=/dev/nfs rw " \ 902 "nfsroot=$serverip:$rootpath " \ 903 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 904 "console=$consoledev,$baudrate $othbootargs;" \ 905 "tftp $loadaddr $bootfile;" \ 906 "tftp $fdtaddr $fdtfile;" \ 907 "bootm $loadaddr - $fdtaddr\0" \ 908 "boot_hd = " \ 909 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 910 "console=$consoledev,$baudrate $othbootargs;" \ 911 "usb start;" \ 912 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 913 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 914 "bootm $loadaddr - $fdtaddr\0" \ 915 "boot_usb_fat = " \ 916 "setenv bootargs root=/dev/ram rw " \ 917 "console=$consoledev,$baudrate $othbootargs " \ 918 "ramdisk_size=$ramdisk_size;" \ 919 "usb start;" \ 920 "fatload usb 0:2 $loadaddr $bootfile;" \ 921 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 922 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 923 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 924 "boot_usb_ext2 = " \ 925 "setenv bootargs root=/dev/ram rw " \ 926 "console=$consoledev,$baudrate $othbootargs " \ 927 "ramdisk_size=$ramdisk_size;" \ 928 "usb start;" \ 929 "ext2load usb 0:4 $loadaddr $bootfile;" \ 930 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 931 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 932 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 933 "boot_nor = " \ 934 "setenv bootargs root=/dev/$jffs2nor rw " \ 935 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 936 "bootm $norbootaddr - $norfdtaddr\0 " \ 937 "boot_ram = " \ 938 "setenv bootargs root=/dev/ram rw " \ 939 "console=$consoledev,$baudrate $othbootargs " \ 940 "ramdisk_size=$ramdisk_size;" \ 941 "tftp $ramdiskaddr $ramdiskfile;" \ 942 "tftp $loadaddr $bootfile;" \ 943 "tftp $fdtaddr $fdtfile;" \ 944 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" 945 946 #endif 947 #endif 948 949 #endif /* __CONFIG_H */ 950