1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * TQM8349 board configuration file 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 #define DEBUG 32 #undef DEBUG 33 34 /* 35 * High Level Configuration Options 36 */ 37 #define CONFIG_E300 1 /* E300 Family */ 38 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 39 #define CONFIG_MPC834X 1 /* MPC834X specific */ 40 #define CONFIG_TQM834X 1 /* TQM834X board specific */ 41 42 /* IMMR Base Addres Register, use Freescale default: 0xff400000 */ 43 #define CFG_IMMRBAR 0xff400000 44 45 /* System clock. Primary input clock when in PCI host mode */ 46 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ 47 48 /* 49 * Local Bus LCRR 50 * LCRR: DLL bypass, Clock divider is 8 51 * 52 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz 53 * 54 * External Local Bus rate is 55 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 56 */ 57 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) 58 59 /* board pre init: do not call, nothing to do */ 60 #undef CONFIG_BOARD_EARLY_INIT_F 61 62 /* detect the number of flash banks */ 63 #define CONFIG_BOARD_EARLY_INIT_R 64 65 /* 66 * DDR Setup 67 */ 68 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 69 #define CFG_SDRAM_BASE CFG_DDR_BASE 70 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 71 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 72 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 73 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 74 75 #undef CFG_DRAM_TEST /* memory test, takes time */ 76 #define CFG_MEMTEST_START 0x00000000 /* memtest region */ 77 #define CFG_MEMTEST_END 0x00100000 78 79 /* 80 * FLASH on the Local Bus 81 */ 82 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 83 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 84 #undef CFG_FLASH_CHECKSUM 85 #define CFG_FLASH_BASE 0x80000000 /* start of FLASH */ 86 87 /* buffered writes in the AMD chip set is not supported yet */ 88 #undef CFG_FLASH_USE_BUFFER_WRITE 89 90 /* 91 * FLASH bank number detection 92 */ 93 94 /* 95 * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash 96 * banks has to be determined at runtime and stored in a gloabl variable 97 * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only 98 * used insted of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and 99 * should be made sufficiently large to accomodate the number of banks that 100 * might acutally be detected. Since most (all?) Flash related functions use 101 * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is 102 * defined as tqm834x_num_flash_banks. 103 */ 104 #define CFG_MAX_FLASH_BANKS_DETECT 2 105 #ifndef __ASSEMBLY__ 106 extern int tqm834x_num_flash_banks; 107 #endif 108 #define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks) 109 110 #define CFG_MAX_FLASH_SECT 512 /* max sectors per device */ 111 112 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ 113 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA) | \ 114 BR_MS_GPCM | BR_PS_32 | BR_V) 115 116 /* FLASH timing (0x0000_0c54) */ 117 #define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \ 118 OR_GPCM_SCY_5 | OR_GPCM_TRLX) 119 120 #define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ 121 122 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) 123 124 #define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */ 125 126 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ 127 128 /* disable remaining mappings */ 129 #define CFG_BR1_PRELIM 0x00000000 130 #define CFG_OR1_PRELIM 0x00000000 131 #define CFG_LBLAWBAR1_PRELIM 0x00000000 132 #define CFG_LBLAWAR1_PRELIM 0x00000000 133 134 #define CFG_BR2_PRELIM 0x00000000 135 #define CFG_OR2_PRELIM 0x00000000 136 #define CFG_LBLAWBAR2_PRELIM 0x00000000 137 #define CFG_LBLAWAR2_PRELIM 0x00000000 138 139 #define CFG_BR3_PRELIM 0x00000000 140 #define CFG_OR3_PRELIM 0x00000000 141 #define CFG_LBLAWBAR3_PRELIM 0x00000000 142 #define CFG_LBLAWAR3_PRELIM 0x00000000 143 144 #define CFG_BR4_PRELIM 0x00000000 145 #define CFG_OR4_PRELIM 0x00000000 146 #define CFG_LBLAWBAR4_PRELIM 0x00000000 147 #define CFG_LBLAWAR4_PRELIM 0x00000000 148 149 #define CFG_BR5_PRELIM 0x00000000 150 #define CFG_OR5_PRELIM 0x00000000 151 #define CFG_LBLAWBAR5_PRELIM 0x00000000 152 #define CFG_LBLAWAR5_PRELIM 0x00000000 153 154 #define CFG_BR6_PRELIM 0x00000000 155 #define CFG_OR6_PRELIM 0x00000000 156 #define CFG_LBLAWBAR6_PRELIM 0x00000000 157 #define CFG_LBLAWAR6_PRELIM 0x00000000 158 159 #define CFG_BR7_PRELIM 0x00000000 160 #define CFG_OR7_PRELIM 0x00000000 161 #define CFG_LBLAWBAR7_PRELIM 0x00000000 162 #define CFG_LBLAWAR7_PRELIM 0x00000000 163 164 /* 165 * Monitor config 166 */ 167 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 168 169 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 170 #define CFG_RAMBOOT 171 #else 172 #undef CFG_RAMBOOT 173 #endif 174 175 #define CONFIG_L1_INIT_RAM 176 #define CFG_INIT_RAM_LOCK 1 177 #define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 178 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 179 180 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 181 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 182 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 183 184 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 185 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 186 187 /* 188 * Serial Port 189 */ 190 #define CONFIG_CONS_INDEX 1 191 #undef CONFIG_SERIAL_SOFTWARE_FIFO 192 #define CFG_NS16550 193 #define CFG_NS16550_SERIAL 194 #define CFG_NS16550_REG_SIZE 1 195 #define CFG_NS16550_CLK get_bus_freq(0) 196 197 #define CFG_BAUDRATE_TABLE \ 198 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 199 200 #define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) 201 #define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) 202 203 /* 204 * I2C 205 */ 206 #define CONFIG_HARD_I2C /* I2C with hardware support */ 207 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 208 #define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */ 209 #define CFG_I2C_SLAVE 0x7F /* slave address */ 210 #define CFG_I2C_OFFSET 0x3000 211 212 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 213 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 214 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 215 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */ 216 #define CFG_EEPROM_PAGE_WRITE_ENABLE 217 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 218 #define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ 219 220 /* I2C RTC */ 221 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 222 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 223 224 /* I2C SYSMON (LM75) */ 225 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ 226 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 227 #define CFG_DTT_MAX_TEMP 70 228 #define CFG_DTT_LOW_TEMP -30 229 #define CFG_DTT_HYSTERESIS 3 230 231 /* 232 * TSEC 233 */ 234 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 235 #define CONFIG_MII 236 237 #define CFG_TSEC1_OFFSET 0x24000 238 #define CFG_TSEC1 (CFG_IMMRBAR + CFG_TSEC1_OFFSET) 239 #define CFG_TSEC2_OFFSET 0x25000 240 #define CFG_TSEC2 (CFG_IMMRBAR + CFG_TSEC2_OFFSET) 241 242 #if defined(CONFIG_TSEC_ENET) 243 244 #ifndef CONFIG_NET_MULTI 245 #define CONFIG_NET_MULTI 246 #endif 247 248 #define CONFIG_MPC83XX_TSEC1 1 249 #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" 250 #define CONFIG_MPC83XX_TSEC2 1 251 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" 252 #define TSEC1_PHY_ADDR 0 253 #define TSEC2_PHY_ADDR 1 254 #define TSEC1_PHYIDX 0 255 #define TSEC2_PHYIDX 0 256 257 /* Options are: TSEC[0-1] */ 258 #define CONFIG_ETHPRIME "TSEC0" 259 260 #endif /* CONFIG_TSEC_ENET */ 261 262 /* 263 * General PCI 264 * Addresses are mapped 1-1. 265 */ 266 #define CONFIG_PCI 267 268 #if defined(CONFIG_PCI) 269 270 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 271 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 272 273 /* PCI1 host bridge */ 274 #define CFG_PCI1_MEM_BASE 0xc0000000 275 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 276 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 277 #define CFG_PCI1_IO_BASE 0xe2000000 278 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 279 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 280 281 282 #undef CONFIG_EEPRO100 283 #undef CONFIG_TULIP 284 285 #if !defined(CONFIG_PCI_PNP) 286 #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE 287 #define PCI_ENET0_MEMADDR CFG_PCI1_MEM_BASE 288 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 289 #endif 290 291 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 292 293 #endif /* CONFIG_PCI */ 294 295 /* 296 * Environment 297 */ 298 #define CONFIG_ENV_OVERWRITE 299 300 #ifndef CFG_RAMBOOT 301 #define CFG_ENV_IS_IN_FLASH 1 302 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 303 #define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ 304 #define CFG_ENV_SIZE 0x2000 305 #else 306 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 307 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 308 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 309 #define CFG_ENV_SIZE 0x2000 310 #endif 311 312 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 313 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 314 315 /* Common commands */ 316 #define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\ 317 | CFG_CMD_PING | CFG_CMD_EEPROM \ 318 | CFG_CMD_MII | CFG_CMD_JFFS2 319 320 #if defined(CFG_RAMBOOT) 321 322 #if defined(CONFIG_PCI) 323 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \ 324 | CFG_CMD_TQM8349_COMMON) \ 325 & \ 326 ~(CFG_CMD_ENV | CFG_CMD_LOADS)) 327 #else 328 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 329 | CFG_CMD_TQM8349_COMMON) \ 330 & \ 331 ~(CFG_CMD_ENV | CFG_CMD_LOADS)) 332 #endif 333 334 #else /* CFG_RAMBOOT */ 335 336 #if defined(CONFIG_PCI) 337 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \ 338 | CFG_CMD_TQM8349_COMMON) 339 #else 340 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 341 | CFG_CMD_TQM8349_COMMON) 342 #endif 343 344 #endif /* CFG_RAMBOOT */ 345 346 #include <cmd_confdefs.h> 347 348 /* 349 * Miscellaneous configurable options 350 */ 351 #define CFG_LONGHELP /* undef to save memory */ 352 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 353 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 354 355 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 356 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 357 #else 358 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 359 #endif 360 361 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 362 #define CFG_MAXARGS 16 /* max number of command args */ 363 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 364 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 365 366 #undef CONFIG_WATCHDOG /* watchdog disabled */ 367 368 /* 369 * For booting Linux, the board info and command line data 370 * have to be in the first 8 MB of memory, since this is 371 * the maximum mapped by the Linux kernel during initialization. 372 */ 373 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 374 375 /* 376 * Cache Configuration 377 */ 378 #define CFG_DCACHE_SIZE 32768 379 #define CFG_CACHELINE_SIZE 32 380 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 381 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 382 #endif 383 384 #define CFG_HRCW_LOW (\ 385 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 386 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 387 HRCWL_CSB_TO_CLKIN_4X1 |\ 388 HRCWL_VCO_1X2 |\ 389 HRCWL_CORE_TO_CSB_2X1) 390 391 #if defined(PCI_64BIT) 392 #define CFG_HRCW_HIGH (\ 393 HRCWH_PCI_HOST |\ 394 HRCWH_64_BIT_PCI |\ 395 HRCWH_PCI1_ARBITER_ENABLE |\ 396 HRCWH_PCI2_ARBITER_DISABLE |\ 397 HRCWH_CORE_ENABLE |\ 398 HRCWH_FROM_0X00000100 |\ 399 HRCWH_BOOTSEQ_DISABLE |\ 400 HRCWH_SW_WATCHDOG_DISABLE |\ 401 HRCWH_ROM_LOC_LOCAL_16BIT |\ 402 HRCWH_TSEC1M_IN_GMII |\ 403 HRCWH_TSEC2M_IN_GMII ) 404 #else 405 #define CFG_HRCW_HIGH (\ 406 HRCWH_PCI_HOST |\ 407 HRCWH_32_BIT_PCI |\ 408 HRCWH_PCI1_ARBITER_ENABLE |\ 409 HRCWH_PCI2_ARBITER_DISABLE |\ 410 HRCWH_CORE_ENABLE |\ 411 HRCWH_FROM_0X00000100 |\ 412 HRCWH_BOOTSEQ_DISABLE |\ 413 HRCWH_SW_WATCHDOG_DISABLE |\ 414 HRCWH_ROM_LOC_LOCAL_16BIT |\ 415 HRCWH_TSEC1M_IN_GMII |\ 416 HRCWH_TSEC2M_IN_GMII ) 417 #endif 418 419 /* i-cache and d-cache disabled */ 420 #define CFG_HID0_INIT 0x000000000 421 #define CFG_HID0_FINAL CFG_HID0_INIT 422 #define CFG_HID2 0x000000000 423 424 /* 425 * Internal Definitions 426 * 427 * Boot Flags 428 */ 429 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 430 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 431 432 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 433 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 434 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 435 #endif 436 437 /* 438 * Environment Configuration 439 */ 440 441 #if defined(CONFIG_TSEC_ENET) 442 #define CONFIG_ETHADDR D2:DA:5E:44:BC:29 443 #define CONFIG_HAS_ETH1 444 #define CONFIG_ETH1ADDR 1E:F3:40:21:92:53 445 #endif 446 447 #define CONFIG_IPADDR 192.168.205.1 448 449 #define CONFIG_HOSTNAME tqm8349 450 #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx 451 #define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage 452 453 #define CONFIG_SERVERIP 192.168.1.1 454 #define CONFIG_GATEWAYIP 192.168.1.1 455 #define CONFIG_NETMASK 255.255.255.0 456 457 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 458 459 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 460 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 461 462 #define CONFIG_BAUDRATE 115200 463 464 #define CONFIG_PREBOOT "echo;" \ 465 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ 466 "echo" 467 468 #undef CONFIG_BOOTARGS 469 470 #define CONFIG_EXTRA_ENV_SETTINGS \ 471 "netdev=eth0\0" \ 472 "hostname=tqm83xx\0" \ 473 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 474 "nfsroot=$(serverip):$(rootpath)\0" \ 475 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 476 "addip=setenv bootargs $(bootargs) " \ 477 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ 478 ":$(hostname):$(netdev):off panic=1\0" \ 479 "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ 480 "flash_nfs=run nfsargs addip addtty;" \ 481 "bootm $(kernel_addr)\0" \ 482 "flash_self=run ramargs addip addtty;" \ 483 "bootm $(kernel_addr) $(ramdisk_addr)\0" \ 484 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ 485 "bootm\0" \ 486 "rootpath=/opt/eldk/ppc_6xx\0" \ 487 "bootfile=/tftpboot/tqm83xx/uImage\0" \ 488 "kernel_addr=80060000\0" \ 489 "ramdisk_addr=80160000\0" \ 490 "load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \ 491 "update=protect off 80000000 8003ffff; " \ 492 "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \ 493 "upd=run load;run update\0" \ 494 "" 495 496 #define CONFIG_BOOTCOMMAND "run flash_self" 497 498 /* 499 * JFFS2 partitions 500 */ 501 /* mtdparts command line support */ 502 #define CONFIG_JFFS2_CMDLINE 503 #define MTDIDS_DEFAULT "nor0=TQM834x-0" 504 505 /* default mtd partition table */ 506 #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\ 507 "1m(kernel),2m(initrd),"\ 508 "-(user);"\ 509 510 #endif /* __CONFIG_H */ 511