1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * TQM8349 board configuration file 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 /* 32 * High Level Configuration Options 33 */ 34 #define CONFIG_E300 1 /* E300 Family */ 35 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 36 #define CONFIG_MPC834x 1 /* MPC834x specific */ 37 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 38 #define CONFIG_TQM834X 1 /* TQM834X board specific */ 39 40 #define CONFIG_SYS_TEXT_BASE 0x80000000 41 42 /* IMMR Base Address Register, use Freescale default: 0xff400000 */ 43 #define CONFIG_SYS_IMMR 0xff400000 44 45 /* System clock. Primary input clock when in PCI host mode */ 46 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ 47 48 /* 49 * Local Bus LCRR 50 * LCRR: DLL bypass, Clock divider is 8 51 * 52 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz 53 * 54 * External Local Bus rate is 55 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 56 */ 57 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 58 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 59 60 /* board pre init: do not call, nothing to do */ 61 #undef CONFIG_BOARD_EARLY_INIT_F 62 63 /* detect the number of flash banks */ 64 #define CONFIG_BOARD_EARLY_INIT_R 65 66 /* 67 * DDR Setup 68 */ 69 /* DDR is system memory*/ 70 #define CONFIG_SYS_DDR_BASE 0x00000000 71 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 72 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 73 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 74 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 75 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 76 77 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 78 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 79 #define CONFIG_SYS_MEMTEST_END 0x00100000 80 81 /* 82 * FLASH on the Local Bus 83 */ 84 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 85 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 86 #undef CONFIG_SYS_FLASH_CHECKSUM 87 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ 88 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ 89 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ 90 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 91 92 /* 93 * FLASH bank number detection 94 */ 95 96 /* 97 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of 98 * Flash banks has to be determined at runtime and stored in a gloabl variable 99 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is 100 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array 101 * flash_info, and should be made sufficiently large to accomodate the number 102 * of banks that might actually be detected. Since most (all?) Flash related 103 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on 104 * the board, it is defined as tqm834x_num_flash_banks. 105 */ 106 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 107 108 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ 109 110 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ 111 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \ 112 | BR_MS_GPCM \ 113 | BR_PS_32 \ 114 | BR_V) 115 116 /* FLASH timing (0x0000_0c54) */ 117 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \ 118 | OR_GPCM_ACS_DIV4 \ 119 | OR_GPCM_SCY_5 \ 120 | OR_GPCM_TRLX) 121 122 #define CONFIG_SYS_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ 123 124 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ 125 | CONFIG_SYS_OR_TIMING_FLASH) 126 127 /* 1 GiB window size (2^(size + 1)) */ 128 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D 129 130 /* Window base at flash base */ 131 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 132 133 /* disable remaining mappings */ 134 #define CONFIG_SYS_BR1_PRELIM 0x00000000 135 #define CONFIG_SYS_OR1_PRELIM 0x00000000 136 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 137 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 138 139 #define CONFIG_SYS_BR2_PRELIM 0x00000000 140 #define CONFIG_SYS_OR2_PRELIM 0x00000000 141 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 142 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 143 144 #define CONFIG_SYS_BR3_PRELIM 0x00000000 145 #define CONFIG_SYS_OR3_PRELIM 0x00000000 146 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 147 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 148 149 /* 150 * Monitor config 151 */ 152 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 153 154 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 155 # define CONFIG_SYS_RAMBOOT 156 #else 157 # undef CONFIG_SYS_RAMBOOT 158 #endif 159 160 #define CONFIG_SYS_INIT_RAM_LOCK 1 161 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 162 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 163 164 #define CONFIG_SYS_GBL_DATA_OFFSET \ 165 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 166 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 167 168 /* Reserve 384 kB = 3 sect. for Mon */ 169 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 170 /* Reserve 512 kB for malloc */ 171 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 172 173 /* 174 * Serial Port 175 */ 176 #define CONFIG_CONS_INDEX 1 177 #define CONFIG_SYS_NS16550 178 #define CONFIG_SYS_NS16550_SERIAL 179 #define CONFIG_SYS_NS16550_REG_SIZE 1 180 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 181 182 #define CONFIG_SYS_BAUDRATE_TABLE \ 183 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 184 185 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 186 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 187 188 /* 189 * I2C 190 */ 191 #define CONFIG_HARD_I2C /* I2C with hardware support */ 192 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 193 #define CONFIG_FSL_I2C 194 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */ 195 #define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */ 196 #define CONFIG_SYS_I2C_OFFSET 0x3000 197 198 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 199 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 200 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 201 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ 202 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 203 #define CONFIG_SYS_I2C_MULTI_EEPROMS /* more than one eeprom */ 204 205 /* I2C RTC */ 206 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 207 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 208 209 /* I2C SYSMON (LM75) */ 210 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ 211 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 212 #define CONFIG_SYS_DTT_MAX_TEMP 70 213 #define CONFIG_SYS_DTT_LOW_TEMP -30 214 #define CONFIG_SYS_DTT_HYSTERESIS 3 215 216 /* 217 * TSEC 218 */ 219 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 220 #define CONFIG_MII 221 222 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 223 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 224 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 225 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 226 227 #if defined(CONFIG_TSEC_ENET) 228 229 #define CONFIG_TSEC1 1 230 #define CONFIG_TSEC1_NAME "TSEC0" 231 #define CONFIG_TSEC2 1 232 #define CONFIG_TSEC2_NAME "TSEC1" 233 #define TSEC1_PHY_ADDR 2 234 #define TSEC2_PHY_ADDR 1 235 #define TSEC1_PHYIDX 0 236 #define TSEC2_PHYIDX 0 237 #define TSEC1_FLAGS TSEC_GIGABIT 238 #define TSEC2_FLAGS TSEC_GIGABIT 239 240 /* Options are: TSEC[0-1] */ 241 #define CONFIG_ETHPRIME "TSEC0" 242 243 #endif /* CONFIG_TSEC_ENET */ 244 245 /* 246 * General PCI 247 * Addresses are mapped 1-1. 248 */ 249 #define CONFIG_PCI 250 251 #if defined(CONFIG_PCI) 252 253 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 254 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 255 256 /* PCI1 host bridge */ 257 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 258 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 259 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 260 #define CONFIG_SYS_PCI1_MMIO_BASE \ 261 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 262 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 263 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 264 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 265 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 266 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ 267 268 #undef CONFIG_EEPRO100 269 #define CONFIG_EEPRO100 270 #undef CONFIG_TULIP 271 272 #if !defined(CONFIG_PCI_PNP) 273 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE 274 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE 275 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 276 #endif 277 278 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 279 280 #endif /* CONFIG_PCI */ 281 282 /* 283 * Environment 284 */ 285 #define CONFIG_ENV_IS_IN_FLASH 1 286 #define CONFIG_ENV_ADDR \ 287 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 288 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ 289 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ 290 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 291 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 292 293 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 294 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 295 296 /* 297 * BOOTP options 298 */ 299 #define CONFIG_BOOTP_BOOTFILESIZE 300 #define CONFIG_BOOTP_BOOTPATH 301 #define CONFIG_BOOTP_GATEWAY 302 #define CONFIG_BOOTP_HOSTNAME 303 304 305 /* 306 * Command line configuration. 307 */ 308 #include <config_cmd_default.h> 309 310 #define CONFIG_CMD_ASKENV 311 #define CONFIG_CMD_DATE 312 #define CONFIG_CMD_DHCP 313 #define CONFIG_CMD_DTT 314 #define CONFIG_CMD_EEPROM 315 #define CONFIG_CMD_I2C 316 #define CONFIG_CMD_NFS 317 #define CONFIG_CMD_JFFS2 318 #define CONFIG_CMD_MII 319 #define CONFIG_CMD_PING 320 #define CONFIG_CMD_REGINFO 321 #define CONFIG_CMD_SNTP 322 323 #if defined(CONFIG_PCI) 324 #define CONFIG_CMD_PCI 325 #endif 326 327 #if defined(CONFIG_SYS_RAMBOOT) 328 #undef CONFIG_CMD_SAVEENV 329 #undef CONFIG_CMD_LOADS 330 #endif 331 332 /* 333 * Miscellaneous configurable options 334 */ 335 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 336 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 337 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 338 339 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 340 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 341 342 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 343 #ifdef CONFIG_SYS_HUSH_PARSER 344 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 345 #endif 346 347 #if defined(CONFIG_CMD_KGDB) 348 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 349 #else 350 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 351 #endif 352 353 /* Print Buffer Size */ 354 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 355 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 356 /* Boot Argument Buffer Size */ 357 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 358 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 359 360 #undef CONFIG_WATCHDOG /* watchdog disabled */ 361 362 /* pass open firmware flat tree */ 363 #define CONFIG_OF_LIBFDT 1 364 #define CONFIG_OF_BOARD_SETUP 1 365 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 366 367 /* 368 * For booting Linux, the board info and command line data 369 * have to be in the first 256 MB of memory, since this is 370 * the maximum mapped by the Linux kernel during initialization. 371 */ 372 /* Initial Memory map for Linux */ 373 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 374 375 #define CONFIG_SYS_HRCW_LOW (\ 376 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 377 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 378 HRCWL_CSB_TO_CLKIN_4X1 |\ 379 HRCWL_VCO_1X2 |\ 380 HRCWL_CORE_TO_CSB_2X1) 381 382 #if defined(PCI_64BIT) 383 #define CONFIG_SYS_HRCW_HIGH (\ 384 HRCWH_PCI_HOST |\ 385 HRCWH_64_BIT_PCI |\ 386 HRCWH_PCI1_ARBITER_ENABLE |\ 387 HRCWH_PCI2_ARBITER_DISABLE |\ 388 HRCWH_CORE_ENABLE |\ 389 HRCWH_FROM_0X00000100 |\ 390 HRCWH_BOOTSEQ_DISABLE |\ 391 HRCWH_SW_WATCHDOG_DISABLE |\ 392 HRCWH_ROM_LOC_LOCAL_16BIT |\ 393 HRCWH_TSEC1M_IN_GMII |\ 394 HRCWH_TSEC2M_IN_GMII) 395 #else 396 #define CONFIG_SYS_HRCW_HIGH (\ 397 HRCWH_PCI_HOST |\ 398 HRCWH_32_BIT_PCI |\ 399 HRCWH_PCI1_ARBITER_ENABLE |\ 400 HRCWH_PCI2_ARBITER_DISABLE |\ 401 HRCWH_CORE_ENABLE |\ 402 HRCWH_FROM_0X00000100 |\ 403 HRCWH_BOOTSEQ_DISABLE |\ 404 HRCWH_SW_WATCHDOG_DISABLE |\ 405 HRCWH_ROM_LOC_LOCAL_16BIT |\ 406 HRCWH_TSEC1M_IN_GMII |\ 407 HRCWH_TSEC2M_IN_GMII) 408 #endif 409 410 /* System IO Config */ 411 #define CONFIG_SYS_SICRH 0 412 #define CONFIG_SYS_SICRL SICRL_LDP_A 413 414 /* i-cache and d-cache disabled */ 415 #define CONFIG_SYS_HID0_INIT 0x000000000 416 #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ 417 HID0_ENABLE_INSTRUCTION_CACHE) 418 #define CONFIG_SYS_HID2 HID2_HBE 419 420 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 421 422 /* DDR 0 - 512M */ 423 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 424 | BATL_PP_10 \ 425 | BATL_MEMCOHERENCE) 426 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 427 | BATU_BL_256M \ 428 | BATU_VS \ 429 | BATU_VP) 430 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 431 | BATL_PP_10 \ 432 | BATL_MEMCOHERENCE) 433 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 434 | BATU_BL_256M \ 435 | BATU_VS \ 436 | BATU_VP) 437 438 /* stack in DCACHE @ 512M (no backing mem) */ 439 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ 440 | BATL_PP_10 \ 441 | BATL_MEMCOHERENCE) 442 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ 443 | BATU_BL_128K \ 444 | BATU_VS \ 445 | BATU_VP) 446 447 /* PCI */ 448 #ifdef CONFIG_PCI 449 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ 450 | BATL_PP_10 \ 451 | BATL_MEMCOHERENCE) 452 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ 453 | BATU_BL_256M \ 454 | BATU_VS \ 455 | BATU_VP) 456 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ 457 | BATL_PP_10 \ 458 | BATL_MEMCOHERENCE \ 459 | BATL_GUARDEDSTORAGE) 460 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ 461 | BATU_BL_256M \ 462 | BATU_VS \ 463 | BATU_VP) 464 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ 465 | BATL_PP_10 \ 466 | BATL_CACHEINHIBIT \ 467 | BATL_GUARDEDSTORAGE) 468 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ 469 | BATU_BL_16M \ 470 | BATU_VS \ 471 | BATU_VP) 472 #else 473 #define CONFIG_SYS_IBAT3L (0) 474 #define CONFIG_SYS_IBAT3U (0) 475 #define CONFIG_SYS_IBAT4L (0) 476 #define CONFIG_SYS_IBAT4U (0) 477 #define CONFIG_SYS_IBAT5L (0) 478 #define CONFIG_SYS_IBAT5U (0) 479 #endif 480 481 /* IMMRBAR */ 482 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ 483 | BATL_PP_10 \ 484 | BATL_CACHEINHIBIT \ 485 | BATL_GUARDEDSTORAGE) 486 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ 487 | BATU_BL_1M \ 488 | BATU_VS \ 489 | BATU_VP) 490 491 /* FLASH */ 492 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ 493 | BATL_PP_10 \ 494 | BATL_CACHEINHIBIT \ 495 | BATL_GUARDEDSTORAGE) 496 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ 497 | BATU_BL_256M \ 498 | BATU_VS \ 499 | BATU_VP) 500 501 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 502 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 503 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 504 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 505 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 506 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 507 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 508 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 509 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 510 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 511 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 512 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 513 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 514 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 515 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 516 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 517 518 #if defined(CONFIG_CMD_KGDB) 519 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 520 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 521 #endif 522 523 /* 524 * Environment Configuration 525 */ 526 527 /* default location for tftp and bootm */ 528 #define CONFIG_LOADADDR 400000 529 530 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 531 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 532 533 #define CONFIG_BAUDRATE 115200 534 535 #define CONFIG_PREBOOT "echo;" \ 536 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 537 "echo" 538 539 #undef CONFIG_BOOTARGS 540 541 #define CONFIG_EXTRA_ENV_SETTINGS \ 542 "netdev=eth0\0" \ 543 "hostname=tqm834x\0" \ 544 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 545 "nfsroot=${serverip}:${rootpath}\0" \ 546 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 547 "addip=setenv bootargs ${bootargs} " \ 548 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 549 ":${hostname}:${netdev}:off panic=1\0" \ 550 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ 551 "flash_nfs_old=run nfsargs addip addcons;" \ 552 "bootm ${kernel_addr}\0" \ 553 "flash_nfs=run nfsargs addip addcons;" \ 554 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 555 "flash_self_old=run ramargs addip addcons;" \ 556 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 557 "flash_self=run ramargs addip addcons;" \ 558 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 559 "net_nfs_old=tftp 400000 ${bootfile};" \ 560 "run nfsargs addip addcons;bootm\0" \ 561 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 562 "tftp ${fdt_addr_r} ${fdt_file}; " \ 563 "run nfsargs addip addcons; " \ 564 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 565 "rootpath=/opt/eldk/ppc_6xx\0" \ 566 "bootfile=tqm834x/uImage\0" \ 567 "fdtfile=tqm834x/tqm834x.dtb\0" \ 568 "kernel_addr_r=400000\0" \ 569 "fdt_addr_r=600000\0" \ 570 "ramdisk_addr_r=800000\0" \ 571 "kernel_addr=800C0000\0" \ 572 "fdt_addr=800A0000\0" \ 573 "ramdisk_addr=80300000\0" \ 574 "u-boot=tqm834x/u-boot.bin\0" \ 575 "load=tftp 200000 ${u-boot}\0" \ 576 "update=protect off 80000000 +${filesize};" \ 577 "era 80000000 +${filesize};" \ 578 "cp.b 200000 80000000 ${filesize}\0" \ 579 "upd=run load update\0" \ 580 "" 581 582 #define CONFIG_BOOTCOMMAND "run flash_self" 583 584 /* 585 * JFFS2 partitions 586 */ 587 /* mtdparts command line support */ 588 #define CONFIG_CMD_MTDPARTS 589 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 590 #define CONFIG_FLASH_CFI_MTD 591 #define MTDIDS_DEFAULT "nor0=TQM834x-0" 592 593 /* default mtd partition table */ 594 #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \ 595 "1m(kernel),2m(initrd)," \ 596 "-(user);" \ 597 598 #endif /* __CONFIG_H */ 599