1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * TQM8349 board configuration file 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 #define DEBUG 32 #undef DEBUG 33 34 /* 35 * High Level Configuration Options 36 */ 37 #define CONFIG_E300 1 /* E300 Family */ 38 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 39 #define CONFIG_MPC834X 1 /* MPC834X specific */ 40 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 41 #define CONFIG_TQM834X 1 /* TQM834X board specific */ 42 43 /* IMMR Base Addres Register, use Freescale default: 0xff400000 */ 44 #define CFG_IMMR 0xff400000 45 46 /* System clock. Primary input clock when in PCI host mode */ 47 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ 48 49 /* 50 * Local Bus LCRR 51 * LCRR: DLL bypass, Clock divider is 8 52 * 53 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz 54 * 55 * External Local Bus rate is 56 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 57 */ 58 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) 59 60 #define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK)) 61 #define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */ 62 #define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */ 63 #define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */ 64 #define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */ 65 #define CFG_SCCR_VAL ( CFG_SCCR_INIT \ 66 | CFG_SCCR_TSEC1CM \ 67 | CFG_SCCR_TSEC2CM \ 68 | CFG_SCCR_ENCCM \ 69 | CFG_SCCR_USBCM ) 70 71 /* board pre init: do not call, nothing to do */ 72 #undef CONFIG_BOARD_EARLY_INIT_F 73 74 /* detect the number of flash banks */ 75 #define CONFIG_BOARD_EARLY_INIT_R 76 77 /* 78 * DDR Setup 79 */ 80 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 81 #define CFG_SDRAM_BASE CFG_DDR_BASE 82 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 83 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 84 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 85 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 86 87 #undef CFG_DRAM_TEST /* memory test, takes time */ 88 #define CFG_MEMTEST_START 0x00000000 /* memtest region */ 89 #define CFG_MEMTEST_END 0x00100000 90 91 /* 92 * FLASH on the Local Bus 93 */ 94 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 95 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 96 #undef CFG_FLASH_CHECKSUM 97 #define CFG_FLASH_BASE 0x80000000 /* start of FLASH */ 98 #define CFG_FLASH_SIZE 8 /* FLASH size in MB */ 99 100 /* buffered writes in the AMD chip set is not supported yet */ 101 #undef CFG_FLASH_USE_BUFFER_WRITE 102 103 /* 104 * FLASH bank number detection 105 */ 106 107 /* 108 * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash 109 * banks has to be determined at runtime and stored in a gloabl variable 110 * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only 111 * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and 112 * should be made sufficiently large to accomodate the number of banks that 113 * might actually be detected. Since most (all?) Flash related functions use 114 * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is 115 * defined as tqm834x_num_flash_banks. 116 */ 117 #define CFG_MAX_FLASH_BANKS_DETECT 2 118 #ifndef __ASSEMBLY__ 119 extern int tqm834x_num_flash_banks; 120 #endif 121 #define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks) 122 123 #define CFG_MAX_FLASH_SECT 512 /* max sectors per device */ 124 125 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ 126 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA) | \ 127 BR_MS_GPCM | BR_PS_32 | BR_V) 128 129 /* FLASH timing (0x0000_0c54) */ 130 #define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \ 131 OR_GPCM_SCY_5 | OR_GPCM_TRLX) 132 133 #define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ 134 135 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) 136 137 #define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */ 138 139 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ 140 141 /* disable remaining mappings */ 142 #define CFG_BR1_PRELIM 0x00000000 143 #define CFG_OR1_PRELIM 0x00000000 144 #define CFG_LBLAWBAR1_PRELIM 0x00000000 145 #define CFG_LBLAWAR1_PRELIM 0x00000000 146 147 #define CFG_BR2_PRELIM 0x00000000 148 #define CFG_OR2_PRELIM 0x00000000 149 #define CFG_LBLAWBAR2_PRELIM 0x00000000 150 #define CFG_LBLAWAR2_PRELIM 0x00000000 151 152 #define CFG_BR3_PRELIM 0x00000000 153 #define CFG_OR3_PRELIM 0x00000000 154 #define CFG_LBLAWBAR3_PRELIM 0x00000000 155 #define CFG_LBLAWAR3_PRELIM 0x00000000 156 157 #define CFG_BR4_PRELIM 0x00000000 158 #define CFG_OR4_PRELIM 0x00000000 159 #define CFG_LBLAWBAR4_PRELIM 0x00000000 160 #define CFG_LBLAWAR4_PRELIM 0x00000000 161 162 #define CFG_BR5_PRELIM 0x00000000 163 #define CFG_OR5_PRELIM 0x00000000 164 #define CFG_LBLAWBAR5_PRELIM 0x00000000 165 #define CFG_LBLAWAR5_PRELIM 0x00000000 166 167 #define CFG_BR6_PRELIM 0x00000000 168 #define CFG_OR6_PRELIM 0x00000000 169 #define CFG_LBLAWBAR6_PRELIM 0x00000000 170 #define CFG_LBLAWAR6_PRELIM 0x00000000 171 172 #define CFG_BR7_PRELIM 0x00000000 173 #define CFG_OR7_PRELIM 0x00000000 174 #define CFG_LBLAWBAR7_PRELIM 0x00000000 175 #define CFG_LBLAWAR7_PRELIM 0x00000000 176 177 /* 178 * Monitor config 179 */ 180 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 181 182 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 183 #define CFG_RAMBOOT 184 #else 185 #undef CFG_RAMBOOT 186 #endif 187 188 #define CONFIG_L1_INIT_RAM 189 #define CFG_INIT_RAM_LOCK 1 190 #define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 191 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 192 193 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 194 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 195 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 196 197 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 198 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 199 200 /* 201 * Serial Port 202 */ 203 #define CONFIG_CONS_INDEX 1 204 #undef CONFIG_SERIAL_SOFTWARE_FIFO 205 #define CFG_NS16550 206 #define CFG_NS16550_SERIAL 207 #define CFG_NS16550_REG_SIZE 1 208 #define CFG_NS16550_CLK get_bus_freq(0) 209 210 #define CFG_BAUDRATE_TABLE \ 211 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 212 213 #define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) 214 #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) 215 216 /* 217 * I2C 218 */ 219 #define CONFIG_HARD_I2C /* I2C with hardware support */ 220 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 221 #define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */ 222 #define CFG_I2C_SLAVE 0x7F /* slave address */ 223 #define CFG_I2C_OFFSET 0x3000 224 225 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 226 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 227 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 228 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */ 229 #define CFG_EEPROM_PAGE_WRITE_ENABLE 230 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 231 #define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ 232 233 /* I2C RTC */ 234 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 235 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 236 237 /* I2C SYSMON (LM75) */ 238 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ 239 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 240 #define CFG_DTT_MAX_TEMP 70 241 #define CFG_DTT_LOW_TEMP -30 242 #define CFG_DTT_HYSTERESIS 3 243 244 /* 245 * TSEC 246 */ 247 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 248 #define CONFIG_MII 249 250 #define CFG_TSEC1_OFFSET 0x24000 251 #define CFG_TSEC1 (CFG_IMMR + CFG_TSEC1_OFFSET) 252 #define CFG_TSEC2_OFFSET 0x25000 253 #define CFG_TSEC2 (CFG_IMMR + CFG_TSEC2_OFFSET) 254 255 #if defined(CONFIG_TSEC_ENET) 256 257 #ifndef CONFIG_NET_MULTI 258 #define CONFIG_NET_MULTI 259 #endif 260 261 #define CONFIG_MPC83XX_TSEC1 1 262 #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" 263 #define CONFIG_MPC83XX_TSEC2 1 264 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" 265 #define TSEC1_PHY_ADDR 2 266 #define TSEC2_PHY_ADDR 1 267 #define TSEC1_PHYIDX 0 268 #define TSEC2_PHYIDX 0 269 270 /* Options are: TSEC[0-1] */ 271 #define CONFIG_ETHPRIME "TSEC0" 272 273 #endif /* CONFIG_TSEC_ENET */ 274 275 /* 276 * General PCI 277 * Addresses are mapped 1-1. 278 */ 279 #define CONFIG_PCI 280 281 #if defined(CONFIG_PCI) 282 283 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 284 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 285 286 /* PCI1 host bridge */ 287 #define CFG_PCI1_MEM_BASE 0xc0000000 288 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 289 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 290 #define CFG_PCI1_IO_BASE 0xe2000000 291 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 292 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 293 294 295 #undef CONFIG_EEPRO100 296 #define CONFIG_EEPRO100 297 #undef CONFIG_TULIP 298 299 #if !defined(CONFIG_PCI_PNP) 300 #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE 301 #define PCI_ENET0_MEMADDR CFG_PCI1_MEM_BASE 302 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 303 #endif 304 305 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 306 307 #endif /* CONFIG_PCI */ 308 309 /* 310 * Environment 311 */ 312 #define CONFIG_ENV_OVERWRITE 313 314 #ifndef CFG_RAMBOOT 315 #define CFG_ENV_IS_IN_FLASH 1 316 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 317 #define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ 318 #define CFG_ENV_SIZE 0x2000 319 #else 320 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 321 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 322 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 323 #define CFG_ENV_SIZE 0x2000 324 #endif 325 326 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 327 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 328 329 /* Common commands */ 330 #define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\ 331 | CFG_CMD_PING | CFG_CMD_EEPROM \ 332 | CFG_CMD_MII | CFG_CMD_JFFS2 333 334 #if defined(CFG_RAMBOOT) 335 336 #if defined(CONFIG_PCI) 337 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \ 338 | CFG_CMD_TQM8349_COMMON) \ 339 & \ 340 ~(CFG_CMD_ENV | CFG_CMD_LOADS)) 341 #else 342 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 343 | CFG_CMD_TQM8349_COMMON) \ 344 & \ 345 ~(CFG_CMD_ENV | CFG_CMD_LOADS)) 346 #endif 347 348 #else /* CFG_RAMBOOT */ 349 350 #if defined(CONFIG_PCI) 351 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \ 352 | CFG_CMD_TQM8349_COMMON) 353 #else 354 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 355 | CFG_CMD_TQM8349_COMMON) 356 #endif 357 358 #endif /* CFG_RAMBOOT */ 359 360 #include <cmd_confdefs.h> 361 362 /* 363 * Miscellaneous configurable options 364 */ 365 #define CFG_LONGHELP /* undef to save memory */ 366 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 367 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 368 369 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 370 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ 371 #ifdef CFG_HUSH_PARSER 372 #define CFG_PROMPT_HUSH_PS2 "> " 373 #endif 374 375 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 376 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 377 #else 378 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 379 #endif 380 381 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 382 #define CFG_MAXARGS 16 /* max number of command args */ 383 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 384 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 385 386 #undef CONFIG_WATCHDOG /* watchdog disabled */ 387 388 /* 389 * For booting Linux, the board info and command line data 390 * have to be in the first 8 MB of memory, since this is 391 * the maximum mapped by the Linux kernel during initialization. 392 */ 393 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 394 395 /* 396 * Cache Configuration 397 */ 398 #define CFG_DCACHE_SIZE 32768 399 #define CFG_CACHELINE_SIZE 32 400 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 401 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 402 #endif 403 404 #define CFG_HRCW_LOW (\ 405 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 406 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 407 HRCWL_CSB_TO_CLKIN_4X1 |\ 408 HRCWL_VCO_1X2 |\ 409 HRCWL_CORE_TO_CSB_2X1) 410 411 #if defined(PCI_64BIT) 412 #define CFG_HRCW_HIGH (\ 413 HRCWH_PCI_HOST |\ 414 HRCWH_64_BIT_PCI |\ 415 HRCWH_PCI1_ARBITER_ENABLE |\ 416 HRCWH_PCI2_ARBITER_DISABLE |\ 417 HRCWH_CORE_ENABLE |\ 418 HRCWH_FROM_0X00000100 |\ 419 HRCWH_BOOTSEQ_DISABLE |\ 420 HRCWH_SW_WATCHDOG_DISABLE |\ 421 HRCWH_ROM_LOC_LOCAL_16BIT |\ 422 HRCWH_TSEC1M_IN_GMII |\ 423 HRCWH_TSEC2M_IN_GMII ) 424 #else 425 #define CFG_HRCW_HIGH (\ 426 HRCWH_PCI_HOST |\ 427 HRCWH_32_BIT_PCI |\ 428 HRCWH_PCI1_ARBITER_ENABLE |\ 429 HRCWH_PCI2_ARBITER_DISABLE |\ 430 HRCWH_CORE_ENABLE |\ 431 HRCWH_FROM_0X00000100 |\ 432 HRCWH_BOOTSEQ_DISABLE |\ 433 HRCWH_SW_WATCHDOG_DISABLE |\ 434 HRCWH_ROM_LOC_LOCAL_16BIT |\ 435 HRCWH_TSEC1M_IN_GMII |\ 436 HRCWH_TSEC2M_IN_GMII ) 437 #endif 438 439 /* System IO Config */ 440 #define CFG_SICRH SICRH_TSOBI1 441 #define CFG_SICRL SICRL_LDP_A 442 443 /* i-cache and d-cache disabled */ 444 #define CFG_HID0_INIT 0x000000000 445 #define CFG_HID0_FINAL CFG_HID0_INIT 446 #define CFG_HID2 HID2_HBE 447 448 /* DDR 0 - 512M */ 449 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 450 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 451 #define CFG_IBAT1L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 452 #define CFG_IBAT1U (CFG_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) 453 454 /* stack in DCACHE @ 512M (no backing mem) */ 455 #define CFG_IBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) 456 #define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 457 458 /* PCI */ 459 #ifdef CONFIG_PCI 460 #define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 461 #define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 462 #define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 463 #define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) 464 #define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 465 #define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP) 466 #else 467 #define CFG_IBAT3L (0) 468 #define CFG_IBAT3U (0) 469 #define CFG_IBAT4L (0) 470 #define CFG_IBAT4U (0) 471 #define CFG_IBAT5L (0) 472 #define CFG_IBAT5U (0) 473 #endif 474 475 /* IMMRBAR */ 476 #define CFG_IBAT6L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 477 #define CFG_IBAT6U (CFG_IMMR | BATU_BL_1M | BATU_VS | BATU_VP) 478 479 /* FLASH */ 480 #define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 481 #define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 482 483 #define CFG_DBAT0L CFG_IBAT0L 484 #define CFG_DBAT0U CFG_IBAT0U 485 #define CFG_DBAT1L CFG_IBAT1L 486 #define CFG_DBAT1U CFG_IBAT1U 487 #define CFG_DBAT2L CFG_IBAT2L 488 #define CFG_DBAT2U CFG_IBAT2U 489 #define CFG_DBAT3L CFG_IBAT3L 490 #define CFG_DBAT3U CFG_IBAT3U 491 #define CFG_DBAT4L CFG_IBAT4L 492 #define CFG_DBAT4U CFG_IBAT4U 493 #define CFG_DBAT5L CFG_IBAT5L 494 #define CFG_DBAT5U CFG_IBAT5U 495 #define CFG_DBAT6L CFG_IBAT6L 496 #define CFG_DBAT6U CFG_IBAT6U 497 #define CFG_DBAT7L CFG_IBAT7L 498 #define CFG_DBAT7U CFG_IBAT7U 499 500 /* 501 * Internal Definitions 502 * 503 * Boot Flags 504 */ 505 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 506 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 507 508 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 509 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 510 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 511 #endif 512 513 /* 514 * Environment Configuration 515 */ 516 517 #if defined(CONFIG_TSEC_ENET) 518 #define CONFIG_ETHADDR D2:DA:5E:44:BC:29 519 #define CONFIG_HAS_ETH1 520 #define CONFIG_ETH1ADDR 1E:F3:40:21:92:53 521 #endif 522 523 #define CONFIG_IPADDR 192.168.205.1 524 525 #define CONFIG_HOSTNAME tqm8349 526 #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx 527 #define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage 528 529 #define CONFIG_SERVERIP 192.168.1.1 530 #define CONFIG_GATEWAYIP 192.168.1.1 531 #define CONFIG_NETMASK 255.255.255.0 532 533 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 534 535 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 536 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 537 538 #define CONFIG_BAUDRATE 115200 539 540 #define CONFIG_PREBOOT "echo;" \ 541 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ 542 "echo" 543 544 #undef CONFIG_BOOTARGS 545 546 #define CONFIG_EXTRA_ENV_SETTINGS \ 547 "netdev=eth0\0" \ 548 "hostname=tqm83xx\0" \ 549 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 550 "nfsroot=${serverip}:${rootpath}\0" \ 551 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 552 "addip=setenv bootargs ${bootargs} " \ 553 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 554 ":${hostname}:${netdev}:off panic=1\0" \ 555 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 556 "flash_nfs=run nfsargs addip addtty;" \ 557 "bootm ${kernel_addr}\0" \ 558 "flash_self=run ramargs addip addtty;" \ 559 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 560 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 561 "bootm\0" \ 562 "rootpath=/opt/eldk/ppc_6xx\0" \ 563 "bootfile=/tftpboot/tqm83xx/uImage\0" \ 564 "kernel_addr=80060000\0" \ 565 "ramdisk_addr=80160000\0" \ 566 "load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \ 567 "update=protect off 80000000 8003ffff; " \ 568 "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \ 569 "upd=run load;run update\0" \ 570 "" 571 572 #define CONFIG_BOOTCOMMAND "run flash_self" 573 574 /* 575 * JFFS2 partitions 576 */ 577 /* mtdparts command line support */ 578 #define CONFIG_JFFS2_CMDLINE 579 #define MTDIDS_DEFAULT "nor0=TQM834x-0" 580 581 /* default mtd partition table */ 582 #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\ 583 "1m(kernel),2m(initrd),"\ 584 "-(user);"\ 585 586 #endif /* __CONFIG_H */ 587