1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * TQM8349 board configuration file 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 #define DEBUG 32 #undef DEBUG 33 34 /* 35 * High Level Configuration Options 36 */ 37 #define CONFIG_E300 1 /* E300 Family */ 38 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 39 #define CONFIG_MPC834X 1 /* MPC834X specific */ 40 #define CONFIG_TQM834X 1 /* TQM834X board specific */ 41 42 /* IMMR Base Addres Register, use Freescale default: 0xff400000 */ 43 #define CFG_IMMRBAR 0xff400000 44 45 /* System clock. Primary input clock when in PCI host mode */ 46 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ 47 48 /* 49 * Local Bus LCRR 50 * LCRR: DLL bypass, Clock divider is 8 51 * 52 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz 53 * 54 * External Local Bus rate is 55 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 56 */ 57 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) 58 59 /* board pre init: do not call, nothing to do */ 60 #undef CONFIG_BOARD_EARLY_INIT_F 61 62 /* detect the number of flash banks */ 63 #define CONFIG_BOARD_EARLY_INIT_R 64 65 /* 66 * DDR Setup 67 */ 68 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 69 #define CFG_SDRAM_BASE CFG_DDR_BASE 70 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 71 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 72 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 73 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 74 75 #undef CFG_DRAM_TEST /* memory test, takes time */ 76 #define CFG_MEMTEST_START 0x00000000 /* memtest region */ 77 #define CFG_MEMTEST_END 0x00100000 78 79 /* 80 * FLASH on the Local Bus 81 */ 82 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 83 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 84 #undef CFG_FLASH_CHECKSUM 85 #define CFG_FLASH_BASE 0x80000000 /* start of FLASH */ 86 87 /* buffered writes in the AMD chip set is not supported yet */ 88 #undef CFG_FLASH_USE_BUFFER_WRITE 89 90 /* 91 * FLASH bank number detection 92 */ 93 94 /* 95 * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash 96 * banks has to be determined at runtime and stored in a gloabl variable 97 * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only 98 * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and 99 * should be made sufficiently large to accomodate the number of banks that 100 * might actually be detected. Since most (all?) Flash related functions use 101 * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is 102 * defined as tqm834x_num_flash_banks. 103 */ 104 #define CFG_MAX_FLASH_BANKS_DETECT 2 105 #ifndef __ASSEMBLY__ 106 extern int tqm834x_num_flash_banks; 107 #endif 108 #define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks) 109 110 #define CFG_MAX_FLASH_SECT 512 /* max sectors per device */ 111 112 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ 113 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA) | \ 114 BR_MS_GPCM | BR_PS_32 | BR_V) 115 116 /* FLASH timing (0x0000_0c54) */ 117 #define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \ 118 OR_GPCM_SCY_5 | OR_GPCM_TRLX) 119 120 #define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ 121 122 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) 123 124 #define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */ 125 126 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ 127 128 /* disable remaining mappings */ 129 #define CFG_BR1_PRELIM 0x00000000 130 #define CFG_OR1_PRELIM 0x00000000 131 #define CFG_LBLAWBAR1_PRELIM 0x00000000 132 #define CFG_LBLAWAR1_PRELIM 0x00000000 133 134 #define CFG_BR2_PRELIM 0x00000000 135 #define CFG_OR2_PRELIM 0x00000000 136 #define CFG_LBLAWBAR2_PRELIM 0x00000000 137 #define CFG_LBLAWAR2_PRELIM 0x00000000 138 139 #define CFG_BR3_PRELIM 0x00000000 140 #define CFG_OR3_PRELIM 0x00000000 141 #define CFG_LBLAWBAR3_PRELIM 0x00000000 142 #define CFG_LBLAWAR3_PRELIM 0x00000000 143 144 #define CFG_BR4_PRELIM 0x00000000 145 #define CFG_OR4_PRELIM 0x00000000 146 #define CFG_LBLAWBAR4_PRELIM 0x00000000 147 #define CFG_LBLAWAR4_PRELIM 0x00000000 148 149 #define CFG_BR5_PRELIM 0x00000000 150 #define CFG_OR5_PRELIM 0x00000000 151 #define CFG_LBLAWBAR5_PRELIM 0x00000000 152 #define CFG_LBLAWAR5_PRELIM 0x00000000 153 154 #define CFG_BR6_PRELIM 0x00000000 155 #define CFG_OR6_PRELIM 0x00000000 156 #define CFG_LBLAWBAR6_PRELIM 0x00000000 157 #define CFG_LBLAWAR6_PRELIM 0x00000000 158 159 #define CFG_BR7_PRELIM 0x00000000 160 #define CFG_OR7_PRELIM 0x00000000 161 #define CFG_LBLAWBAR7_PRELIM 0x00000000 162 #define CFG_LBLAWAR7_PRELIM 0x00000000 163 164 /* 165 * Monitor config 166 */ 167 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 168 169 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 170 #define CFG_RAMBOOT 171 #else 172 #undef CFG_RAMBOOT 173 #endif 174 175 #define CONFIG_L1_INIT_RAM 176 #define CFG_INIT_RAM_LOCK 1 177 #define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 178 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 179 180 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 181 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 182 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 183 184 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 185 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 186 187 /* 188 * Serial Port 189 */ 190 #define CONFIG_CONS_INDEX 1 191 #undef CONFIG_SERIAL_SOFTWARE_FIFO 192 #define CFG_NS16550 193 #define CFG_NS16550_SERIAL 194 #define CFG_NS16550_REG_SIZE 1 195 #define CFG_NS16550_CLK get_bus_freq(0) 196 197 #define CFG_BAUDRATE_TABLE \ 198 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 199 200 #define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) 201 #define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) 202 203 /* 204 * I2C 205 */ 206 #define CONFIG_HARD_I2C /* I2C with hardware support */ 207 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 208 #define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */ 209 #define CFG_I2C_SLAVE 0x7F /* slave address */ 210 #define CFG_I2C_OFFSET 0x3000 211 212 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 213 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 214 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 215 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */ 216 #define CFG_EEPROM_PAGE_WRITE_ENABLE 217 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 218 #define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ 219 220 /* I2C RTC */ 221 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 222 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 223 224 /* I2C SYSMON (LM75) */ 225 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ 226 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 227 #define CFG_DTT_MAX_TEMP 70 228 #define CFG_DTT_LOW_TEMP -30 229 #define CFG_DTT_HYSTERESIS 3 230 231 /* 232 * TSEC 233 */ 234 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 235 #define CONFIG_MII 236 237 #define CFG_TSEC1_OFFSET 0x24000 238 #define CFG_TSEC1 (CFG_IMMRBAR + CFG_TSEC1_OFFSET) 239 #define CFG_TSEC2_OFFSET 0x25000 240 #define CFG_TSEC2 (CFG_IMMRBAR + CFG_TSEC2_OFFSET) 241 242 #if defined(CONFIG_TSEC_ENET) 243 244 #ifndef CONFIG_NET_MULTI 245 #define CONFIG_NET_MULTI 246 #endif 247 248 #define CONFIG_MPC83XX_TSEC1 1 249 #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" 250 #define CONFIG_MPC83XX_TSEC2 1 251 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" 252 #define TSEC1_PHY_ADDR 2 253 #define TSEC2_PHY_ADDR 1 254 #define TSEC1_PHYIDX 0 255 #define TSEC2_PHYIDX 0 256 257 /* Options are: TSEC[0-1] */ 258 #define CONFIG_ETHPRIME "TSEC0" 259 260 #endif /* CONFIG_TSEC_ENET */ 261 262 /* 263 * General PCI 264 * Addresses are mapped 1-1. 265 */ 266 #define CONFIG_PCI 267 268 #if defined(CONFIG_PCI) 269 270 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 271 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 272 273 /* PCI1 host bridge */ 274 #define CFG_PCI1_MEM_BASE 0xc0000000 275 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 276 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 277 #define CFG_PCI1_IO_BASE 0xe2000000 278 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 279 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 280 281 282 #undef CONFIG_EEPRO100 283 #define CONFIG_EEPRO100 284 #undef CONFIG_TULIP 285 286 #if !defined(CONFIG_PCI_PNP) 287 #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE 288 #define PCI_ENET0_MEMADDR CFG_PCI1_MEM_BASE 289 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 290 #endif 291 292 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 293 294 #endif /* CONFIG_PCI */ 295 296 /* 297 * Environment 298 */ 299 #define CONFIG_ENV_OVERWRITE 300 301 #ifndef CFG_RAMBOOT 302 #define CFG_ENV_IS_IN_FLASH 1 303 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 304 #define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ 305 #define CFG_ENV_SIZE 0x2000 306 #else 307 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 308 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 309 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 310 #define CFG_ENV_SIZE 0x2000 311 #endif 312 313 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 314 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 315 316 /* Common commands */ 317 #define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\ 318 | CFG_CMD_PING | CFG_CMD_EEPROM \ 319 | CFG_CMD_MII | CFG_CMD_JFFS2 320 321 #if defined(CFG_RAMBOOT) 322 323 #if defined(CONFIG_PCI) 324 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \ 325 | CFG_CMD_TQM8349_COMMON) \ 326 & \ 327 ~(CFG_CMD_ENV | CFG_CMD_LOADS)) 328 #else 329 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 330 | CFG_CMD_TQM8349_COMMON) \ 331 & \ 332 ~(CFG_CMD_ENV | CFG_CMD_LOADS)) 333 #endif 334 335 #else /* CFG_RAMBOOT */ 336 337 #if defined(CONFIG_PCI) 338 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \ 339 | CFG_CMD_TQM8349_COMMON) 340 #else 341 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 342 | CFG_CMD_TQM8349_COMMON) 343 #endif 344 345 #endif /* CFG_RAMBOOT */ 346 347 #include <cmd_confdefs.h> 348 349 /* 350 * Miscellaneous configurable options 351 */ 352 #define CFG_LONGHELP /* undef to save memory */ 353 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 354 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 355 356 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 357 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ 358 #ifdef CFG_HUSH_PARSER 359 #define CFG_PROMPT_HUSH_PS2 "> " 360 #endif 361 362 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 363 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 364 #else 365 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 366 #endif 367 368 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 369 #define CFG_MAXARGS 16 /* max number of command args */ 370 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 371 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 372 373 #undef CONFIG_WATCHDOG /* watchdog disabled */ 374 375 /* 376 * For booting Linux, the board info and command line data 377 * have to be in the first 8 MB of memory, since this is 378 * the maximum mapped by the Linux kernel during initialization. 379 */ 380 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 381 382 /* 383 * Cache Configuration 384 */ 385 #define CFG_DCACHE_SIZE 32768 386 #define CFG_CACHELINE_SIZE 32 387 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 388 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 389 #endif 390 391 #define CFG_HRCW_LOW (\ 392 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 393 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 394 HRCWL_CSB_TO_CLKIN_4X1 |\ 395 HRCWL_VCO_1X2 |\ 396 HRCWL_CORE_TO_CSB_2X1) 397 398 #if defined(PCI_64BIT) 399 #define CFG_HRCW_HIGH (\ 400 HRCWH_PCI_HOST |\ 401 HRCWH_64_BIT_PCI |\ 402 HRCWH_PCI1_ARBITER_ENABLE |\ 403 HRCWH_PCI2_ARBITER_DISABLE |\ 404 HRCWH_CORE_ENABLE |\ 405 HRCWH_FROM_0X00000100 |\ 406 HRCWH_BOOTSEQ_DISABLE |\ 407 HRCWH_SW_WATCHDOG_DISABLE |\ 408 HRCWH_ROM_LOC_LOCAL_16BIT |\ 409 HRCWH_TSEC1M_IN_GMII |\ 410 HRCWH_TSEC2M_IN_GMII ) 411 #else 412 #define CFG_HRCW_HIGH (\ 413 HRCWH_PCI_HOST |\ 414 HRCWH_32_BIT_PCI |\ 415 HRCWH_PCI1_ARBITER_ENABLE |\ 416 HRCWH_PCI2_ARBITER_DISABLE |\ 417 HRCWH_CORE_ENABLE |\ 418 HRCWH_FROM_0X00000100 |\ 419 HRCWH_BOOTSEQ_DISABLE |\ 420 HRCWH_SW_WATCHDOG_DISABLE |\ 421 HRCWH_ROM_LOC_LOCAL_16BIT |\ 422 HRCWH_TSEC1M_IN_GMII |\ 423 HRCWH_TSEC2M_IN_GMII ) 424 #endif 425 426 /* System IO Config */ 427 #define CFG_SICRH SICRH_TSOBI1 428 #define CFG_SICRL SICRL_LDP_A 429 430 /* i-cache and d-cache disabled */ 431 #define CFG_HID0_INIT 0x000000000 432 #define CFG_HID0_FINAL CFG_HID0_INIT 433 #define CFG_HID2 HID2_HBE 434 435 /* DDR 0 - 512M */ 436 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 437 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 438 #define CFG_IBAT1L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 439 #define CFG_IBAT1U (CFG_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) 440 441 /* stack in DCACHE @ 512M (no backing mem) */ 442 #define CFG_IBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) 443 #define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 444 445 /* PCI */ 446 #ifdef CONFIG_PCI 447 #define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 448 #define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 449 #define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 450 #define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) 451 #define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 452 #define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP) 453 #else 454 #define CFG_IBAT3L (0) 455 #define CFG_IBAT3U (0) 456 #define CFG_IBAT4L (0) 457 #define CFG_IBAT4U (0) 458 #define CFG_IBAT5L (0) 459 #define CFG_IBAT5U (0) 460 #endif 461 462 /* IMMRBAR */ 463 #define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 464 #define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 465 466 /* FLASH */ 467 #define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 468 #define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 469 470 #define CFG_DBAT0L CFG_IBAT0L 471 #define CFG_DBAT0U CFG_IBAT0U 472 #define CFG_DBAT1L CFG_IBAT1L 473 #define CFG_DBAT1U CFG_IBAT1U 474 #define CFG_DBAT2L CFG_IBAT2L 475 #define CFG_DBAT2U CFG_IBAT2U 476 #define CFG_DBAT3L CFG_IBAT3L 477 #define CFG_DBAT3U CFG_IBAT3U 478 #define CFG_DBAT4L CFG_IBAT4L 479 #define CFG_DBAT4U CFG_IBAT4U 480 #define CFG_DBAT5L CFG_IBAT5L 481 #define CFG_DBAT5U CFG_IBAT5U 482 #define CFG_DBAT6L CFG_IBAT6L 483 #define CFG_DBAT6U CFG_IBAT6U 484 #define CFG_DBAT7L CFG_IBAT7L 485 #define CFG_DBAT7U CFG_IBAT7U 486 487 /* 488 * Internal Definitions 489 * 490 * Boot Flags 491 */ 492 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 493 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 494 495 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 496 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 497 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 498 #endif 499 500 /* 501 * Environment Configuration 502 */ 503 504 #if defined(CONFIG_TSEC_ENET) 505 #define CONFIG_ETHADDR D2:DA:5E:44:BC:29 506 #define CONFIG_HAS_ETH1 507 #define CONFIG_ETH1ADDR 1E:F3:40:21:92:53 508 #endif 509 510 #define CONFIG_IPADDR 192.168.205.1 511 512 #define CONFIG_HOSTNAME tqm8349 513 #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx 514 #define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage 515 516 #define CONFIG_SERVERIP 192.168.1.1 517 #define CONFIG_GATEWAYIP 192.168.1.1 518 #define CONFIG_NETMASK 255.255.255.0 519 520 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 521 522 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 523 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 524 525 #define CONFIG_BAUDRATE 115200 526 527 #define CONFIG_PREBOOT "echo;" \ 528 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ 529 "echo" 530 531 #undef CONFIG_BOOTARGS 532 533 #define CONFIG_EXTRA_ENV_SETTINGS \ 534 "netdev=eth0\0" \ 535 "hostname=tqm83xx\0" \ 536 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 537 "nfsroot=${serverip}:${rootpath}\0" \ 538 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 539 "addip=setenv bootargs ${bootargs} " \ 540 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 541 ":${hostname}:${netdev}:off panic=1\0" \ 542 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 543 "flash_nfs=run nfsargs addip addtty;" \ 544 "bootm ${kernel_addr}\0" \ 545 "flash_self=run ramargs addip addtty;" \ 546 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 547 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 548 "bootm\0" \ 549 "rootpath=/opt/eldk/ppc_6xx\0" \ 550 "bootfile=/tftpboot/tqm83xx/uImage\0" \ 551 "kernel_addr=80060000\0" \ 552 "ramdisk_addr=80160000\0" \ 553 "load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \ 554 "update=protect off 80000000 8003ffff; " \ 555 "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \ 556 "upd=run load;run update\0" \ 557 "" 558 559 #define CONFIG_BOOTCOMMAND "run flash_self" 560 561 /* 562 * JFFS2 partitions 563 */ 564 /* mtdparts command line support */ 565 #define CONFIG_JFFS2_CMDLINE 566 #define MTDIDS_DEFAULT "nor0=TQM834x-0" 567 568 /* default mtd partition table */ 569 #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\ 570 "1m(kernel),2m(initrd),"\ 571 "-(user);"\ 572 573 #endif /* __CONFIG_H */ 574