1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * TQM8349 board configuration file 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 /* 32 * High Level Configuration Options 33 */ 34 #define CONFIG_E300 1 /* E300 Family */ 35 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 36 #define CONFIG_MPC834X 1 /* MPC834X specific */ 37 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 38 #define CONFIG_TQM834X 1 /* TQM834X board specific */ 39 40 /* IMMR Base Addres Register, use Freescale default: 0xff400000 */ 41 #define CONFIG_SYS_IMMR 0xff400000 42 43 /* System clock. Primary input clock when in PCI host mode */ 44 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ 45 46 /* 47 * Local Bus LCRR 48 * LCRR: DLL bypass, Clock divider is 8 49 * 50 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz 51 * 52 * External Local Bus rate is 53 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 54 */ 55 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) 56 57 /* board pre init: do not call, nothing to do */ 58 #undef CONFIG_BOARD_EARLY_INIT_F 59 60 /* detect the number of flash banks */ 61 #define CONFIG_BOARD_EARLY_INIT_R 62 63 /* 64 * DDR Setup 65 */ 66 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 67 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 68 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 69 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 70 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 71 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 72 73 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 74 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 75 #define CONFIG_SYS_MEMTEST_END 0x00100000 76 77 /* 78 * FLASH on the Local Bus 79 */ 80 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 81 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 82 #undef CONFIG_SYS_FLASH_CHECKSUM 83 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ 84 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ 85 86 /* buffered writes in the AMD chip set is not supported yet */ 87 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 88 89 /* 90 * FLASH bank number detection 91 */ 92 93 /* 94 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash 95 * banks has to be determined at runtime and stored in a gloabl variable 96 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is only 97 * used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array flash_info, and 98 * should be made sufficiently large to accomodate the number of banks that 99 * might actually be detected. Since most (all?) Flash related functions use 100 * CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on the board, it is 101 * defined as tqm834x_num_flash_banks. 102 */ 103 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 104 #ifndef __ASSEMBLY__ 105 extern int tqm834x_num_flash_banks; 106 #endif 107 #define CONFIG_SYS_MAX_FLASH_BANKS (tqm834x_num_flash_banks) 108 109 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ 110 111 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ 112 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) | \ 113 BR_MS_GPCM | BR_PS_32 | BR_V) 114 115 /* FLASH timing (0x0000_0c54) */ 116 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \ 117 OR_GPCM_SCY_5 | OR_GPCM_TRLX) 118 119 #define CONFIG_SYS_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ 120 121 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 122 123 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */ 124 125 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ 126 127 /* disable remaining mappings */ 128 #define CONFIG_SYS_BR1_PRELIM 0x00000000 129 #define CONFIG_SYS_OR1_PRELIM 0x00000000 130 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 131 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 132 133 #define CONFIG_SYS_BR2_PRELIM 0x00000000 134 #define CONFIG_SYS_OR2_PRELIM 0x00000000 135 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 136 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 137 138 #define CONFIG_SYS_BR3_PRELIM 0x00000000 139 #define CONFIG_SYS_OR3_PRELIM 0x00000000 140 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 141 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 142 143 /* 144 * Monitor config 145 */ 146 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 147 148 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 149 #define CONFIG_SYS_RAMBOOT 150 #else 151 #undef CONFIG_SYS_RAMBOOT 152 #endif 153 154 #define CONFIG_SYS_INIT_RAM_LOCK 1 155 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 156 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 157 158 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 159 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 160 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 161 162 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB = 3 sect. for Mon */ 163 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ 164 165 /* 166 * Serial Port 167 */ 168 #define CONFIG_CONS_INDEX 1 169 #undef CONFIG_SERIAL_SOFTWARE_FIFO 170 #define CONFIG_SYS_NS16550 171 #define CONFIG_SYS_NS16550_SERIAL 172 #define CONFIG_SYS_NS16550_REG_SIZE 1 173 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 174 175 #define CONFIG_SYS_BAUDRATE_TABLE \ 176 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 177 178 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 179 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 180 181 /* 182 * I2C 183 */ 184 #define CONFIG_HARD_I2C /* I2C with hardware support */ 185 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 186 #define CONFIG_FSL_I2C 187 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */ 188 #define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */ 189 #define CONFIG_SYS_I2C_OFFSET 0x3000 190 191 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 192 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 193 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 194 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */ 195 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 196 #define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ 197 198 /* I2C RTC */ 199 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 200 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 201 202 /* I2C SYSMON (LM75) */ 203 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ 204 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 205 #define CONFIG_SYS_DTT_MAX_TEMP 70 206 #define CONFIG_SYS_DTT_LOW_TEMP -30 207 #define CONFIG_SYS_DTT_HYSTERESIS 3 208 209 /* 210 * TSEC 211 */ 212 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 213 #define CONFIG_MII 214 215 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 216 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 217 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 218 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 219 220 #if defined(CONFIG_TSEC_ENET) 221 222 #ifndef CONFIG_NET_MULTI 223 #define CONFIG_NET_MULTI 224 #endif 225 226 #define CONFIG_TSEC1 1 227 #define CONFIG_TSEC1_NAME "TSEC0" 228 #define CONFIG_TSEC2 1 229 #define CONFIG_TSEC2_NAME "TSEC1" 230 #define TSEC1_PHY_ADDR 2 231 #define TSEC2_PHY_ADDR 1 232 #define TSEC1_PHYIDX 0 233 #define TSEC2_PHYIDX 0 234 #define TSEC1_FLAGS TSEC_GIGABIT 235 #define TSEC2_FLAGS TSEC_GIGABIT 236 237 /* Options are: TSEC[0-1] */ 238 #define CONFIG_ETHPRIME "TSEC0" 239 240 #endif /* CONFIG_TSEC_ENET */ 241 242 /* 243 * General PCI 244 * Addresses are mapped 1-1. 245 */ 246 #define CONFIG_PCI 247 248 #if defined(CONFIG_PCI) 249 250 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 251 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 252 253 /* PCI1 host bridge */ 254 #define CONFIG_SYS_PCI1_MEM_BASE 0xc0000000 255 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 256 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 257 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 258 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 259 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ 260 261 #undef CONFIG_EEPRO100 262 #define CONFIG_EEPRO100 263 #undef CONFIG_TULIP 264 265 #if !defined(CONFIG_PCI_PNP) 266 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE 267 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE 268 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 269 #endif 270 271 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 272 273 #endif /* CONFIG_PCI */ 274 275 /* 276 * Environment 277 */ 278 #ifdef CONFIG_SYS_RAMBOOT 279 # define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 280 #else 281 # define CONFIG_ENV_IS_IN_FLASH 1 282 #endif 283 284 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 285 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ 286 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ 287 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 288 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 289 290 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 291 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 292 293 /* 294 * BOOTP options 295 */ 296 #define CONFIG_BOOTP_BOOTFILESIZE 297 #define CONFIG_BOOTP_BOOTPATH 298 #define CONFIG_BOOTP_GATEWAY 299 #define CONFIG_BOOTP_HOSTNAME 300 301 302 /* 303 * Command line configuration. 304 */ 305 #include <config_cmd_default.h> 306 307 #define CONFIG_CMD_DATE 308 #define CONFIG_CMD_DTT 309 #define CONFIG_CMD_EEPROM 310 #define CONFIG_CMD_I2C 311 #define CONFIG_CMD_JFFS2 312 #define CONFIG_CMD_MII 313 #define CONFIG_CMD_PING 314 #define CONFIG_CMD_DHCP 315 316 #if defined(CONFIG_PCI) 317 #define CONFIG_CMD_PCI 318 #endif 319 320 #if defined(CONFIG_SYS_RAMBOOT) 321 #undef CONFIG_CMD_SAVEENV 322 #undef CONFIG_CMD_LOADS 323 #endif 324 325 /* 326 * Miscellaneous configurable options 327 */ 328 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 329 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 330 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 331 332 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 333 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 334 #ifdef CONFIG_SYS_HUSH_PARSER 335 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 336 #endif 337 338 #if defined(CONFIG_CMD_KGDB) 339 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 340 #else 341 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 342 #endif 343 344 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 345 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 346 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 347 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 348 349 #undef CONFIG_WATCHDOG /* watchdog disabled */ 350 351 /* 352 * For booting Linux, the board info and command line data 353 * have to be in the first 8 MB of memory, since this is 354 * the maximum mapped by the Linux kernel during initialization. 355 */ 356 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 357 358 #define CONFIG_SYS_HRCW_LOW (\ 359 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 360 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 361 HRCWL_CSB_TO_CLKIN_4X1 |\ 362 HRCWL_VCO_1X2 |\ 363 HRCWL_CORE_TO_CSB_2X1) 364 365 #if defined(PCI_64BIT) 366 #define CONFIG_SYS_HRCW_HIGH (\ 367 HRCWH_PCI_HOST |\ 368 HRCWH_64_BIT_PCI |\ 369 HRCWH_PCI1_ARBITER_ENABLE |\ 370 HRCWH_PCI2_ARBITER_DISABLE |\ 371 HRCWH_CORE_ENABLE |\ 372 HRCWH_FROM_0X00000100 |\ 373 HRCWH_BOOTSEQ_DISABLE |\ 374 HRCWH_SW_WATCHDOG_DISABLE |\ 375 HRCWH_ROM_LOC_LOCAL_16BIT |\ 376 HRCWH_TSEC1M_IN_GMII |\ 377 HRCWH_TSEC2M_IN_GMII ) 378 #else 379 #define CONFIG_SYS_HRCW_HIGH (\ 380 HRCWH_PCI_HOST |\ 381 HRCWH_32_BIT_PCI |\ 382 HRCWH_PCI1_ARBITER_ENABLE |\ 383 HRCWH_PCI2_ARBITER_DISABLE |\ 384 HRCWH_CORE_ENABLE |\ 385 HRCWH_FROM_0X00000100 |\ 386 HRCWH_BOOTSEQ_DISABLE |\ 387 HRCWH_SW_WATCHDOG_DISABLE |\ 388 HRCWH_ROM_LOC_LOCAL_16BIT |\ 389 HRCWH_TSEC1M_IN_GMII |\ 390 HRCWH_TSEC2M_IN_GMII ) 391 #endif 392 393 /* System IO Config */ 394 #define CONFIG_SYS_SICRH 0 395 #define CONFIG_SYS_SICRL SICRL_LDP_A 396 397 /* i-cache and d-cache disabled */ 398 #define CONFIG_SYS_HID0_INIT 0x000000000 399 #define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT 400 #define CONFIG_SYS_HID2 HID2_HBE 401 402 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 403 404 /* DDR 0 - 512M */ 405 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 406 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 407 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 408 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) 409 410 /* stack in DCACHE @ 512M (no backing mem) */ 411 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) 412 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 413 414 /* PCI */ 415 #ifdef CONFIG_PCI 416 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 417 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 418 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 419 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) 420 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 421 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP) 422 #else 423 #define CONFIG_SYS_IBAT3L (0) 424 #define CONFIG_SYS_IBAT3U (0) 425 #define CONFIG_SYS_IBAT4L (0) 426 #define CONFIG_SYS_IBAT4U (0) 427 #define CONFIG_SYS_IBAT5L (0) 428 #define CONFIG_SYS_IBAT5U (0) 429 #endif 430 431 /* IMMRBAR */ 432 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 433 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR | BATU_BL_1M | BATU_VS | BATU_VP) 434 435 /* FLASH */ 436 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 437 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 438 439 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 440 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 441 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 442 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 443 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 444 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 445 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 446 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 447 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 448 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 449 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 450 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 451 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 452 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 453 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 454 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 455 456 /* 457 * Internal Definitions 458 * 459 * Boot Flags 460 */ 461 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 462 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 463 464 #if defined(CONFIG_CMD_KGDB) 465 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 466 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 467 #endif 468 469 /* 470 * Environment Configuration 471 */ 472 473 #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ 474 475 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 476 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 477 478 #define CONFIG_BAUDRATE 115200 479 480 #define CONFIG_PREBOOT "echo;" \ 481 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 482 "echo" 483 484 #undef CONFIG_BOOTARGS 485 486 #define CONFIG_EXTRA_ENV_SETTINGS \ 487 "netdev=eth0\0" \ 488 "hostname=tqm834x\0" \ 489 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 490 "nfsroot=${serverip}:${rootpath}\0" \ 491 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 492 "addip=setenv bootargs ${bootargs} " \ 493 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 494 ":${hostname}:${netdev}:off panic=1\0" \ 495 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 496 "flash_nfs=run nfsargs addip addtty;" \ 497 "bootm ${kernel_addr}\0" \ 498 "flash_self=run ramargs addip addtty;" \ 499 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 500 "net_nfs=tftp 400000 ${bootfile};run nfsargs addip addtty;" \ 501 "bootm\0" \ 502 "rootpath=/opt/eldk/ppc_6xx\0" \ 503 "bootfile=/tftpboot/tqm834x/uImage\0" \ 504 "kernel_addr=80060000\0" \ 505 "ramdisk_addr=80160000\0" \ 506 "load=tftp 100000 /tftpboot/tqm834x/u-boot.bin\0" \ 507 "update=protect off 80000000 8003ffff; " \ 508 "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \ 509 "upd=run load update\0" \ 510 "" 511 512 #define CONFIG_BOOTCOMMAND "run flash_self" 513 514 /* 515 * JFFS2 partitions 516 */ 517 /* mtdparts command line support */ 518 #define CONFIG_CMD_MTDPARTS 519 #define MTDIDS_DEFAULT "nor0=TQM834x-0" 520 521 /* default mtd partition table */ 522 #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env),"\ 523 "1m(kernel),2m(initrd),"\ 524 "-(user);"\ 525 526 #endif /* __CONFIG_H */ 527