1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240RDB 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_FSL_SATA_V2 17 #define CONFIG_PCIE4 18 19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 23 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg 24 #ifndef CONFIG_SDCARD 25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #else 28 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 29 #define CONFIG_SPL_ENV_SUPPORT 30 #define CONFIG_SPL_SERIAL_SUPPORT 31 #define CONFIG_SPL_FLUSH_IMAGE 32 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 33 #define CONFIG_SPL_LIBGENERIC_SUPPORT 34 #define CONFIG_SPL_LIBCOMMON_SUPPORT 35 #define CONFIG_SPL_I2C_SUPPORT 36 #define CONFIG_FSL_LAW /* Use common FSL init code */ 37 #define CONFIG_SYS_TEXT_BASE 0x00201000 38 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 39 #define CONFIG_SPL_PAD_TO 0x40000 40 #define CONFIG_SPL_MAX_SIZE 0x28000 41 #define RESET_VECTOR_OFFSET 0x27FFC 42 #define BOOT_PAGE_OFFSET 0x27000 43 44 #ifdef CONFIG_SDCARD 45 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 46 #define CONFIG_SPL_MMC_SUPPORT 47 #define CONFIG_SPL_MMC_MINIMAL 48 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 49 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 50 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 51 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 52 #ifndef CONFIG_SPL_BUILD 53 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 54 #endif 55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 56 #define CONFIG_SPL_MMC_BOOT 57 #endif 58 59 #ifdef CONFIG_SPL_BUILD 60 #define CONFIG_SPL_SKIP_RELOCATE 61 #define CONFIG_SPL_COMMON_INIT_DDR 62 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 63 #define CONFIG_SYS_NO_FLASH 64 #endif 65 66 #endif 67 #endif /* CONFIG_RAMBOOT_PBL */ 68 69 #define CONFIG_DDR_ECC 70 71 #define CONFIG_CMD_REGINFO 72 73 /* High Level Configuration Options */ 74 #define CONFIG_BOOKE 75 #define CONFIG_E500 /* BOOKE e500 family */ 76 #define CONFIG_E500MC /* BOOKE e500mc family */ 77 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 78 #define CONFIG_MP /* support multiple processors */ 79 80 #ifndef CONFIG_SYS_TEXT_BASE 81 #define CONFIG_SYS_TEXT_BASE 0xeff40000 82 #endif 83 84 #ifndef CONFIG_RESET_VECTOR_ADDRESS 85 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 86 #endif 87 88 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 89 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 90 #define CONFIG_FSL_IFC /* Enable IFC Support */ 91 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 92 #define CONFIG_PCI /* Enable PCI/PCIE */ 93 #define CONFIG_PCIE1 /* PCIE controller 1 */ 94 #define CONFIG_PCIE2 /* PCIE controller 2 */ 95 #define CONFIG_PCIE3 /* PCIE controller 3 */ 96 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 97 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 98 99 #define CONFIG_FSL_LAW /* Use common FSL init code */ 100 101 #define CONFIG_ENV_OVERWRITE 102 103 /* 104 * These can be toggled for performance analysis, otherwise use default. 105 */ 106 #define CONFIG_SYS_CACHE_STASHING 107 #define CONFIG_BTB /* toggle branch predition */ 108 #ifdef CONFIG_DDR_ECC 109 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 110 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 111 #endif 112 113 #define CONFIG_ENABLE_36BIT_PHYS 114 115 #define CONFIG_ADDR_MAP 116 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 117 118 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 119 #define CONFIG_SYS_MEMTEST_END 0x00400000 120 #define CONFIG_SYS_ALT_MEMTEST 121 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 122 123 /* 124 * Config the L3 Cache as L3 SRAM 125 */ 126 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 127 #define CONFIG_SYS_L3_SIZE (512 << 10) 128 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 129 #ifdef CONFIG_RAMBOOT_PBL 130 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 131 #endif 132 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 133 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 134 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 135 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 136 137 #define CONFIG_SYS_DCSRBAR 0xf0000000 138 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 139 140 /* 141 * DDR Setup 142 */ 143 #define CONFIG_VERY_BIG_RAM 144 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 145 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 146 147 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 148 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 149 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 150 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 151 152 #define CONFIG_DDR_SPD 153 #define CONFIG_SYS_FSL_DDR3 154 155 /* 156 * IFC Definitions 157 */ 158 #define CONFIG_SYS_FLASH_BASE 0xe0000000 159 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 160 161 #ifdef CONFIG_SPL_BUILD 162 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 163 #else 164 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 165 #endif 166 167 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 168 #define CONFIG_MISC_INIT_R 169 170 #define CONFIG_HWCONFIG 171 172 /* define to use L1 as initial stack */ 173 #define CONFIG_L1_INIT_RAM 174 #define CONFIG_SYS_INIT_RAM_LOCK 175 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 176 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 177 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 178 /* The assembler doesn't like typecast */ 179 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 180 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 181 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 182 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 183 184 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 185 GENERATED_GBL_DATA_SIZE) 186 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 187 188 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 189 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 190 191 /* Serial Port - controlled on board with jumper J8 192 * open - index 2 193 * shorted - index 1 194 */ 195 #define CONFIG_CONS_INDEX 1 196 #define CONFIG_SYS_NS16550_SERIAL 197 #define CONFIG_SYS_NS16550_REG_SIZE 1 198 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 199 200 #define CONFIG_SYS_BAUDRATE_TABLE \ 201 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 202 203 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 204 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 205 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 206 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 207 208 /* I2C */ 209 #define CONFIG_SYS_I2C 210 #define CONFIG_SYS_I2C_FSL 211 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 212 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 213 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 214 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 215 216 /* 217 * General PCI 218 * Memory space is mapped 1-1, but I/O space must start from 0. 219 */ 220 221 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 222 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 223 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 224 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 225 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 226 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 227 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 228 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 229 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 230 231 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 232 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 233 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 234 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 235 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 236 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 237 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 238 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 239 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 240 241 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 242 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 243 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 244 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 245 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 246 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 247 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 248 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 249 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 250 251 /* controller 4, Base address 203000 */ 252 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 253 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 254 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 255 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 256 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 257 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 258 259 #ifdef CONFIG_PCI 260 #define CONFIG_PCI_INDIRECT_BRIDGE 261 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 262 263 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 264 #define CONFIG_DOS_PARTITION 265 #endif /* CONFIG_PCI */ 266 267 /* SATA */ 268 #ifdef CONFIG_FSL_SATA_V2 269 #define CONFIG_LIBATA 270 #define CONFIG_FSL_SATA 271 272 #define CONFIG_SYS_SATA_MAX_DEVICE 2 273 #define CONFIG_SATA1 274 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 275 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 276 #define CONFIG_SATA2 277 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 278 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 279 280 #define CONFIG_LBA48 281 #define CONFIG_CMD_SATA 282 #define CONFIG_DOS_PARTITION 283 #endif 284 285 #ifdef CONFIG_FMAN_ENET 286 #define CONFIG_MII /* MII PHY management */ 287 #define CONFIG_ETHPRIME "FM1@DTSEC1" 288 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 289 #endif 290 291 /* 292 * Environment 293 */ 294 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 295 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 296 297 /* 298 * Command line configuration. 299 */ 300 #define CONFIG_CMD_ERRATA 301 #define CONFIG_CMD_IRQ 302 303 #ifdef CONFIG_PCI 304 #define CONFIG_CMD_PCI 305 #endif 306 307 /* 308 * Miscellaneous configurable options 309 */ 310 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 311 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 312 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 313 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 314 #ifdef CONFIG_CMD_KGDB 315 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 316 #else 317 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 318 #endif 319 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 320 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 321 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 322 323 /* 324 * For booting Linux, the board info and command line data 325 * have to be in the first 64 MB of memory, since this is 326 * the maximum mapped by the Linux kernel during initialization. 327 */ 328 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 329 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 330 331 #ifdef CONFIG_CMD_KGDB 332 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 333 #endif 334 335 /* 336 * Environment Configuration 337 */ 338 #define CONFIG_ROOTPATH "/opt/nfsroot" 339 #define CONFIG_BOOTFILE "uImage" 340 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 341 342 /* default location for tftp and bootm */ 343 #define CONFIG_LOADADDR 1000000 344 345 #define CONFIG_BAUDRATE 115200 346 347 #define CONFIG_HVBOOT \ 348 "setenv bootargs config-addr=0x60000000; " \ 349 "bootm 0x01000000 - 0x00f00000" 350 351 #ifdef CONFIG_SYS_NO_FLASH 352 #ifndef CONFIG_RAMBOOT_PBL 353 #define CONFIG_ENV_IS_NOWHERE 354 #endif 355 #else 356 #define CONFIG_FLASH_CFI_DRIVER 357 #define CONFIG_SYS_FLASH_CFI 358 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 359 #endif 360 361 #if defined(CONFIG_SPIFLASH) 362 #define CONFIG_SYS_EXTRA_ENV_RELOC 363 #define CONFIG_ENV_IS_IN_SPI_FLASH 364 #define CONFIG_ENV_SPI_BUS 0 365 #define CONFIG_ENV_SPI_CS 0 366 #define CONFIG_ENV_SPI_MAX_HZ 10000000 367 #define CONFIG_ENV_SPI_MODE 0 368 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 369 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 370 #define CONFIG_ENV_SECT_SIZE 0x10000 371 #elif defined(CONFIG_SDCARD) 372 #define CONFIG_SYS_EXTRA_ENV_RELOC 373 #define CONFIG_ENV_IS_IN_MMC 374 #define CONFIG_SYS_MMC_ENV_DEV 0 375 #define CONFIG_ENV_SIZE 0x2000 376 #define CONFIG_ENV_OFFSET (512 * 0x800) 377 #elif defined(CONFIG_NAND) 378 #define CONFIG_SYS_EXTRA_ENV_RELOC 379 #define CONFIG_ENV_IS_IN_NAND 380 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 381 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 382 #elif defined(CONFIG_ENV_IS_NOWHERE) 383 #define CONFIG_ENV_SIZE 0x2000 384 #else 385 #define CONFIG_ENV_IS_IN_FLASH 386 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 387 #define CONFIG_ENV_SIZE 0x2000 388 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 389 #endif 390 391 #define CONFIG_SYS_CLK_FREQ 66666666 392 #define CONFIG_DDR_CLK_FREQ 133333333 393 394 #ifndef __ASSEMBLY__ 395 unsigned long get_board_sys_clk(void); 396 unsigned long get_board_ddr_clk(void); 397 #endif 398 399 /* 400 * DDR Setup 401 */ 402 #define CONFIG_SYS_SPD_BUS_NUM 0 403 #define SPD_EEPROM_ADDRESS1 0x52 404 #define SPD_EEPROM_ADDRESS2 0x54 405 #define SPD_EEPROM_ADDRESS3 0x56 406 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 407 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 408 409 /* 410 * IFC Definitions 411 */ 412 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 413 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 414 + 0x8000000) | \ 415 CSPR_PORT_SIZE_16 | \ 416 CSPR_MSEL_NOR | \ 417 CSPR_V) 418 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 419 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 420 CSPR_PORT_SIZE_16 | \ 421 CSPR_MSEL_NOR | \ 422 CSPR_V) 423 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 424 /* NOR Flash Timing Params */ 425 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 426 427 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 428 FTIM0_NOR_TEADC(0x5) | \ 429 FTIM0_NOR_TEAHC(0x5)) 430 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 431 FTIM1_NOR_TRAD_NOR(0x1A) |\ 432 FTIM1_NOR_TSEQRAD_NOR(0x13)) 433 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 434 FTIM2_NOR_TCH(0x4) | \ 435 FTIM2_NOR_TWPH(0x0E) | \ 436 FTIM2_NOR_TWP(0x1c)) 437 #define CONFIG_SYS_NOR_FTIM3 0x0 438 439 #define CONFIG_SYS_FLASH_QUIET_TEST 440 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 441 442 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 443 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 444 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 445 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 446 447 #define CONFIG_SYS_FLASH_EMPTY_INFO 448 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 449 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 450 451 /* NAND Flash on IFC */ 452 #define CONFIG_NAND_FSL_IFC 453 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 454 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 455 #define CONFIG_SYS_NAND_BASE 0xff800000 456 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 457 458 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 459 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 460 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 461 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 462 | CSPR_V) 463 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 464 465 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 466 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 467 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 468 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 469 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 470 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 471 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 472 473 #define CONFIG_SYS_NAND_ONFI_DETECTION 474 475 /* ONFI NAND Flash mode0 Timing Params */ 476 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 477 FTIM0_NAND_TWP(0x18) | \ 478 FTIM0_NAND_TWCHT(0x07) | \ 479 FTIM0_NAND_TWH(0x0a)) 480 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 481 FTIM1_NAND_TWBE(0x39) | \ 482 FTIM1_NAND_TRR(0x0e) | \ 483 FTIM1_NAND_TRP(0x18)) 484 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 485 FTIM2_NAND_TREH(0x0a) | \ 486 FTIM2_NAND_TWHRE(0x1e)) 487 #define CONFIG_SYS_NAND_FTIM3 0x0 488 489 #define CONFIG_SYS_NAND_DDR_LAW 11 490 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 491 #define CONFIG_SYS_MAX_NAND_DEVICE 1 492 #define CONFIG_CMD_NAND 493 494 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 495 496 #if defined(CONFIG_NAND) 497 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 498 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 499 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 500 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 501 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 502 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 503 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 504 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 505 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 506 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 507 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 508 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 509 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 510 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 511 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 512 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 513 #else 514 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 515 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 516 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 517 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 518 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 519 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 520 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 521 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 522 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 523 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 524 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 525 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 526 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 527 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 528 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 529 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 530 #endif 531 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 532 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 533 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 534 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 535 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 536 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 537 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 538 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 539 540 /* CPLD on IFC */ 541 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 542 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 543 #define CONFIG_SYS_CSPR3_EXT (0xf) 544 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 545 | CSPR_PORT_SIZE_8 \ 546 | CSPR_MSEL_GPCM \ 547 | CSPR_V) 548 549 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 550 #define CONFIG_SYS_CSOR3 0x0 551 552 /* CPLD Timing parameters for IFC CS3 */ 553 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 554 FTIM0_GPCM_TEADC(0x0e) | \ 555 FTIM0_GPCM_TEAHC(0x0e)) 556 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 557 FTIM1_GPCM_TRAD(0x1f)) 558 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 559 FTIM2_GPCM_TCH(0x8) | \ 560 FTIM2_GPCM_TWP(0x1f)) 561 #define CONFIG_SYS_CS3_FTIM3 0x0 562 563 #if defined(CONFIG_RAMBOOT_PBL) 564 #define CONFIG_SYS_RAMBOOT 565 #endif 566 567 /* I2C */ 568 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 569 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 570 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 571 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 572 573 #define I2C_MUX_CH_DEFAULT 0x8 574 #define I2C_MUX_CH_VOL_MONITOR 0xa 575 #define I2C_MUX_CH_VSC3316_FS 0xc 576 #define I2C_MUX_CH_VSC3316_BS 0xd 577 578 /* Voltage monitor on channel 2*/ 579 #define I2C_VOL_MONITOR_ADDR 0x40 580 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 581 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 582 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 583 584 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 585 #ifndef CONFIG_SPL_BUILD 586 #define CONFIG_VID 587 #endif 588 #define CONFIG_VOL_MONITOR_IR36021_SET 589 #define CONFIG_VOL_MONITOR_IR36021_READ 590 /* The lowest and highest voltage allowed for T4240RDB */ 591 #define VDD_MV_MIN 819 592 #define VDD_MV_MAX 1212 593 594 /* 595 * eSPI - Enhanced SPI 596 */ 597 #define CONFIG_SF_DEFAULT_SPEED 10000000 598 #define CONFIG_SF_DEFAULT_MODE 0 599 600 /* Qman/Bman */ 601 #ifndef CONFIG_NOBQFMAN 602 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 603 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 604 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 605 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 606 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 607 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 608 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 609 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 610 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 611 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 612 CONFIG_SYS_BMAN_CENA_SIZE) 613 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 614 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 615 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 616 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 617 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 618 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 619 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 620 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 621 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 622 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 623 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 624 CONFIG_SYS_QMAN_CENA_SIZE) 625 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 626 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 627 628 #define CONFIG_SYS_DPAA_FMAN 629 #define CONFIG_SYS_DPAA_PME 630 #define CONFIG_SYS_PMAN 631 #define CONFIG_SYS_DPAA_DCE 632 #define CONFIG_SYS_DPAA_RMAN 633 #define CONFIG_SYS_INTERLAKEN 634 635 /* Default address of microcode for the Linux Fman driver */ 636 #if defined(CONFIG_SPIFLASH) 637 /* 638 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 639 * env, so we got 0x110000. 640 */ 641 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 642 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 643 #elif defined(CONFIG_SDCARD) 644 /* 645 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 646 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 647 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 648 */ 649 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 650 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 651 #elif defined(CONFIG_NAND) 652 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 653 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 654 #else 655 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 656 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 657 #endif 658 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 659 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 660 #endif /* CONFIG_NOBQFMAN */ 661 662 #ifdef CONFIG_SYS_DPAA_FMAN 663 #define CONFIG_FMAN_ENET 664 #define CONFIG_PHYLIB_10G 665 #define CONFIG_PHY_VITESSE 666 #define CONFIG_PHY_CORTINA 667 #define CONFIG_SYS_CORTINA_FW_IN_NOR 668 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 669 #define CONFIG_CORTINA_FW_LENGTH 0x40000 670 #define CONFIG_PHY_TERANETICS 671 #define SGMII_PHY_ADDR1 0x0 672 #define SGMII_PHY_ADDR2 0x1 673 #define SGMII_PHY_ADDR3 0x2 674 #define SGMII_PHY_ADDR4 0x3 675 #define SGMII_PHY_ADDR5 0x4 676 #define SGMII_PHY_ADDR6 0x5 677 #define SGMII_PHY_ADDR7 0x6 678 #define SGMII_PHY_ADDR8 0x7 679 #define FM1_10GEC1_PHY_ADDR 0x10 680 #define FM1_10GEC2_PHY_ADDR 0x11 681 #define FM2_10GEC1_PHY_ADDR 0x12 682 #define FM2_10GEC2_PHY_ADDR 0x13 683 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 684 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 685 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 686 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 687 #endif 688 689 /* SATA */ 690 #ifdef CONFIG_FSL_SATA_V2 691 #define CONFIG_LIBATA 692 #define CONFIG_FSL_SATA 693 694 #define CONFIG_SYS_SATA_MAX_DEVICE 2 695 #define CONFIG_SATA1 696 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 697 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 698 #define CONFIG_SATA2 699 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 700 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 701 702 #define CONFIG_LBA48 703 #define CONFIG_CMD_SATA 704 #define CONFIG_DOS_PARTITION 705 #endif 706 707 #ifdef CONFIG_FMAN_ENET 708 #define CONFIG_MII /* MII PHY management */ 709 #define CONFIG_ETHPRIME "FM1@DTSEC1" 710 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 711 #endif 712 713 /* 714 * USB 715 */ 716 #define CONFIG_USB_EHCI 717 #define CONFIG_USB_EHCI_FSL 718 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 719 #define CONFIG_HAS_FSL_DR_USB 720 721 #define CONFIG_MMC 722 723 #ifdef CONFIG_MMC 724 #define CONFIG_FSL_ESDHC 725 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 726 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 727 #define CONFIG_GENERIC_MMC 728 #define CONFIG_DOS_PARTITION 729 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 730 #endif 731 732 /* Hash command with SHA acceleration supported in hardware */ 733 #ifdef CONFIG_FSL_CAAM 734 #define CONFIG_CMD_HASH 735 #define CONFIG_SHA_HW_ACCEL 736 #endif 737 738 739 #define __USB_PHY_TYPE utmi 740 741 /* 742 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 743 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 744 * interleaving. It can be cacheline, page, bank, superbank. 745 * See doc/README.fsl-ddr for details. 746 */ 747 #ifdef CONFIG_PPC_T4240 748 #define CTRL_INTLV_PREFERED 3way_4KB 749 #else 750 #define CTRL_INTLV_PREFERED cacheline 751 #endif 752 753 #define CONFIG_EXTRA_ENV_SETTINGS \ 754 "hwconfig=fsl_ddr:" \ 755 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 756 "bank_intlv=auto;" \ 757 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 758 "netdev=eth0\0" \ 759 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 760 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 761 "tftpflash=tftpboot $loadaddr $uboot && " \ 762 "protect off $ubootaddr +$filesize && " \ 763 "erase $ubootaddr +$filesize && " \ 764 "cp.b $loadaddr $ubootaddr $filesize && " \ 765 "protect on $ubootaddr +$filesize && " \ 766 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 767 "consoledev=ttyS0\0" \ 768 "ramdiskaddr=2000000\0" \ 769 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 770 "fdtaddr=1e00000\0" \ 771 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 772 "bdev=sda3\0" 773 774 #define CONFIG_HVBOOT \ 775 "setenv bootargs config-addr=0x60000000; " \ 776 "bootm 0x01000000 - 0x00f00000" 777 778 #define CONFIG_LINUX \ 779 "setenv bootargs root=/dev/ram rw " \ 780 "console=$consoledev,$baudrate $othbootargs;" \ 781 "setenv ramdiskaddr 0x02000000;" \ 782 "setenv fdtaddr 0x00c00000;" \ 783 "setenv loadaddr 0x1000000;" \ 784 "bootm $loadaddr $ramdiskaddr $fdtaddr" 785 786 #define CONFIG_HDBOOT \ 787 "setenv bootargs root=/dev/$bdev rw " \ 788 "console=$consoledev,$baudrate $othbootargs;" \ 789 "tftp $loadaddr $bootfile;" \ 790 "tftp $fdtaddr $fdtfile;" \ 791 "bootm $loadaddr - $fdtaddr" 792 793 #define CONFIG_NFSBOOTCOMMAND \ 794 "setenv bootargs root=/dev/nfs rw " \ 795 "nfsroot=$serverip:$rootpath " \ 796 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 797 "console=$consoledev,$baudrate $othbootargs;" \ 798 "tftp $loadaddr $bootfile;" \ 799 "tftp $fdtaddr $fdtfile;" \ 800 "bootm $loadaddr - $fdtaddr" 801 802 #define CONFIG_RAMBOOTCOMMAND \ 803 "setenv bootargs root=/dev/ram rw " \ 804 "console=$consoledev,$baudrate $othbootargs;" \ 805 "tftp $ramdiskaddr $ramdiskfile;" \ 806 "tftp $loadaddr $bootfile;" \ 807 "tftp $fdtaddr $fdtfile;" \ 808 "bootm $loadaddr $ramdiskaddr $fdtaddr" 809 810 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 811 812 #include <asm/fsl_secure_boot.h> 813 814 #endif /* __CONFIG_H */ 815