1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240RDB 14 #define CONFIG_PHYS_64BIT 15 #define CONFIG_DISPLAY_BOARDINFO 16 17 #define CONFIG_FSL_SATA_V2 18 #define CONFIG_PCIE4 19 20 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 21 22 #ifdef CONFIG_RAMBOOT_PBL 23 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 24 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg 25 #ifndef CONFIG_SDCARD 26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 28 #else 29 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 30 #define CONFIG_SPL_ENV_SUPPORT 31 #define CONFIG_SPL_SERIAL_SUPPORT 32 #define CONFIG_SPL_FLUSH_IMAGE 33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 34 #define CONFIG_SPL_LIBGENERIC_SUPPORT 35 #define CONFIG_SPL_LIBCOMMON_SUPPORT 36 #define CONFIG_SPL_I2C_SUPPORT 37 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 38 #define CONFIG_FSL_LAW /* Use common FSL init code */ 39 #define CONFIG_SYS_TEXT_BASE 0x00201000 40 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 41 #define CONFIG_SPL_PAD_TO 0x40000 42 #define CONFIG_SPL_MAX_SIZE 0x28000 43 #define RESET_VECTOR_OFFSET 0x27FFC 44 #define BOOT_PAGE_OFFSET 0x27000 45 46 #ifdef CONFIG_SDCARD 47 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 48 #define CONFIG_SPL_MMC_SUPPORT 49 #define CONFIG_SPL_MMC_MINIMAL 50 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 51 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 52 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 53 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 54 #ifndef CONFIG_SPL_BUILD 55 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 56 #endif 57 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 58 #define CONFIG_SPL_MMC_BOOT 59 #endif 60 61 #ifdef CONFIG_SPL_BUILD 62 #define CONFIG_SPL_SKIP_RELOCATE 63 #define CONFIG_SPL_COMMON_INIT_DDR 64 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 65 #define CONFIG_SYS_NO_FLASH 66 #endif 67 68 #endif 69 #endif /* CONFIG_RAMBOOT_PBL */ 70 71 #define CONFIG_DDR_ECC 72 73 #define CONFIG_CMD_REGINFO 74 75 /* High Level Configuration Options */ 76 #define CONFIG_BOOKE 77 #define CONFIG_E500 /* BOOKE e500 family */ 78 #define CONFIG_E500MC /* BOOKE e500mc family */ 79 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 80 #define CONFIG_MP /* support multiple processors */ 81 82 #ifndef CONFIG_SYS_TEXT_BASE 83 #define CONFIG_SYS_TEXT_BASE 0xeff40000 84 #endif 85 86 #ifndef CONFIG_RESET_VECTOR_ADDRESS 87 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 88 #endif 89 90 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 91 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 92 #define CONFIG_FSL_IFC /* Enable IFC Support */ 93 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 94 #define CONFIG_PCI /* Enable PCI/PCIE */ 95 #define CONFIG_PCIE1 /* PCIE controler 1 */ 96 #define CONFIG_PCIE2 /* PCIE controler 2 */ 97 #define CONFIG_PCIE3 /* PCIE controler 3 */ 98 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 99 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 100 101 #define CONFIG_FSL_LAW /* Use common FSL init code */ 102 103 #define CONFIG_ENV_OVERWRITE 104 105 /* 106 * These can be toggled for performance analysis, otherwise use default. 107 */ 108 #define CONFIG_SYS_CACHE_STASHING 109 #define CONFIG_BTB /* toggle branch predition */ 110 #ifdef CONFIG_DDR_ECC 111 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 112 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 113 #endif 114 115 #define CONFIG_ENABLE_36BIT_PHYS 116 117 #define CONFIG_ADDR_MAP 118 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 119 120 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 121 #define CONFIG_SYS_MEMTEST_END 0x00400000 122 #define CONFIG_SYS_ALT_MEMTEST 123 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 124 125 /* 126 * Config the L3 Cache as L3 SRAM 127 */ 128 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 129 #define CONFIG_SYS_L3_SIZE (512 << 10) 130 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 131 #ifdef CONFIG_RAMBOOT_PBL 132 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 133 #endif 134 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 135 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 136 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 137 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 138 139 #define CONFIG_SYS_DCSRBAR 0xf0000000 140 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 141 142 /* 143 * DDR Setup 144 */ 145 #define CONFIG_VERY_BIG_RAM 146 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 147 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 148 149 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 150 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 151 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 152 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 153 154 #define CONFIG_DDR_SPD 155 #define CONFIG_SYS_FSL_DDR3 156 157 /* 158 * IFC Definitions 159 */ 160 #define CONFIG_SYS_FLASH_BASE 0xe0000000 161 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 162 163 #ifdef CONFIG_SPL_BUILD 164 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 165 #else 166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 167 #endif 168 169 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 170 #define CONFIG_MISC_INIT_R 171 172 #define CONFIG_HWCONFIG 173 174 /* define to use L1 as initial stack */ 175 #define CONFIG_L1_INIT_RAM 176 #define CONFIG_SYS_INIT_RAM_LOCK 177 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 178 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 179 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 180 /* The assembler doesn't like typecast */ 181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 182 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 183 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 184 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 185 186 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 187 GENERATED_GBL_DATA_SIZE) 188 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 189 190 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 191 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 192 193 /* Serial Port - controlled on board with jumper J8 194 * open - index 2 195 * shorted - index 1 196 */ 197 #define CONFIG_CONS_INDEX 1 198 #define CONFIG_SYS_NS16550_SERIAL 199 #define CONFIG_SYS_NS16550_REG_SIZE 1 200 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 201 202 #define CONFIG_SYS_BAUDRATE_TABLE \ 203 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 204 205 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 206 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 207 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 208 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 209 210 /* I2C */ 211 #define CONFIG_SYS_I2C 212 #define CONFIG_SYS_I2C_FSL 213 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 214 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 215 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 216 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 217 218 /* 219 * General PCI 220 * Memory space is mapped 1-1, but I/O space must start from 0. 221 */ 222 223 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 224 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 225 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 226 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 227 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 228 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 229 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 230 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 231 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 232 233 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 234 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 235 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 236 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 237 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 238 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 239 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 240 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 241 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 242 243 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 244 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 245 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 246 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 247 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 248 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 249 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 250 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 251 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 252 253 /* controller 4, Base address 203000 */ 254 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 255 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 256 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 257 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 258 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 259 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 260 261 #ifdef CONFIG_PCI 262 #define CONFIG_PCI_INDIRECT_BRIDGE 263 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 264 265 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 266 #define CONFIG_DOS_PARTITION 267 #endif /* CONFIG_PCI */ 268 269 /* SATA */ 270 #ifdef CONFIG_FSL_SATA_V2 271 #define CONFIG_LIBATA 272 #define CONFIG_FSL_SATA 273 274 #define CONFIG_SYS_SATA_MAX_DEVICE 2 275 #define CONFIG_SATA1 276 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 277 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 278 #define CONFIG_SATA2 279 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 280 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 281 282 #define CONFIG_LBA48 283 #define CONFIG_CMD_SATA 284 #define CONFIG_DOS_PARTITION 285 #define CONFIG_CMD_EXT2 286 #endif 287 288 #ifdef CONFIG_FMAN_ENET 289 #define CONFIG_MII /* MII PHY management */ 290 #define CONFIG_ETHPRIME "FM1@DTSEC1" 291 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 292 #endif 293 294 /* 295 * Environment 296 */ 297 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 298 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 299 300 /* 301 * Command line configuration. 302 */ 303 #define CONFIG_CMD_ERRATA 304 #define CONFIG_CMD_GREPENV 305 #define CONFIG_CMD_IRQ 306 #define CONFIG_CMD_MII 307 308 #ifdef CONFIG_PCI 309 #define CONFIG_CMD_PCI 310 #endif 311 312 /* 313 * Miscellaneous configurable options 314 */ 315 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 316 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 317 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 318 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 319 #ifdef CONFIG_CMD_KGDB 320 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 321 #else 322 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 323 #endif 324 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 325 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 326 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 327 328 /* 329 * For booting Linux, the board info and command line data 330 * have to be in the first 64 MB of memory, since this is 331 * the maximum mapped by the Linux kernel during initialization. 332 */ 333 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 334 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 335 336 #ifdef CONFIG_CMD_KGDB 337 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 338 #endif 339 340 /* 341 * Environment Configuration 342 */ 343 #define CONFIG_ROOTPATH "/opt/nfsroot" 344 #define CONFIG_BOOTFILE "uImage" 345 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 346 347 /* default location for tftp and bootm */ 348 #define CONFIG_LOADADDR 1000000 349 350 #define CONFIG_BAUDRATE 115200 351 352 #define CONFIG_HVBOOT \ 353 "setenv bootargs config-addr=0x60000000; " \ 354 "bootm 0x01000000 - 0x00f00000" 355 356 #ifdef CONFIG_SYS_NO_FLASH 357 #ifndef CONFIG_RAMBOOT_PBL 358 #define CONFIG_ENV_IS_NOWHERE 359 #endif 360 #else 361 #define CONFIG_FLASH_CFI_DRIVER 362 #define CONFIG_SYS_FLASH_CFI 363 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 364 #endif 365 366 #if defined(CONFIG_SPIFLASH) 367 #define CONFIG_SYS_EXTRA_ENV_RELOC 368 #define CONFIG_ENV_IS_IN_SPI_FLASH 369 #define CONFIG_ENV_SPI_BUS 0 370 #define CONFIG_ENV_SPI_CS 0 371 #define CONFIG_ENV_SPI_MAX_HZ 10000000 372 #define CONFIG_ENV_SPI_MODE 0 373 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 374 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 375 #define CONFIG_ENV_SECT_SIZE 0x10000 376 #elif defined(CONFIG_SDCARD) 377 #define CONFIG_SYS_EXTRA_ENV_RELOC 378 #define CONFIG_ENV_IS_IN_MMC 379 #define CONFIG_SYS_MMC_ENV_DEV 0 380 #define CONFIG_ENV_SIZE 0x2000 381 #define CONFIG_ENV_OFFSET (512 * 0x800) 382 #elif defined(CONFIG_NAND) 383 #define CONFIG_SYS_EXTRA_ENV_RELOC 384 #define CONFIG_ENV_IS_IN_NAND 385 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 386 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 387 #elif defined(CONFIG_ENV_IS_NOWHERE) 388 #define CONFIG_ENV_SIZE 0x2000 389 #else 390 #define CONFIG_ENV_IS_IN_FLASH 391 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 392 #define CONFIG_ENV_SIZE 0x2000 393 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 394 #endif 395 396 #define CONFIG_SYS_CLK_FREQ 66666666 397 #define CONFIG_DDR_CLK_FREQ 133333333 398 399 #ifndef __ASSEMBLY__ 400 unsigned long get_board_sys_clk(void); 401 unsigned long get_board_ddr_clk(void); 402 #endif 403 404 /* 405 * DDR Setup 406 */ 407 #define CONFIG_SYS_SPD_BUS_NUM 0 408 #define SPD_EEPROM_ADDRESS1 0x52 409 #define SPD_EEPROM_ADDRESS2 0x54 410 #define SPD_EEPROM_ADDRESS3 0x56 411 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 412 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 413 414 /* 415 * IFC Definitions 416 */ 417 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 418 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 419 + 0x8000000) | \ 420 CSPR_PORT_SIZE_16 | \ 421 CSPR_MSEL_NOR | \ 422 CSPR_V) 423 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 424 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 425 CSPR_PORT_SIZE_16 | \ 426 CSPR_MSEL_NOR | \ 427 CSPR_V) 428 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 429 /* NOR Flash Timing Params */ 430 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 431 432 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 433 FTIM0_NOR_TEADC(0x5) | \ 434 FTIM0_NOR_TEAHC(0x5)) 435 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 436 FTIM1_NOR_TRAD_NOR(0x1A) |\ 437 FTIM1_NOR_TSEQRAD_NOR(0x13)) 438 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 439 FTIM2_NOR_TCH(0x4) | \ 440 FTIM2_NOR_TWPH(0x0E) | \ 441 FTIM2_NOR_TWP(0x1c)) 442 #define CONFIG_SYS_NOR_FTIM3 0x0 443 444 #define CONFIG_SYS_FLASH_QUIET_TEST 445 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 446 447 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 448 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 449 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 450 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 451 452 #define CONFIG_SYS_FLASH_EMPTY_INFO 453 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 454 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 455 456 /* NAND Flash on IFC */ 457 #define CONFIG_NAND_FSL_IFC 458 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 459 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 460 #define CONFIG_SYS_NAND_BASE 0xff800000 461 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 462 463 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 464 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 465 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 466 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 467 | CSPR_V) 468 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 469 470 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 471 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 472 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 473 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 474 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 475 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 476 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 477 478 #define CONFIG_SYS_NAND_ONFI_DETECTION 479 480 /* ONFI NAND Flash mode0 Timing Params */ 481 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 482 FTIM0_NAND_TWP(0x18) | \ 483 FTIM0_NAND_TWCHT(0x07) | \ 484 FTIM0_NAND_TWH(0x0a)) 485 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 486 FTIM1_NAND_TWBE(0x39) | \ 487 FTIM1_NAND_TRR(0x0e) | \ 488 FTIM1_NAND_TRP(0x18)) 489 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 490 FTIM2_NAND_TREH(0x0a) | \ 491 FTIM2_NAND_TWHRE(0x1e)) 492 #define CONFIG_SYS_NAND_FTIM3 0x0 493 494 #define CONFIG_SYS_NAND_DDR_LAW 11 495 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 496 #define CONFIG_SYS_MAX_NAND_DEVICE 1 497 #define CONFIG_CMD_NAND 498 499 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 500 501 #if defined(CONFIG_NAND) 502 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 503 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 504 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 505 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 506 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 507 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 508 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 509 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 510 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 511 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 512 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 513 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 514 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 515 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 516 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 517 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 518 #else 519 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 520 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 521 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 522 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 523 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 524 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 525 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 526 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 527 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 528 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 529 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 530 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 531 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 532 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 533 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 534 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 535 #endif 536 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 537 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 538 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 539 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 540 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 541 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 542 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 543 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 544 545 /* CPLD on IFC */ 546 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 547 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 548 #define CONFIG_SYS_CSPR3_EXT (0xf) 549 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 550 | CSPR_PORT_SIZE_8 \ 551 | CSPR_MSEL_GPCM \ 552 | CSPR_V) 553 554 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 555 #define CONFIG_SYS_CSOR3 0x0 556 557 /* CPLD Timing parameters for IFC CS3 */ 558 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 559 FTIM0_GPCM_TEADC(0x0e) | \ 560 FTIM0_GPCM_TEAHC(0x0e)) 561 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 562 FTIM1_GPCM_TRAD(0x1f)) 563 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 564 FTIM2_GPCM_TCH(0x8) | \ 565 FTIM2_GPCM_TWP(0x1f)) 566 #define CONFIG_SYS_CS3_FTIM3 0x0 567 568 #if defined(CONFIG_RAMBOOT_PBL) 569 #define CONFIG_SYS_RAMBOOT 570 #endif 571 572 /* I2C */ 573 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 574 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 575 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 576 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 577 578 #define I2C_MUX_CH_DEFAULT 0x8 579 #define I2C_MUX_CH_VOL_MONITOR 0xa 580 #define I2C_MUX_CH_VSC3316_FS 0xc 581 #define I2C_MUX_CH_VSC3316_BS 0xd 582 583 /* Voltage monitor on channel 2*/ 584 #define I2C_VOL_MONITOR_ADDR 0x40 585 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 586 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 587 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 588 589 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 590 #ifndef CONFIG_SPL_BUILD 591 #define CONFIG_VID 592 #endif 593 #define CONFIG_VOL_MONITOR_IR36021_SET 594 #define CONFIG_VOL_MONITOR_IR36021_READ 595 /* The lowest and highest voltage allowed for T4240RDB */ 596 #define VDD_MV_MIN 819 597 #define VDD_MV_MAX 1212 598 599 /* 600 * eSPI - Enhanced SPI 601 */ 602 #define CONFIG_SF_DEFAULT_SPEED 10000000 603 #define CONFIG_SF_DEFAULT_MODE 0 604 605 /* Qman/Bman */ 606 #ifndef CONFIG_NOBQFMAN 607 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 608 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 609 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 610 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 611 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 612 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 613 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 614 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 615 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 616 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 617 CONFIG_SYS_BMAN_CENA_SIZE) 618 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 619 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 620 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 621 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 622 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 623 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 624 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 625 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 626 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 627 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 628 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 629 CONFIG_SYS_QMAN_CENA_SIZE) 630 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 631 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 632 633 #define CONFIG_SYS_DPAA_FMAN 634 #define CONFIG_SYS_DPAA_PME 635 #define CONFIG_SYS_PMAN 636 #define CONFIG_SYS_DPAA_DCE 637 #define CONFIG_SYS_DPAA_RMAN 638 #define CONFIG_SYS_INTERLAKEN 639 640 /* Default address of microcode for the Linux Fman driver */ 641 #if defined(CONFIG_SPIFLASH) 642 /* 643 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 644 * env, so we got 0x110000. 645 */ 646 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 647 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 648 #elif defined(CONFIG_SDCARD) 649 /* 650 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 651 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 652 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 653 */ 654 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 655 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 656 #elif defined(CONFIG_NAND) 657 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 658 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 659 #else 660 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 661 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 662 #endif 663 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 664 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 665 #endif /* CONFIG_NOBQFMAN */ 666 667 #ifdef CONFIG_SYS_DPAA_FMAN 668 #define CONFIG_FMAN_ENET 669 #define CONFIG_PHYLIB_10G 670 #define CONFIG_PHY_VITESSE 671 #define CONFIG_PHY_CORTINA 672 #define CONFIG_SYS_CORTINA_FW_IN_NOR 673 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 674 #define CONFIG_CORTINA_FW_LENGTH 0x40000 675 #define CONFIG_PHY_TERANETICS 676 #define SGMII_PHY_ADDR1 0x0 677 #define SGMII_PHY_ADDR2 0x1 678 #define SGMII_PHY_ADDR3 0x2 679 #define SGMII_PHY_ADDR4 0x3 680 #define SGMII_PHY_ADDR5 0x4 681 #define SGMII_PHY_ADDR6 0x5 682 #define SGMII_PHY_ADDR7 0x6 683 #define SGMII_PHY_ADDR8 0x7 684 #define FM1_10GEC1_PHY_ADDR 0x10 685 #define FM1_10GEC2_PHY_ADDR 0x11 686 #define FM2_10GEC1_PHY_ADDR 0x12 687 #define FM2_10GEC2_PHY_ADDR 0x13 688 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 689 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 690 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 691 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 692 #endif 693 694 /* SATA */ 695 #ifdef CONFIG_FSL_SATA_V2 696 #define CONFIG_LIBATA 697 #define CONFIG_FSL_SATA 698 699 #define CONFIG_SYS_SATA_MAX_DEVICE 2 700 #define CONFIG_SATA1 701 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 702 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 703 #define CONFIG_SATA2 704 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 705 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 706 707 #define CONFIG_LBA48 708 #define CONFIG_CMD_SATA 709 #define CONFIG_DOS_PARTITION 710 #define CONFIG_CMD_EXT2 711 #endif 712 713 #ifdef CONFIG_FMAN_ENET 714 #define CONFIG_MII /* MII PHY management */ 715 #define CONFIG_ETHPRIME "FM1@DTSEC1" 716 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 717 #endif 718 719 /* 720 * USB 721 */ 722 #define CONFIG_USB_STORAGE 723 #define CONFIG_USB_EHCI 724 #define CONFIG_USB_EHCI_FSL 725 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 726 #define CONFIG_CMD_EXT2 727 #define CONFIG_HAS_FSL_DR_USB 728 729 #define CONFIG_MMC 730 731 #ifdef CONFIG_MMC 732 #define CONFIG_FSL_ESDHC 733 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 734 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 735 #define CONFIG_CMD_MMC 736 #define CONFIG_GENERIC_MMC 737 #define CONFIG_CMD_EXT2 738 #define CONFIG_CMD_FAT 739 #define CONFIG_DOS_PARTITION 740 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 741 #endif 742 743 /* Hash command with SHA acceleration supported in hardware */ 744 #ifdef CONFIG_FSL_CAAM 745 #define CONFIG_CMD_HASH 746 #define CONFIG_SHA_HW_ACCEL 747 #endif 748 749 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 750 751 #define __USB_PHY_TYPE utmi 752 753 /* 754 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 755 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 756 * interleaving. It can be cacheline, page, bank, superbank. 757 * See doc/README.fsl-ddr for details. 758 */ 759 #ifdef CONFIG_PPC_T4240 760 #define CTRL_INTLV_PREFERED 3way_4KB 761 #else 762 #define CTRL_INTLV_PREFERED cacheline 763 #endif 764 765 #define CONFIG_EXTRA_ENV_SETTINGS \ 766 "hwconfig=fsl_ddr:" \ 767 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 768 "bank_intlv=auto;" \ 769 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 770 "netdev=eth0\0" \ 771 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 772 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 773 "tftpflash=tftpboot $loadaddr $uboot && " \ 774 "protect off $ubootaddr +$filesize && " \ 775 "erase $ubootaddr +$filesize && " \ 776 "cp.b $loadaddr $ubootaddr $filesize && " \ 777 "protect on $ubootaddr +$filesize && " \ 778 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 779 "consoledev=ttyS0\0" \ 780 "ramdiskaddr=2000000\0" \ 781 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 782 "fdtaddr=c00000\0" \ 783 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 784 "bdev=sda3\0" 785 786 #define CONFIG_HVBOOT \ 787 "setenv bootargs config-addr=0x60000000; " \ 788 "bootm 0x01000000 - 0x00f00000" 789 790 #define CONFIG_LINUX \ 791 "setenv bootargs root=/dev/ram rw " \ 792 "console=$consoledev,$baudrate $othbootargs;" \ 793 "setenv ramdiskaddr 0x02000000;" \ 794 "setenv fdtaddr 0x00c00000;" \ 795 "setenv loadaddr 0x1000000;" \ 796 "bootm $loadaddr $ramdiskaddr $fdtaddr" 797 798 #define CONFIG_HDBOOT \ 799 "setenv bootargs root=/dev/$bdev rw " \ 800 "console=$consoledev,$baudrate $othbootargs;" \ 801 "tftp $loadaddr $bootfile;" \ 802 "tftp $fdtaddr $fdtfile;" \ 803 "bootm $loadaddr - $fdtaddr" 804 805 #define CONFIG_NFSBOOTCOMMAND \ 806 "setenv bootargs root=/dev/nfs rw " \ 807 "nfsroot=$serverip:$rootpath " \ 808 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 809 "console=$consoledev,$baudrate $othbootargs;" \ 810 "tftp $loadaddr $bootfile;" \ 811 "tftp $fdtaddr $fdtfile;" \ 812 "bootm $loadaddr - $fdtaddr" 813 814 #define CONFIG_RAMBOOTCOMMAND \ 815 "setenv bootargs root=/dev/ram rw " \ 816 "console=$consoledev,$baudrate $othbootargs;" \ 817 "tftp $ramdiskaddr $ramdiskfile;" \ 818 "tftp $loadaddr $bootfile;" \ 819 "tftp $fdtaddr $fdtfile;" \ 820 "bootm $loadaddr $ramdiskaddr $fdtaddr" 821 822 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 823 824 #include <asm/fsl_secure_boot.h> 825 826 #endif /* __CONFIG_H */ 827