1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240RDB 14 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_PCIE4 17 18 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 19 20 #ifdef CONFIG_RAMBOOT_PBL 21 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 22 #ifndef CONFIG_SDCARD 23 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 25 #else 26 #define CONFIG_SPL_FLUSH_IMAGE 27 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 28 #define CONFIG_FSL_LAW /* Use common FSL init code */ 29 #define CONFIG_SYS_TEXT_BASE 0x00201000 30 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 31 #define CONFIG_SPL_PAD_TO 0x40000 32 #define CONFIG_SPL_MAX_SIZE 0x28000 33 #define RESET_VECTOR_OFFSET 0x27FFC 34 #define BOOT_PAGE_OFFSET 0x27000 35 36 #ifdef CONFIG_SDCARD 37 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 38 #define CONFIG_SPL_MMC_MINIMAL 39 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 40 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 41 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 42 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 43 #ifndef CONFIG_SPL_BUILD 44 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 45 #endif 46 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 47 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg 48 #define CONFIG_SPL_MMC_BOOT 49 #endif 50 51 #ifdef CONFIG_SPL_BUILD 52 #define CONFIG_SPL_SKIP_RELOCATE 53 #define CONFIG_SPL_COMMON_INIT_DDR 54 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 55 #define CONFIG_SYS_NO_FLASH 56 #endif 57 58 #endif 59 #endif /* CONFIG_RAMBOOT_PBL */ 60 61 #define CONFIG_DDR_ECC 62 63 #define CONFIG_CMD_REGINFO 64 65 /* High Level Configuration Options */ 66 #define CONFIG_BOOKE 67 #define CONFIG_E500 /* BOOKE e500 family */ 68 #define CONFIG_E500MC /* BOOKE e500mc family */ 69 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 70 #define CONFIG_MP /* support multiple processors */ 71 72 #ifndef CONFIG_SYS_TEXT_BASE 73 #define CONFIG_SYS_TEXT_BASE 0xeff40000 74 #endif 75 76 #ifndef CONFIG_RESET_VECTOR_ADDRESS 77 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 78 #endif 79 80 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 81 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 82 #define CONFIG_FSL_IFC /* Enable IFC Support */ 83 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 84 #define CONFIG_PCIE1 /* PCIE controller 1 */ 85 #define CONFIG_PCIE2 /* PCIE controller 2 */ 86 #define CONFIG_PCIE3 /* PCIE controller 3 */ 87 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 88 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 89 90 #define CONFIG_FSL_LAW /* Use common FSL init code */ 91 92 #define CONFIG_ENV_OVERWRITE 93 94 /* 95 * These can be toggled for performance analysis, otherwise use default. 96 */ 97 #define CONFIG_SYS_CACHE_STASHING 98 #define CONFIG_BTB /* toggle branch predition */ 99 #ifdef CONFIG_DDR_ECC 100 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 101 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 102 #endif 103 104 #define CONFIG_ENABLE_36BIT_PHYS 105 106 #define CONFIG_ADDR_MAP 107 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 108 109 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 110 #define CONFIG_SYS_MEMTEST_END 0x00400000 111 #define CONFIG_SYS_ALT_MEMTEST 112 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 113 114 /* 115 * Config the L3 Cache as L3 SRAM 116 */ 117 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 118 #define CONFIG_SYS_L3_SIZE (512 << 10) 119 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 120 #ifdef CONFIG_RAMBOOT_PBL 121 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 122 #endif 123 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 124 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 125 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 126 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 127 128 #define CONFIG_SYS_DCSRBAR 0xf0000000 129 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 130 131 /* 132 * DDR Setup 133 */ 134 #define CONFIG_VERY_BIG_RAM 135 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 136 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 137 138 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 139 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 140 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 141 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 142 143 #define CONFIG_DDR_SPD 144 #define CONFIG_SYS_FSL_DDR3 145 146 /* 147 * IFC Definitions 148 */ 149 #define CONFIG_SYS_FLASH_BASE 0xe0000000 150 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 151 152 #ifdef CONFIG_SPL_BUILD 153 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 154 #else 155 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 156 #endif 157 158 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 159 #define CONFIG_MISC_INIT_R 160 161 #define CONFIG_HWCONFIG 162 163 /* define to use L1 as initial stack */ 164 #define CONFIG_L1_INIT_RAM 165 #define CONFIG_SYS_INIT_RAM_LOCK 166 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 167 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 168 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 169 /* The assembler doesn't like typecast */ 170 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 171 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 172 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 173 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 174 175 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 176 GENERATED_GBL_DATA_SIZE) 177 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 178 179 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 180 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 181 182 /* Serial Port - controlled on board with jumper J8 183 * open - index 2 184 * shorted - index 1 185 */ 186 #define CONFIG_CONS_INDEX 1 187 #define CONFIG_SYS_NS16550_SERIAL 188 #define CONFIG_SYS_NS16550_REG_SIZE 1 189 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 190 191 #define CONFIG_SYS_BAUDRATE_TABLE \ 192 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 193 194 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 195 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 196 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 197 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 198 199 /* I2C */ 200 #define CONFIG_SYS_I2C 201 #define CONFIG_SYS_I2C_FSL 202 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 203 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 204 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 205 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 206 207 /* 208 * General PCI 209 * Memory space is mapped 1-1, but I/O space must start from 0. 210 */ 211 212 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 213 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 214 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 215 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 216 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 217 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 218 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 219 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 220 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 221 222 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 223 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 224 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 225 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 226 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 227 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 228 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 229 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 230 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 231 232 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 233 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 234 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 235 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 236 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 237 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 238 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 239 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 240 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 241 242 /* controller 4, Base address 203000 */ 243 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 244 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 245 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 246 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 247 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 248 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 249 250 #ifdef CONFIG_PCI 251 #define CONFIG_PCI_INDIRECT_BRIDGE 252 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 253 254 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 255 #define CONFIG_DOS_PARTITION 256 #endif /* CONFIG_PCI */ 257 258 /* SATA */ 259 #ifdef CONFIG_FSL_SATA_V2 260 #define CONFIG_LIBATA 261 #define CONFIG_FSL_SATA 262 263 #define CONFIG_SYS_SATA_MAX_DEVICE 2 264 #define CONFIG_SATA1 265 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 266 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 267 #define CONFIG_SATA2 268 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 269 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 270 271 #define CONFIG_LBA48 272 #define CONFIG_CMD_SATA 273 #define CONFIG_DOS_PARTITION 274 #endif 275 276 #ifdef CONFIG_FMAN_ENET 277 #define CONFIG_MII /* MII PHY management */ 278 #define CONFIG_ETHPRIME "FM1@DTSEC1" 279 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 280 #endif 281 282 /* 283 * Environment 284 */ 285 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 286 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 287 288 /* 289 * Command line configuration. 290 */ 291 #define CONFIG_CMD_ERRATA 292 #define CONFIG_CMD_IRQ 293 294 #ifdef CONFIG_PCI 295 #define CONFIG_CMD_PCI 296 #endif 297 298 /* 299 * Miscellaneous configurable options 300 */ 301 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 302 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 303 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 304 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 305 #ifdef CONFIG_CMD_KGDB 306 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 307 #else 308 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 309 #endif 310 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 311 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 312 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 313 314 /* 315 * For booting Linux, the board info and command line data 316 * have to be in the first 64 MB of memory, since this is 317 * the maximum mapped by the Linux kernel during initialization. 318 */ 319 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 320 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 321 322 #ifdef CONFIG_CMD_KGDB 323 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 324 #endif 325 326 /* 327 * Environment Configuration 328 */ 329 #define CONFIG_ROOTPATH "/opt/nfsroot" 330 #define CONFIG_BOOTFILE "uImage" 331 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 332 333 /* default location for tftp and bootm */ 334 #define CONFIG_LOADADDR 1000000 335 336 #define CONFIG_BAUDRATE 115200 337 338 #define CONFIG_HVBOOT \ 339 "setenv bootargs config-addr=0x60000000; " \ 340 "bootm 0x01000000 - 0x00f00000" 341 342 #ifdef CONFIG_SYS_NO_FLASH 343 #ifndef CONFIG_RAMBOOT_PBL 344 #define CONFIG_ENV_IS_NOWHERE 345 #endif 346 #else 347 #define CONFIG_FLASH_CFI_DRIVER 348 #define CONFIG_SYS_FLASH_CFI 349 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 350 #endif 351 352 #if defined(CONFIG_SPIFLASH) 353 #define CONFIG_SYS_EXTRA_ENV_RELOC 354 #define CONFIG_ENV_IS_IN_SPI_FLASH 355 #define CONFIG_ENV_SPI_BUS 0 356 #define CONFIG_ENV_SPI_CS 0 357 #define CONFIG_ENV_SPI_MAX_HZ 10000000 358 #define CONFIG_ENV_SPI_MODE 0 359 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 360 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 361 #define CONFIG_ENV_SECT_SIZE 0x10000 362 #elif defined(CONFIG_SDCARD) 363 #define CONFIG_SYS_EXTRA_ENV_RELOC 364 #define CONFIG_ENV_IS_IN_MMC 365 #define CONFIG_SYS_MMC_ENV_DEV 0 366 #define CONFIG_ENV_SIZE 0x2000 367 #define CONFIG_ENV_OFFSET (512 * 0x800) 368 #elif defined(CONFIG_NAND) 369 #define CONFIG_SYS_EXTRA_ENV_RELOC 370 #define CONFIG_ENV_IS_IN_NAND 371 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 372 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 373 #elif defined(CONFIG_ENV_IS_NOWHERE) 374 #define CONFIG_ENV_SIZE 0x2000 375 #else 376 #define CONFIG_ENV_IS_IN_FLASH 377 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 378 #define CONFIG_ENV_SIZE 0x2000 379 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 380 #endif 381 382 #define CONFIG_SYS_CLK_FREQ 66666666 383 #define CONFIG_DDR_CLK_FREQ 133333333 384 385 #ifndef __ASSEMBLY__ 386 unsigned long get_board_sys_clk(void); 387 unsigned long get_board_ddr_clk(void); 388 #endif 389 390 /* 391 * DDR Setup 392 */ 393 #define CONFIG_SYS_SPD_BUS_NUM 0 394 #define SPD_EEPROM_ADDRESS1 0x52 395 #define SPD_EEPROM_ADDRESS2 0x54 396 #define SPD_EEPROM_ADDRESS3 0x56 397 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 398 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 399 400 /* 401 * IFC Definitions 402 */ 403 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 404 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 405 + 0x8000000) | \ 406 CSPR_PORT_SIZE_16 | \ 407 CSPR_MSEL_NOR | \ 408 CSPR_V) 409 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 410 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 411 CSPR_PORT_SIZE_16 | \ 412 CSPR_MSEL_NOR | \ 413 CSPR_V) 414 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 415 /* NOR Flash Timing Params */ 416 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 417 418 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 419 FTIM0_NOR_TEADC(0x5) | \ 420 FTIM0_NOR_TEAHC(0x5)) 421 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 422 FTIM1_NOR_TRAD_NOR(0x1A) |\ 423 FTIM1_NOR_TSEQRAD_NOR(0x13)) 424 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 425 FTIM2_NOR_TCH(0x4) | \ 426 FTIM2_NOR_TWPH(0x0E) | \ 427 FTIM2_NOR_TWP(0x1c)) 428 #define CONFIG_SYS_NOR_FTIM3 0x0 429 430 #define CONFIG_SYS_FLASH_QUIET_TEST 431 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 432 433 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 434 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 435 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 436 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 437 438 #define CONFIG_SYS_FLASH_EMPTY_INFO 439 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 440 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 441 442 /* NAND Flash on IFC */ 443 #define CONFIG_NAND_FSL_IFC 444 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 445 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 446 #define CONFIG_SYS_NAND_BASE 0xff800000 447 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 448 449 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 450 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 451 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 452 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 453 | CSPR_V) 454 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 455 456 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 457 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 458 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 459 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 460 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 461 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 462 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 463 464 #define CONFIG_SYS_NAND_ONFI_DETECTION 465 466 /* ONFI NAND Flash mode0 Timing Params */ 467 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 468 FTIM0_NAND_TWP(0x18) | \ 469 FTIM0_NAND_TWCHT(0x07) | \ 470 FTIM0_NAND_TWH(0x0a)) 471 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 472 FTIM1_NAND_TWBE(0x39) | \ 473 FTIM1_NAND_TRR(0x0e) | \ 474 FTIM1_NAND_TRP(0x18)) 475 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 476 FTIM2_NAND_TREH(0x0a) | \ 477 FTIM2_NAND_TWHRE(0x1e)) 478 #define CONFIG_SYS_NAND_FTIM3 0x0 479 480 #define CONFIG_SYS_NAND_DDR_LAW 11 481 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 482 #define CONFIG_SYS_MAX_NAND_DEVICE 1 483 #define CONFIG_CMD_NAND 484 485 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 486 487 #if defined(CONFIG_NAND) 488 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 489 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 490 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 491 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 492 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 493 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 494 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 495 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 496 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 497 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 498 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 499 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 500 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 501 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 502 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 503 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 504 #else 505 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 506 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 507 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 508 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 509 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 510 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 511 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 512 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 513 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 514 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 515 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 516 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 517 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 518 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 519 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 520 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 521 #endif 522 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 523 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 524 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 525 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 526 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 527 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 528 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 529 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 530 531 /* CPLD on IFC */ 532 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 533 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 534 #define CONFIG_SYS_CSPR3_EXT (0xf) 535 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 536 | CSPR_PORT_SIZE_8 \ 537 | CSPR_MSEL_GPCM \ 538 | CSPR_V) 539 540 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 541 #define CONFIG_SYS_CSOR3 0x0 542 543 /* CPLD Timing parameters for IFC CS3 */ 544 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 545 FTIM0_GPCM_TEADC(0x0e) | \ 546 FTIM0_GPCM_TEAHC(0x0e)) 547 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 548 FTIM1_GPCM_TRAD(0x1f)) 549 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 550 FTIM2_GPCM_TCH(0x8) | \ 551 FTIM2_GPCM_TWP(0x1f)) 552 #define CONFIG_SYS_CS3_FTIM3 0x0 553 554 #if defined(CONFIG_RAMBOOT_PBL) 555 #define CONFIG_SYS_RAMBOOT 556 #endif 557 558 /* I2C */ 559 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 560 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 561 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 562 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 563 564 #define I2C_MUX_CH_DEFAULT 0x8 565 #define I2C_MUX_CH_VOL_MONITOR 0xa 566 #define I2C_MUX_CH_VSC3316_FS 0xc 567 #define I2C_MUX_CH_VSC3316_BS 0xd 568 569 /* Voltage monitor on channel 2*/ 570 #define I2C_VOL_MONITOR_ADDR 0x40 571 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 572 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 573 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 574 575 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 576 #ifndef CONFIG_SPL_BUILD 577 #define CONFIG_VID 578 #endif 579 #define CONFIG_VOL_MONITOR_IR36021_SET 580 #define CONFIG_VOL_MONITOR_IR36021_READ 581 /* The lowest and highest voltage allowed for T4240RDB */ 582 #define VDD_MV_MIN 819 583 #define VDD_MV_MAX 1212 584 585 /* 586 * eSPI - Enhanced SPI 587 */ 588 #define CONFIG_SF_DEFAULT_SPEED 10000000 589 #define CONFIG_SF_DEFAULT_MODE 0 590 591 /* Qman/Bman */ 592 #ifndef CONFIG_NOBQFMAN 593 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 594 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 595 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 596 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 597 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 598 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 599 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 600 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 601 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 602 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 603 CONFIG_SYS_BMAN_CENA_SIZE) 604 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 605 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 606 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 607 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 608 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 609 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 610 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 611 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 612 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 613 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 614 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 615 CONFIG_SYS_QMAN_CENA_SIZE) 616 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 617 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 618 619 #define CONFIG_SYS_DPAA_FMAN 620 #define CONFIG_SYS_DPAA_PME 621 #define CONFIG_SYS_PMAN 622 #define CONFIG_SYS_DPAA_DCE 623 #define CONFIG_SYS_DPAA_RMAN 624 #define CONFIG_SYS_INTERLAKEN 625 626 /* Default address of microcode for the Linux Fman driver */ 627 #if defined(CONFIG_SPIFLASH) 628 /* 629 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 630 * env, so we got 0x110000. 631 */ 632 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 633 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 634 #elif defined(CONFIG_SDCARD) 635 /* 636 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 637 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 638 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 639 */ 640 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 641 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 642 #elif defined(CONFIG_NAND) 643 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 644 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 645 #else 646 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 647 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 648 #endif 649 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 650 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 651 #endif /* CONFIG_NOBQFMAN */ 652 653 #ifdef CONFIG_SYS_DPAA_FMAN 654 #define CONFIG_FMAN_ENET 655 #define CONFIG_PHYLIB_10G 656 #define CONFIG_PHY_VITESSE 657 #define CONFIG_PHY_CORTINA 658 #define CONFIG_SYS_CORTINA_FW_IN_NOR 659 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 660 #define CONFIG_CORTINA_FW_LENGTH 0x40000 661 #define CONFIG_PHY_TERANETICS 662 #define SGMII_PHY_ADDR1 0x0 663 #define SGMII_PHY_ADDR2 0x1 664 #define SGMII_PHY_ADDR3 0x2 665 #define SGMII_PHY_ADDR4 0x3 666 #define SGMII_PHY_ADDR5 0x4 667 #define SGMII_PHY_ADDR6 0x5 668 #define SGMII_PHY_ADDR7 0x6 669 #define SGMII_PHY_ADDR8 0x7 670 #define FM1_10GEC1_PHY_ADDR 0x10 671 #define FM1_10GEC2_PHY_ADDR 0x11 672 #define FM2_10GEC1_PHY_ADDR 0x12 673 #define FM2_10GEC2_PHY_ADDR 0x13 674 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 675 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 676 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 677 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 678 #endif 679 680 /* SATA */ 681 #ifdef CONFIG_FSL_SATA_V2 682 #define CONFIG_LIBATA 683 #define CONFIG_FSL_SATA 684 685 #define CONFIG_SYS_SATA_MAX_DEVICE 2 686 #define CONFIG_SATA1 687 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 688 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 689 #define CONFIG_SATA2 690 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 691 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 692 693 #define CONFIG_LBA48 694 #define CONFIG_CMD_SATA 695 #define CONFIG_DOS_PARTITION 696 #endif 697 698 #ifdef CONFIG_FMAN_ENET 699 #define CONFIG_MII /* MII PHY management */ 700 #define CONFIG_ETHPRIME "FM1@DTSEC1" 701 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 702 #endif 703 704 /* 705 * USB 706 */ 707 #define CONFIG_USB_EHCI 708 #define CONFIG_USB_EHCI_FSL 709 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 710 #define CONFIG_HAS_FSL_DR_USB 711 712 #define CONFIG_MMC 713 714 #ifdef CONFIG_MMC 715 #define CONFIG_FSL_ESDHC 716 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 717 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 718 #define CONFIG_GENERIC_MMC 719 #define CONFIG_DOS_PARTITION 720 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 721 #endif 722 723 /* Hash command with SHA acceleration supported in hardware */ 724 #ifdef CONFIG_FSL_CAAM 725 #define CONFIG_CMD_HASH 726 #define CONFIG_SHA_HW_ACCEL 727 #endif 728 729 730 #define __USB_PHY_TYPE utmi 731 732 /* 733 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 734 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 735 * interleaving. It can be cacheline, page, bank, superbank. 736 * See doc/README.fsl-ddr for details. 737 */ 738 #ifdef CONFIG_PPC_T4240 739 #define CTRL_INTLV_PREFERED 3way_4KB 740 #else 741 #define CTRL_INTLV_PREFERED cacheline 742 #endif 743 744 #define CONFIG_EXTRA_ENV_SETTINGS \ 745 "hwconfig=fsl_ddr:" \ 746 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 747 "bank_intlv=auto;" \ 748 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 749 "netdev=eth0\0" \ 750 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 751 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 752 "tftpflash=tftpboot $loadaddr $uboot && " \ 753 "protect off $ubootaddr +$filesize && " \ 754 "erase $ubootaddr +$filesize && " \ 755 "cp.b $loadaddr $ubootaddr $filesize && " \ 756 "protect on $ubootaddr +$filesize && " \ 757 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 758 "consoledev=ttyS0\0" \ 759 "ramdiskaddr=2000000\0" \ 760 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 761 "fdtaddr=1e00000\0" \ 762 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 763 "bdev=sda3\0" 764 765 #define CONFIG_HVBOOT \ 766 "setenv bootargs config-addr=0x60000000; " \ 767 "bootm 0x01000000 - 0x00f00000" 768 769 #define CONFIG_LINUX \ 770 "setenv bootargs root=/dev/ram rw " \ 771 "console=$consoledev,$baudrate $othbootargs;" \ 772 "setenv ramdiskaddr 0x02000000;" \ 773 "setenv fdtaddr 0x00c00000;" \ 774 "setenv loadaddr 0x1000000;" \ 775 "bootm $loadaddr $ramdiskaddr $fdtaddr" 776 777 #define CONFIG_HDBOOT \ 778 "setenv bootargs root=/dev/$bdev rw " \ 779 "console=$consoledev,$baudrate $othbootargs;" \ 780 "tftp $loadaddr $bootfile;" \ 781 "tftp $fdtaddr $fdtfile;" \ 782 "bootm $loadaddr - $fdtaddr" 783 784 #define CONFIG_NFSBOOTCOMMAND \ 785 "setenv bootargs root=/dev/nfs rw " \ 786 "nfsroot=$serverip:$rootpath " \ 787 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 788 "console=$consoledev,$baudrate $othbootargs;" \ 789 "tftp $loadaddr $bootfile;" \ 790 "tftp $fdtaddr $fdtfile;" \ 791 "bootm $loadaddr - $fdtaddr" 792 793 #define CONFIG_RAMBOOTCOMMAND \ 794 "setenv bootargs root=/dev/ram rw " \ 795 "console=$consoledev,$baudrate $othbootargs;" \ 796 "tftp $ramdiskaddr $ramdiskfile;" \ 797 "tftp $loadaddr $bootfile;" \ 798 "tftp $fdtaddr $fdtfile;" \ 799 "bootm $loadaddr $ramdiskaddr $fdtaddr" 800 801 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 802 803 #include <asm/fsl_secure_boot.h> 804 805 #endif /* __CONFIG_H */ 806