1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240RDB 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_FSL_SATA_V2 17 #define CONFIG_PCIE4 18 19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 23 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg 24 #ifndef CONFIG_SDCARD 25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #else 28 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 29 #define CONFIG_SPL_SERIAL_SUPPORT 30 #define CONFIG_SPL_FLUSH_IMAGE 31 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 32 #define CONFIG_SPL_LIBGENERIC_SUPPORT 33 #define CONFIG_SPL_LIBCOMMON_SUPPORT 34 #define CONFIG_SPL_I2C_SUPPORT 35 #define CONFIG_FSL_LAW /* Use common FSL init code */ 36 #define CONFIG_SYS_TEXT_BASE 0x00201000 37 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 38 #define CONFIG_SPL_PAD_TO 0x40000 39 #define CONFIG_SPL_MAX_SIZE 0x28000 40 #define RESET_VECTOR_OFFSET 0x27FFC 41 #define BOOT_PAGE_OFFSET 0x27000 42 43 #ifdef CONFIG_SDCARD 44 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 45 #define CONFIG_SPL_MMC_SUPPORT 46 #define CONFIG_SPL_MMC_MINIMAL 47 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 48 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 49 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 50 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 51 #ifndef CONFIG_SPL_BUILD 52 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 53 #endif 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 55 #define CONFIG_SPL_MMC_BOOT 56 #endif 57 58 #ifdef CONFIG_SPL_BUILD 59 #define CONFIG_SPL_SKIP_RELOCATE 60 #define CONFIG_SPL_COMMON_INIT_DDR 61 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 62 #define CONFIG_SYS_NO_FLASH 63 #endif 64 65 #endif 66 #endif /* CONFIG_RAMBOOT_PBL */ 67 68 #define CONFIG_DDR_ECC 69 70 #define CONFIG_CMD_REGINFO 71 72 /* High Level Configuration Options */ 73 #define CONFIG_BOOKE 74 #define CONFIG_E500 /* BOOKE e500 family */ 75 #define CONFIG_E500MC /* BOOKE e500mc family */ 76 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 77 #define CONFIG_MP /* support multiple processors */ 78 79 #ifndef CONFIG_SYS_TEXT_BASE 80 #define CONFIG_SYS_TEXT_BASE 0xeff40000 81 #endif 82 83 #ifndef CONFIG_RESET_VECTOR_ADDRESS 84 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 85 #endif 86 87 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 88 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 89 #define CONFIG_FSL_IFC /* Enable IFC Support */ 90 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 91 #define CONFIG_PCI /* Enable PCI/PCIE */ 92 #define CONFIG_PCIE1 /* PCIE controller 1 */ 93 #define CONFIG_PCIE2 /* PCIE controller 2 */ 94 #define CONFIG_PCIE3 /* PCIE controller 3 */ 95 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 96 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 97 98 #define CONFIG_FSL_LAW /* Use common FSL init code */ 99 100 #define CONFIG_ENV_OVERWRITE 101 102 /* 103 * These can be toggled for performance analysis, otherwise use default. 104 */ 105 #define CONFIG_SYS_CACHE_STASHING 106 #define CONFIG_BTB /* toggle branch predition */ 107 #ifdef CONFIG_DDR_ECC 108 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 109 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 110 #endif 111 112 #define CONFIG_ENABLE_36BIT_PHYS 113 114 #define CONFIG_ADDR_MAP 115 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 116 117 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 118 #define CONFIG_SYS_MEMTEST_END 0x00400000 119 #define CONFIG_SYS_ALT_MEMTEST 120 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 121 122 /* 123 * Config the L3 Cache as L3 SRAM 124 */ 125 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 126 #define CONFIG_SYS_L3_SIZE (512 << 10) 127 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 128 #ifdef CONFIG_RAMBOOT_PBL 129 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 130 #endif 131 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 132 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 133 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 134 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 135 136 #define CONFIG_SYS_DCSRBAR 0xf0000000 137 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 138 139 /* 140 * DDR Setup 141 */ 142 #define CONFIG_VERY_BIG_RAM 143 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 144 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 145 146 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 147 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 148 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 149 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 150 151 #define CONFIG_DDR_SPD 152 #define CONFIG_SYS_FSL_DDR3 153 154 /* 155 * IFC Definitions 156 */ 157 #define CONFIG_SYS_FLASH_BASE 0xe0000000 158 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 159 160 #ifdef CONFIG_SPL_BUILD 161 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 162 #else 163 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 164 #endif 165 166 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 167 #define CONFIG_MISC_INIT_R 168 169 #define CONFIG_HWCONFIG 170 171 /* define to use L1 as initial stack */ 172 #define CONFIG_L1_INIT_RAM 173 #define CONFIG_SYS_INIT_RAM_LOCK 174 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 175 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 176 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 177 /* The assembler doesn't like typecast */ 178 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 179 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 180 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 181 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 182 183 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 184 GENERATED_GBL_DATA_SIZE) 185 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 186 187 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 188 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 189 190 /* Serial Port - controlled on board with jumper J8 191 * open - index 2 192 * shorted - index 1 193 */ 194 #define CONFIG_CONS_INDEX 1 195 #define CONFIG_SYS_NS16550_SERIAL 196 #define CONFIG_SYS_NS16550_REG_SIZE 1 197 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 198 199 #define CONFIG_SYS_BAUDRATE_TABLE \ 200 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 201 202 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 203 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 204 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 205 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 206 207 /* I2C */ 208 #define CONFIG_SYS_I2C 209 #define CONFIG_SYS_I2C_FSL 210 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 211 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 212 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 213 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 214 215 /* 216 * General PCI 217 * Memory space is mapped 1-1, but I/O space must start from 0. 218 */ 219 220 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 221 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 222 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 223 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 224 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 225 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 226 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 227 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 228 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 229 230 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 231 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 232 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 233 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 234 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 235 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 236 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 237 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 238 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 239 240 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 241 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 242 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 243 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 244 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 245 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 246 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 247 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 248 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 249 250 /* controller 4, Base address 203000 */ 251 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 252 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 253 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 254 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 255 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 256 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 257 258 #ifdef CONFIG_PCI 259 #define CONFIG_PCI_INDIRECT_BRIDGE 260 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 261 262 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 263 #define CONFIG_DOS_PARTITION 264 #endif /* CONFIG_PCI */ 265 266 /* SATA */ 267 #ifdef CONFIG_FSL_SATA_V2 268 #define CONFIG_LIBATA 269 #define CONFIG_FSL_SATA 270 271 #define CONFIG_SYS_SATA_MAX_DEVICE 2 272 #define CONFIG_SATA1 273 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 274 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 275 #define CONFIG_SATA2 276 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 277 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 278 279 #define CONFIG_LBA48 280 #define CONFIG_CMD_SATA 281 #define CONFIG_DOS_PARTITION 282 #endif 283 284 #ifdef CONFIG_FMAN_ENET 285 #define CONFIG_MII /* MII PHY management */ 286 #define CONFIG_ETHPRIME "FM1@DTSEC1" 287 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 288 #endif 289 290 /* 291 * Environment 292 */ 293 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 294 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 295 296 /* 297 * Command line configuration. 298 */ 299 #define CONFIG_CMD_ERRATA 300 #define CONFIG_CMD_IRQ 301 302 #ifdef CONFIG_PCI 303 #define CONFIG_CMD_PCI 304 #endif 305 306 /* 307 * Miscellaneous configurable options 308 */ 309 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 310 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 311 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 312 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 313 #ifdef CONFIG_CMD_KGDB 314 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 315 #else 316 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 317 #endif 318 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 319 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 320 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 321 322 /* 323 * For booting Linux, the board info and command line data 324 * have to be in the first 64 MB of memory, since this is 325 * the maximum mapped by the Linux kernel during initialization. 326 */ 327 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 328 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 329 330 #ifdef CONFIG_CMD_KGDB 331 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 332 #endif 333 334 /* 335 * Environment Configuration 336 */ 337 #define CONFIG_ROOTPATH "/opt/nfsroot" 338 #define CONFIG_BOOTFILE "uImage" 339 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 340 341 /* default location for tftp and bootm */ 342 #define CONFIG_LOADADDR 1000000 343 344 #define CONFIG_BAUDRATE 115200 345 346 #define CONFIG_HVBOOT \ 347 "setenv bootargs config-addr=0x60000000; " \ 348 "bootm 0x01000000 - 0x00f00000" 349 350 #ifdef CONFIG_SYS_NO_FLASH 351 #ifndef CONFIG_RAMBOOT_PBL 352 #define CONFIG_ENV_IS_NOWHERE 353 #endif 354 #else 355 #define CONFIG_FLASH_CFI_DRIVER 356 #define CONFIG_SYS_FLASH_CFI 357 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 358 #endif 359 360 #if defined(CONFIG_SPIFLASH) 361 #define CONFIG_SYS_EXTRA_ENV_RELOC 362 #define CONFIG_ENV_IS_IN_SPI_FLASH 363 #define CONFIG_ENV_SPI_BUS 0 364 #define CONFIG_ENV_SPI_CS 0 365 #define CONFIG_ENV_SPI_MAX_HZ 10000000 366 #define CONFIG_ENV_SPI_MODE 0 367 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 368 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 369 #define CONFIG_ENV_SECT_SIZE 0x10000 370 #elif defined(CONFIG_SDCARD) 371 #define CONFIG_SYS_EXTRA_ENV_RELOC 372 #define CONFIG_ENV_IS_IN_MMC 373 #define CONFIG_SYS_MMC_ENV_DEV 0 374 #define CONFIG_ENV_SIZE 0x2000 375 #define CONFIG_ENV_OFFSET (512 * 0x800) 376 #elif defined(CONFIG_NAND) 377 #define CONFIG_SYS_EXTRA_ENV_RELOC 378 #define CONFIG_ENV_IS_IN_NAND 379 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 380 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 381 #elif defined(CONFIG_ENV_IS_NOWHERE) 382 #define CONFIG_ENV_SIZE 0x2000 383 #else 384 #define CONFIG_ENV_IS_IN_FLASH 385 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 386 #define CONFIG_ENV_SIZE 0x2000 387 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 388 #endif 389 390 #define CONFIG_SYS_CLK_FREQ 66666666 391 #define CONFIG_DDR_CLK_FREQ 133333333 392 393 #ifndef __ASSEMBLY__ 394 unsigned long get_board_sys_clk(void); 395 unsigned long get_board_ddr_clk(void); 396 #endif 397 398 /* 399 * DDR Setup 400 */ 401 #define CONFIG_SYS_SPD_BUS_NUM 0 402 #define SPD_EEPROM_ADDRESS1 0x52 403 #define SPD_EEPROM_ADDRESS2 0x54 404 #define SPD_EEPROM_ADDRESS3 0x56 405 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 406 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 407 408 /* 409 * IFC Definitions 410 */ 411 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 412 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 413 + 0x8000000) | \ 414 CSPR_PORT_SIZE_16 | \ 415 CSPR_MSEL_NOR | \ 416 CSPR_V) 417 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 418 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 419 CSPR_PORT_SIZE_16 | \ 420 CSPR_MSEL_NOR | \ 421 CSPR_V) 422 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 423 /* NOR Flash Timing Params */ 424 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 425 426 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 427 FTIM0_NOR_TEADC(0x5) | \ 428 FTIM0_NOR_TEAHC(0x5)) 429 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 430 FTIM1_NOR_TRAD_NOR(0x1A) |\ 431 FTIM1_NOR_TSEQRAD_NOR(0x13)) 432 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 433 FTIM2_NOR_TCH(0x4) | \ 434 FTIM2_NOR_TWPH(0x0E) | \ 435 FTIM2_NOR_TWP(0x1c)) 436 #define CONFIG_SYS_NOR_FTIM3 0x0 437 438 #define CONFIG_SYS_FLASH_QUIET_TEST 439 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 440 441 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 442 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 443 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 444 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 445 446 #define CONFIG_SYS_FLASH_EMPTY_INFO 447 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 448 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 449 450 /* NAND Flash on IFC */ 451 #define CONFIG_NAND_FSL_IFC 452 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 453 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 454 #define CONFIG_SYS_NAND_BASE 0xff800000 455 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 456 457 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 458 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 459 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 460 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 461 | CSPR_V) 462 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 463 464 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 465 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 466 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 467 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 468 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 469 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 470 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 471 472 #define CONFIG_SYS_NAND_ONFI_DETECTION 473 474 /* ONFI NAND Flash mode0 Timing Params */ 475 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 476 FTIM0_NAND_TWP(0x18) | \ 477 FTIM0_NAND_TWCHT(0x07) | \ 478 FTIM0_NAND_TWH(0x0a)) 479 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 480 FTIM1_NAND_TWBE(0x39) | \ 481 FTIM1_NAND_TRR(0x0e) | \ 482 FTIM1_NAND_TRP(0x18)) 483 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 484 FTIM2_NAND_TREH(0x0a) | \ 485 FTIM2_NAND_TWHRE(0x1e)) 486 #define CONFIG_SYS_NAND_FTIM3 0x0 487 488 #define CONFIG_SYS_NAND_DDR_LAW 11 489 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 490 #define CONFIG_SYS_MAX_NAND_DEVICE 1 491 #define CONFIG_CMD_NAND 492 493 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 494 495 #if defined(CONFIG_NAND) 496 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 497 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 498 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 499 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 500 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 501 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 502 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 503 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 504 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 505 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 506 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 507 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 508 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 509 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 510 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 511 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 512 #else 513 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 514 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 515 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 516 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 517 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 518 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 519 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 520 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 521 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 522 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 523 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 524 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 525 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 526 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 527 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 528 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 529 #endif 530 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 531 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 532 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 533 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 534 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 535 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 536 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 537 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 538 539 /* CPLD on IFC */ 540 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 541 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 542 #define CONFIG_SYS_CSPR3_EXT (0xf) 543 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 544 | CSPR_PORT_SIZE_8 \ 545 | CSPR_MSEL_GPCM \ 546 | CSPR_V) 547 548 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 549 #define CONFIG_SYS_CSOR3 0x0 550 551 /* CPLD Timing parameters for IFC CS3 */ 552 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 553 FTIM0_GPCM_TEADC(0x0e) | \ 554 FTIM0_GPCM_TEAHC(0x0e)) 555 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 556 FTIM1_GPCM_TRAD(0x1f)) 557 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 558 FTIM2_GPCM_TCH(0x8) | \ 559 FTIM2_GPCM_TWP(0x1f)) 560 #define CONFIG_SYS_CS3_FTIM3 0x0 561 562 #if defined(CONFIG_RAMBOOT_PBL) 563 #define CONFIG_SYS_RAMBOOT 564 #endif 565 566 /* I2C */ 567 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 568 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 569 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 570 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 571 572 #define I2C_MUX_CH_DEFAULT 0x8 573 #define I2C_MUX_CH_VOL_MONITOR 0xa 574 #define I2C_MUX_CH_VSC3316_FS 0xc 575 #define I2C_MUX_CH_VSC3316_BS 0xd 576 577 /* Voltage monitor on channel 2*/ 578 #define I2C_VOL_MONITOR_ADDR 0x40 579 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 580 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 581 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 582 583 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 584 #ifndef CONFIG_SPL_BUILD 585 #define CONFIG_VID 586 #endif 587 #define CONFIG_VOL_MONITOR_IR36021_SET 588 #define CONFIG_VOL_MONITOR_IR36021_READ 589 /* The lowest and highest voltage allowed for T4240RDB */ 590 #define VDD_MV_MIN 819 591 #define VDD_MV_MAX 1212 592 593 /* 594 * eSPI - Enhanced SPI 595 */ 596 #define CONFIG_SF_DEFAULT_SPEED 10000000 597 #define CONFIG_SF_DEFAULT_MODE 0 598 599 /* Qman/Bman */ 600 #ifndef CONFIG_NOBQFMAN 601 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 602 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 603 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 604 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 605 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 606 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 607 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 608 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 609 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 610 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 611 CONFIG_SYS_BMAN_CENA_SIZE) 612 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 613 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 614 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 615 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 616 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 617 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 618 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 619 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 620 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 621 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 622 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 623 CONFIG_SYS_QMAN_CENA_SIZE) 624 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 625 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 626 627 #define CONFIG_SYS_DPAA_FMAN 628 #define CONFIG_SYS_DPAA_PME 629 #define CONFIG_SYS_PMAN 630 #define CONFIG_SYS_DPAA_DCE 631 #define CONFIG_SYS_DPAA_RMAN 632 #define CONFIG_SYS_INTERLAKEN 633 634 /* Default address of microcode for the Linux Fman driver */ 635 #if defined(CONFIG_SPIFLASH) 636 /* 637 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 638 * env, so we got 0x110000. 639 */ 640 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 641 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 642 #elif defined(CONFIG_SDCARD) 643 /* 644 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 645 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 646 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 647 */ 648 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 649 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 650 #elif defined(CONFIG_NAND) 651 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 652 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 653 #else 654 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 655 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 656 #endif 657 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 658 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 659 #endif /* CONFIG_NOBQFMAN */ 660 661 #ifdef CONFIG_SYS_DPAA_FMAN 662 #define CONFIG_FMAN_ENET 663 #define CONFIG_PHYLIB_10G 664 #define CONFIG_PHY_VITESSE 665 #define CONFIG_PHY_CORTINA 666 #define CONFIG_SYS_CORTINA_FW_IN_NOR 667 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 668 #define CONFIG_CORTINA_FW_LENGTH 0x40000 669 #define CONFIG_PHY_TERANETICS 670 #define SGMII_PHY_ADDR1 0x0 671 #define SGMII_PHY_ADDR2 0x1 672 #define SGMII_PHY_ADDR3 0x2 673 #define SGMII_PHY_ADDR4 0x3 674 #define SGMII_PHY_ADDR5 0x4 675 #define SGMII_PHY_ADDR6 0x5 676 #define SGMII_PHY_ADDR7 0x6 677 #define SGMII_PHY_ADDR8 0x7 678 #define FM1_10GEC1_PHY_ADDR 0x10 679 #define FM1_10GEC2_PHY_ADDR 0x11 680 #define FM2_10GEC1_PHY_ADDR 0x12 681 #define FM2_10GEC2_PHY_ADDR 0x13 682 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 683 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 684 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 685 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 686 #endif 687 688 /* SATA */ 689 #ifdef CONFIG_FSL_SATA_V2 690 #define CONFIG_LIBATA 691 #define CONFIG_FSL_SATA 692 693 #define CONFIG_SYS_SATA_MAX_DEVICE 2 694 #define CONFIG_SATA1 695 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 696 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 697 #define CONFIG_SATA2 698 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 699 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 700 701 #define CONFIG_LBA48 702 #define CONFIG_CMD_SATA 703 #define CONFIG_DOS_PARTITION 704 #endif 705 706 #ifdef CONFIG_FMAN_ENET 707 #define CONFIG_MII /* MII PHY management */ 708 #define CONFIG_ETHPRIME "FM1@DTSEC1" 709 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 710 #endif 711 712 /* 713 * USB 714 */ 715 #define CONFIG_USB_EHCI 716 #define CONFIG_USB_EHCI_FSL 717 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 718 #define CONFIG_HAS_FSL_DR_USB 719 720 #define CONFIG_MMC 721 722 #ifdef CONFIG_MMC 723 #define CONFIG_FSL_ESDHC 724 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 725 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 726 #define CONFIG_GENERIC_MMC 727 #define CONFIG_DOS_PARTITION 728 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 729 #endif 730 731 /* Hash command with SHA acceleration supported in hardware */ 732 #ifdef CONFIG_FSL_CAAM 733 #define CONFIG_CMD_HASH 734 #define CONFIG_SHA_HW_ACCEL 735 #endif 736 737 738 #define __USB_PHY_TYPE utmi 739 740 /* 741 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 742 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 743 * interleaving. It can be cacheline, page, bank, superbank. 744 * See doc/README.fsl-ddr for details. 745 */ 746 #ifdef CONFIG_PPC_T4240 747 #define CTRL_INTLV_PREFERED 3way_4KB 748 #else 749 #define CTRL_INTLV_PREFERED cacheline 750 #endif 751 752 #define CONFIG_EXTRA_ENV_SETTINGS \ 753 "hwconfig=fsl_ddr:" \ 754 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 755 "bank_intlv=auto;" \ 756 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 757 "netdev=eth0\0" \ 758 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 759 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 760 "tftpflash=tftpboot $loadaddr $uboot && " \ 761 "protect off $ubootaddr +$filesize && " \ 762 "erase $ubootaddr +$filesize && " \ 763 "cp.b $loadaddr $ubootaddr $filesize && " \ 764 "protect on $ubootaddr +$filesize && " \ 765 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 766 "consoledev=ttyS0\0" \ 767 "ramdiskaddr=2000000\0" \ 768 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 769 "fdtaddr=1e00000\0" \ 770 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 771 "bdev=sda3\0" 772 773 #define CONFIG_HVBOOT \ 774 "setenv bootargs config-addr=0x60000000; " \ 775 "bootm 0x01000000 - 0x00f00000" 776 777 #define CONFIG_LINUX \ 778 "setenv bootargs root=/dev/ram rw " \ 779 "console=$consoledev,$baudrate $othbootargs;" \ 780 "setenv ramdiskaddr 0x02000000;" \ 781 "setenv fdtaddr 0x00c00000;" \ 782 "setenv loadaddr 0x1000000;" \ 783 "bootm $loadaddr $ramdiskaddr $fdtaddr" 784 785 #define CONFIG_HDBOOT \ 786 "setenv bootargs root=/dev/$bdev rw " \ 787 "console=$consoledev,$baudrate $othbootargs;" \ 788 "tftp $loadaddr $bootfile;" \ 789 "tftp $fdtaddr $fdtfile;" \ 790 "bootm $loadaddr - $fdtaddr" 791 792 #define CONFIG_NFSBOOTCOMMAND \ 793 "setenv bootargs root=/dev/nfs rw " \ 794 "nfsroot=$serverip:$rootpath " \ 795 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 796 "console=$consoledev,$baudrate $othbootargs;" \ 797 "tftp $loadaddr $bootfile;" \ 798 "tftp $fdtaddr $fdtfile;" \ 799 "bootm $loadaddr - $fdtaddr" 800 801 #define CONFIG_RAMBOOTCOMMAND \ 802 "setenv bootargs root=/dev/ram rw " \ 803 "console=$consoledev,$baudrate $othbootargs;" \ 804 "tftp $ramdiskaddr $ramdiskfile;" \ 805 "tftp $loadaddr $bootfile;" \ 806 "tftp $fdtaddr $fdtfile;" \ 807 "bootm $loadaddr $ramdiskaddr $fdtaddr" 808 809 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 810 811 #include <asm/fsl_secure_boot.h> 812 813 #endif /* __CONFIG_H */ 814