1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240RDB 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_FSL_SATA_V2 17 #define CONFIG_PCIE4 18 19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 23 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg 24 #ifndef CONFIG_SDCARD 25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #else 28 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 29 #define CONFIG_SPL_SERIAL_SUPPORT 30 #define CONFIG_SPL_FLUSH_IMAGE 31 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 32 #define CONFIG_SPL_LIBGENERIC_SUPPORT 33 #define CONFIG_SPL_LIBCOMMON_SUPPORT 34 #define CONFIG_FSL_LAW /* Use common FSL init code */ 35 #define CONFIG_SYS_TEXT_BASE 0x00201000 36 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 37 #define CONFIG_SPL_PAD_TO 0x40000 38 #define CONFIG_SPL_MAX_SIZE 0x28000 39 #define RESET_VECTOR_OFFSET 0x27FFC 40 #define BOOT_PAGE_OFFSET 0x27000 41 42 #ifdef CONFIG_SDCARD 43 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 44 #define CONFIG_SPL_MMC_SUPPORT 45 #define CONFIG_SPL_MMC_MINIMAL 46 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 47 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 48 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 49 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 50 #ifndef CONFIG_SPL_BUILD 51 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 52 #endif 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 54 #define CONFIG_SPL_MMC_BOOT 55 #endif 56 57 #ifdef CONFIG_SPL_BUILD 58 #define CONFIG_SPL_SKIP_RELOCATE 59 #define CONFIG_SPL_COMMON_INIT_DDR 60 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 61 #define CONFIG_SYS_NO_FLASH 62 #endif 63 64 #endif 65 #endif /* CONFIG_RAMBOOT_PBL */ 66 67 #define CONFIG_DDR_ECC 68 69 #define CONFIG_CMD_REGINFO 70 71 /* High Level Configuration Options */ 72 #define CONFIG_BOOKE 73 #define CONFIG_E500 /* BOOKE e500 family */ 74 #define CONFIG_E500MC /* BOOKE e500mc family */ 75 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 76 #define CONFIG_MP /* support multiple processors */ 77 78 #ifndef CONFIG_SYS_TEXT_BASE 79 #define CONFIG_SYS_TEXT_BASE 0xeff40000 80 #endif 81 82 #ifndef CONFIG_RESET_VECTOR_ADDRESS 83 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 84 #endif 85 86 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 87 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 88 #define CONFIG_FSL_IFC /* Enable IFC Support */ 89 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 90 #define CONFIG_PCI /* Enable PCI/PCIE */ 91 #define CONFIG_PCIE1 /* PCIE controller 1 */ 92 #define CONFIG_PCIE2 /* PCIE controller 2 */ 93 #define CONFIG_PCIE3 /* PCIE controller 3 */ 94 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 95 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 96 97 #define CONFIG_FSL_LAW /* Use common FSL init code */ 98 99 #define CONFIG_ENV_OVERWRITE 100 101 /* 102 * These can be toggled for performance analysis, otherwise use default. 103 */ 104 #define CONFIG_SYS_CACHE_STASHING 105 #define CONFIG_BTB /* toggle branch predition */ 106 #ifdef CONFIG_DDR_ECC 107 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 108 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 109 #endif 110 111 #define CONFIG_ENABLE_36BIT_PHYS 112 113 #define CONFIG_ADDR_MAP 114 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 115 116 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 117 #define CONFIG_SYS_MEMTEST_END 0x00400000 118 #define CONFIG_SYS_ALT_MEMTEST 119 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 120 121 /* 122 * Config the L3 Cache as L3 SRAM 123 */ 124 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 125 #define CONFIG_SYS_L3_SIZE (512 << 10) 126 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 127 #ifdef CONFIG_RAMBOOT_PBL 128 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 129 #endif 130 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 131 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 132 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 133 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 134 135 #define CONFIG_SYS_DCSRBAR 0xf0000000 136 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 137 138 /* 139 * DDR Setup 140 */ 141 #define CONFIG_VERY_BIG_RAM 142 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 143 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 144 145 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 146 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 147 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 148 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 149 150 #define CONFIG_DDR_SPD 151 #define CONFIG_SYS_FSL_DDR3 152 153 /* 154 * IFC Definitions 155 */ 156 #define CONFIG_SYS_FLASH_BASE 0xe0000000 157 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 158 159 #ifdef CONFIG_SPL_BUILD 160 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 161 #else 162 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 163 #endif 164 165 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 166 #define CONFIG_MISC_INIT_R 167 168 #define CONFIG_HWCONFIG 169 170 /* define to use L1 as initial stack */ 171 #define CONFIG_L1_INIT_RAM 172 #define CONFIG_SYS_INIT_RAM_LOCK 173 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 174 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 175 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 176 /* The assembler doesn't like typecast */ 177 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 178 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 179 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 180 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 181 182 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 183 GENERATED_GBL_DATA_SIZE) 184 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 185 186 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 187 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 188 189 /* Serial Port - controlled on board with jumper J8 190 * open - index 2 191 * shorted - index 1 192 */ 193 #define CONFIG_CONS_INDEX 1 194 #define CONFIG_SYS_NS16550_SERIAL 195 #define CONFIG_SYS_NS16550_REG_SIZE 1 196 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 197 198 #define CONFIG_SYS_BAUDRATE_TABLE \ 199 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 200 201 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 202 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 203 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 204 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 205 206 /* I2C */ 207 #define CONFIG_SYS_I2C 208 #define CONFIG_SYS_I2C_FSL 209 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 210 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 211 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 212 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 213 214 /* 215 * General PCI 216 * Memory space is mapped 1-1, but I/O space must start from 0. 217 */ 218 219 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 220 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 221 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 222 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 223 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 224 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 225 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 226 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 227 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 228 229 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 230 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 231 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 232 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 233 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 234 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 235 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 236 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 237 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 238 239 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 240 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 241 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 242 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 243 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 244 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 245 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 246 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 247 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 248 249 /* controller 4, Base address 203000 */ 250 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 251 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 252 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 253 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 254 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 255 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 256 257 #ifdef CONFIG_PCI 258 #define CONFIG_PCI_INDIRECT_BRIDGE 259 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 260 261 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 262 #define CONFIG_DOS_PARTITION 263 #endif /* CONFIG_PCI */ 264 265 /* SATA */ 266 #ifdef CONFIG_FSL_SATA_V2 267 #define CONFIG_LIBATA 268 #define CONFIG_FSL_SATA 269 270 #define CONFIG_SYS_SATA_MAX_DEVICE 2 271 #define CONFIG_SATA1 272 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 273 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 274 #define CONFIG_SATA2 275 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 276 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 277 278 #define CONFIG_LBA48 279 #define CONFIG_CMD_SATA 280 #define CONFIG_DOS_PARTITION 281 #endif 282 283 #ifdef CONFIG_FMAN_ENET 284 #define CONFIG_MII /* MII PHY management */ 285 #define CONFIG_ETHPRIME "FM1@DTSEC1" 286 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 287 #endif 288 289 /* 290 * Environment 291 */ 292 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 293 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 294 295 /* 296 * Command line configuration. 297 */ 298 #define CONFIG_CMD_ERRATA 299 #define CONFIG_CMD_IRQ 300 301 #ifdef CONFIG_PCI 302 #define CONFIG_CMD_PCI 303 #endif 304 305 /* 306 * Miscellaneous configurable options 307 */ 308 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 309 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 310 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 311 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 312 #ifdef CONFIG_CMD_KGDB 313 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 314 #else 315 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 316 #endif 317 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 318 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 319 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 320 321 /* 322 * For booting Linux, the board info and command line data 323 * have to be in the first 64 MB of memory, since this is 324 * the maximum mapped by the Linux kernel during initialization. 325 */ 326 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 327 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 328 329 #ifdef CONFIG_CMD_KGDB 330 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 331 #endif 332 333 /* 334 * Environment Configuration 335 */ 336 #define CONFIG_ROOTPATH "/opt/nfsroot" 337 #define CONFIG_BOOTFILE "uImage" 338 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 339 340 /* default location for tftp and bootm */ 341 #define CONFIG_LOADADDR 1000000 342 343 #define CONFIG_BAUDRATE 115200 344 345 #define CONFIG_HVBOOT \ 346 "setenv bootargs config-addr=0x60000000; " \ 347 "bootm 0x01000000 - 0x00f00000" 348 349 #ifdef CONFIG_SYS_NO_FLASH 350 #ifndef CONFIG_RAMBOOT_PBL 351 #define CONFIG_ENV_IS_NOWHERE 352 #endif 353 #else 354 #define CONFIG_FLASH_CFI_DRIVER 355 #define CONFIG_SYS_FLASH_CFI 356 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 357 #endif 358 359 #if defined(CONFIG_SPIFLASH) 360 #define CONFIG_SYS_EXTRA_ENV_RELOC 361 #define CONFIG_ENV_IS_IN_SPI_FLASH 362 #define CONFIG_ENV_SPI_BUS 0 363 #define CONFIG_ENV_SPI_CS 0 364 #define CONFIG_ENV_SPI_MAX_HZ 10000000 365 #define CONFIG_ENV_SPI_MODE 0 366 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 367 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 368 #define CONFIG_ENV_SECT_SIZE 0x10000 369 #elif defined(CONFIG_SDCARD) 370 #define CONFIG_SYS_EXTRA_ENV_RELOC 371 #define CONFIG_ENV_IS_IN_MMC 372 #define CONFIG_SYS_MMC_ENV_DEV 0 373 #define CONFIG_ENV_SIZE 0x2000 374 #define CONFIG_ENV_OFFSET (512 * 0x800) 375 #elif defined(CONFIG_NAND) 376 #define CONFIG_SYS_EXTRA_ENV_RELOC 377 #define CONFIG_ENV_IS_IN_NAND 378 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 379 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 380 #elif defined(CONFIG_ENV_IS_NOWHERE) 381 #define CONFIG_ENV_SIZE 0x2000 382 #else 383 #define CONFIG_ENV_IS_IN_FLASH 384 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 385 #define CONFIG_ENV_SIZE 0x2000 386 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 387 #endif 388 389 #define CONFIG_SYS_CLK_FREQ 66666666 390 #define CONFIG_DDR_CLK_FREQ 133333333 391 392 #ifndef __ASSEMBLY__ 393 unsigned long get_board_sys_clk(void); 394 unsigned long get_board_ddr_clk(void); 395 #endif 396 397 /* 398 * DDR Setup 399 */ 400 #define CONFIG_SYS_SPD_BUS_NUM 0 401 #define SPD_EEPROM_ADDRESS1 0x52 402 #define SPD_EEPROM_ADDRESS2 0x54 403 #define SPD_EEPROM_ADDRESS3 0x56 404 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 405 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 406 407 /* 408 * IFC Definitions 409 */ 410 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 411 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 412 + 0x8000000) | \ 413 CSPR_PORT_SIZE_16 | \ 414 CSPR_MSEL_NOR | \ 415 CSPR_V) 416 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 417 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 418 CSPR_PORT_SIZE_16 | \ 419 CSPR_MSEL_NOR | \ 420 CSPR_V) 421 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 422 /* NOR Flash Timing Params */ 423 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 424 425 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 426 FTIM0_NOR_TEADC(0x5) | \ 427 FTIM0_NOR_TEAHC(0x5)) 428 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 429 FTIM1_NOR_TRAD_NOR(0x1A) |\ 430 FTIM1_NOR_TSEQRAD_NOR(0x13)) 431 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 432 FTIM2_NOR_TCH(0x4) | \ 433 FTIM2_NOR_TWPH(0x0E) | \ 434 FTIM2_NOR_TWP(0x1c)) 435 #define CONFIG_SYS_NOR_FTIM3 0x0 436 437 #define CONFIG_SYS_FLASH_QUIET_TEST 438 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 439 440 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 441 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 442 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 443 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 444 445 #define CONFIG_SYS_FLASH_EMPTY_INFO 446 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 447 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 448 449 /* NAND Flash on IFC */ 450 #define CONFIG_NAND_FSL_IFC 451 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 452 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 453 #define CONFIG_SYS_NAND_BASE 0xff800000 454 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 455 456 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 457 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 458 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 459 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 460 | CSPR_V) 461 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 462 463 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 464 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 465 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 466 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 467 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 468 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 469 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 470 471 #define CONFIG_SYS_NAND_ONFI_DETECTION 472 473 /* ONFI NAND Flash mode0 Timing Params */ 474 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 475 FTIM0_NAND_TWP(0x18) | \ 476 FTIM0_NAND_TWCHT(0x07) | \ 477 FTIM0_NAND_TWH(0x0a)) 478 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 479 FTIM1_NAND_TWBE(0x39) | \ 480 FTIM1_NAND_TRR(0x0e) | \ 481 FTIM1_NAND_TRP(0x18)) 482 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 483 FTIM2_NAND_TREH(0x0a) | \ 484 FTIM2_NAND_TWHRE(0x1e)) 485 #define CONFIG_SYS_NAND_FTIM3 0x0 486 487 #define CONFIG_SYS_NAND_DDR_LAW 11 488 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 489 #define CONFIG_SYS_MAX_NAND_DEVICE 1 490 #define CONFIG_CMD_NAND 491 492 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 493 494 #if defined(CONFIG_NAND) 495 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 496 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 497 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 498 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 499 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 500 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 501 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 502 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 503 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 504 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 505 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 506 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 507 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 508 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 509 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 510 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 511 #else 512 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 513 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 514 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 515 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 516 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 517 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 518 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 519 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 520 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 521 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 522 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 523 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 524 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 525 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 526 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 527 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 528 #endif 529 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 530 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 531 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 532 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 533 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 534 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 535 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 536 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 537 538 /* CPLD on IFC */ 539 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 540 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 541 #define CONFIG_SYS_CSPR3_EXT (0xf) 542 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 543 | CSPR_PORT_SIZE_8 \ 544 | CSPR_MSEL_GPCM \ 545 | CSPR_V) 546 547 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 548 #define CONFIG_SYS_CSOR3 0x0 549 550 /* CPLD Timing parameters for IFC CS3 */ 551 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 552 FTIM0_GPCM_TEADC(0x0e) | \ 553 FTIM0_GPCM_TEAHC(0x0e)) 554 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 555 FTIM1_GPCM_TRAD(0x1f)) 556 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 557 FTIM2_GPCM_TCH(0x8) | \ 558 FTIM2_GPCM_TWP(0x1f)) 559 #define CONFIG_SYS_CS3_FTIM3 0x0 560 561 #if defined(CONFIG_RAMBOOT_PBL) 562 #define CONFIG_SYS_RAMBOOT 563 #endif 564 565 /* I2C */ 566 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 567 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 568 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 569 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 570 571 #define I2C_MUX_CH_DEFAULT 0x8 572 #define I2C_MUX_CH_VOL_MONITOR 0xa 573 #define I2C_MUX_CH_VSC3316_FS 0xc 574 #define I2C_MUX_CH_VSC3316_BS 0xd 575 576 /* Voltage monitor on channel 2*/ 577 #define I2C_VOL_MONITOR_ADDR 0x40 578 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 579 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 580 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 581 582 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 583 #ifndef CONFIG_SPL_BUILD 584 #define CONFIG_VID 585 #endif 586 #define CONFIG_VOL_MONITOR_IR36021_SET 587 #define CONFIG_VOL_MONITOR_IR36021_READ 588 /* The lowest and highest voltage allowed for T4240RDB */ 589 #define VDD_MV_MIN 819 590 #define VDD_MV_MAX 1212 591 592 /* 593 * eSPI - Enhanced SPI 594 */ 595 #define CONFIG_SF_DEFAULT_SPEED 10000000 596 #define CONFIG_SF_DEFAULT_MODE 0 597 598 /* Qman/Bman */ 599 #ifndef CONFIG_NOBQFMAN 600 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 601 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 602 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 603 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 604 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 605 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 606 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 607 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 608 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 609 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 610 CONFIG_SYS_BMAN_CENA_SIZE) 611 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 612 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 613 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 614 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 615 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 616 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 617 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 618 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 619 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 620 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 621 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 622 CONFIG_SYS_QMAN_CENA_SIZE) 623 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 624 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 625 626 #define CONFIG_SYS_DPAA_FMAN 627 #define CONFIG_SYS_DPAA_PME 628 #define CONFIG_SYS_PMAN 629 #define CONFIG_SYS_DPAA_DCE 630 #define CONFIG_SYS_DPAA_RMAN 631 #define CONFIG_SYS_INTERLAKEN 632 633 /* Default address of microcode for the Linux Fman driver */ 634 #if defined(CONFIG_SPIFLASH) 635 /* 636 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 637 * env, so we got 0x110000. 638 */ 639 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 640 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 641 #elif defined(CONFIG_SDCARD) 642 /* 643 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 644 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 645 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 646 */ 647 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 648 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 649 #elif defined(CONFIG_NAND) 650 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 651 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 652 #else 653 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 654 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 655 #endif 656 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 657 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 658 #endif /* CONFIG_NOBQFMAN */ 659 660 #ifdef CONFIG_SYS_DPAA_FMAN 661 #define CONFIG_FMAN_ENET 662 #define CONFIG_PHYLIB_10G 663 #define CONFIG_PHY_VITESSE 664 #define CONFIG_PHY_CORTINA 665 #define CONFIG_SYS_CORTINA_FW_IN_NOR 666 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 667 #define CONFIG_CORTINA_FW_LENGTH 0x40000 668 #define CONFIG_PHY_TERANETICS 669 #define SGMII_PHY_ADDR1 0x0 670 #define SGMII_PHY_ADDR2 0x1 671 #define SGMII_PHY_ADDR3 0x2 672 #define SGMII_PHY_ADDR4 0x3 673 #define SGMII_PHY_ADDR5 0x4 674 #define SGMII_PHY_ADDR6 0x5 675 #define SGMII_PHY_ADDR7 0x6 676 #define SGMII_PHY_ADDR8 0x7 677 #define FM1_10GEC1_PHY_ADDR 0x10 678 #define FM1_10GEC2_PHY_ADDR 0x11 679 #define FM2_10GEC1_PHY_ADDR 0x12 680 #define FM2_10GEC2_PHY_ADDR 0x13 681 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 682 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 683 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 684 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 685 #endif 686 687 /* SATA */ 688 #ifdef CONFIG_FSL_SATA_V2 689 #define CONFIG_LIBATA 690 #define CONFIG_FSL_SATA 691 692 #define CONFIG_SYS_SATA_MAX_DEVICE 2 693 #define CONFIG_SATA1 694 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 695 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 696 #define CONFIG_SATA2 697 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 698 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 699 700 #define CONFIG_LBA48 701 #define CONFIG_CMD_SATA 702 #define CONFIG_DOS_PARTITION 703 #endif 704 705 #ifdef CONFIG_FMAN_ENET 706 #define CONFIG_MII /* MII PHY management */ 707 #define CONFIG_ETHPRIME "FM1@DTSEC1" 708 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 709 #endif 710 711 /* 712 * USB 713 */ 714 #define CONFIG_USB_EHCI 715 #define CONFIG_USB_EHCI_FSL 716 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 717 #define CONFIG_HAS_FSL_DR_USB 718 719 #define CONFIG_MMC 720 721 #ifdef CONFIG_MMC 722 #define CONFIG_FSL_ESDHC 723 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 724 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 725 #define CONFIG_GENERIC_MMC 726 #define CONFIG_DOS_PARTITION 727 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 728 #endif 729 730 /* Hash command with SHA acceleration supported in hardware */ 731 #ifdef CONFIG_FSL_CAAM 732 #define CONFIG_CMD_HASH 733 #define CONFIG_SHA_HW_ACCEL 734 #endif 735 736 737 #define __USB_PHY_TYPE utmi 738 739 /* 740 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 741 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 742 * interleaving. It can be cacheline, page, bank, superbank. 743 * See doc/README.fsl-ddr for details. 744 */ 745 #ifdef CONFIG_PPC_T4240 746 #define CTRL_INTLV_PREFERED 3way_4KB 747 #else 748 #define CTRL_INTLV_PREFERED cacheline 749 #endif 750 751 #define CONFIG_EXTRA_ENV_SETTINGS \ 752 "hwconfig=fsl_ddr:" \ 753 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 754 "bank_intlv=auto;" \ 755 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 756 "netdev=eth0\0" \ 757 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 758 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 759 "tftpflash=tftpboot $loadaddr $uboot && " \ 760 "protect off $ubootaddr +$filesize && " \ 761 "erase $ubootaddr +$filesize && " \ 762 "cp.b $loadaddr $ubootaddr $filesize && " \ 763 "protect on $ubootaddr +$filesize && " \ 764 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 765 "consoledev=ttyS0\0" \ 766 "ramdiskaddr=2000000\0" \ 767 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 768 "fdtaddr=1e00000\0" \ 769 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 770 "bdev=sda3\0" 771 772 #define CONFIG_HVBOOT \ 773 "setenv bootargs config-addr=0x60000000; " \ 774 "bootm 0x01000000 - 0x00f00000" 775 776 #define CONFIG_LINUX \ 777 "setenv bootargs root=/dev/ram rw " \ 778 "console=$consoledev,$baudrate $othbootargs;" \ 779 "setenv ramdiskaddr 0x02000000;" \ 780 "setenv fdtaddr 0x00c00000;" \ 781 "setenv loadaddr 0x1000000;" \ 782 "bootm $loadaddr $ramdiskaddr $fdtaddr" 783 784 #define CONFIG_HDBOOT \ 785 "setenv bootargs root=/dev/$bdev rw " \ 786 "console=$consoledev,$baudrate $othbootargs;" \ 787 "tftp $loadaddr $bootfile;" \ 788 "tftp $fdtaddr $fdtfile;" \ 789 "bootm $loadaddr - $fdtaddr" 790 791 #define CONFIG_NFSBOOTCOMMAND \ 792 "setenv bootargs root=/dev/nfs rw " \ 793 "nfsroot=$serverip:$rootpath " \ 794 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 795 "console=$consoledev,$baudrate $othbootargs;" \ 796 "tftp $loadaddr $bootfile;" \ 797 "tftp $fdtaddr $fdtfile;" \ 798 "bootm $loadaddr - $fdtaddr" 799 800 #define CONFIG_RAMBOOTCOMMAND \ 801 "setenv bootargs root=/dev/ram rw " \ 802 "console=$consoledev,$baudrate $othbootargs;" \ 803 "tftp $ramdiskaddr $ramdiskfile;" \ 804 "tftp $loadaddr $bootfile;" \ 805 "tftp $fdtaddr $fdtfile;" \ 806 "bootm $loadaddr $ramdiskaddr $fdtaddr" 807 808 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 809 810 #include <asm/fsl_secure_boot.h> 811 812 #endif /* __CONFIG_H */ 813