1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240RDB 14 #define CONFIG_PHYS_64BIT 15 #define CONFIG_DISPLAY_BOARDINFO 16 17 #define CONFIG_FSL_SATA_V2 18 #define CONFIG_PCIE4 19 20 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 21 22 #ifdef CONFIG_RAMBOOT_PBL 23 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 24 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg 25 #ifndef CONFIG_SDCARD 26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 28 #else 29 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 30 #define CONFIG_SPL_ENV_SUPPORT 31 #define CONFIG_SPL_SERIAL_SUPPORT 32 #define CONFIG_SPL_FLUSH_IMAGE 33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 34 #define CONFIG_SPL_LIBGENERIC_SUPPORT 35 #define CONFIG_SPL_LIBCOMMON_SUPPORT 36 #define CONFIG_SPL_I2C_SUPPORT 37 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 38 #define CONFIG_FSL_LAW /* Use common FSL init code */ 39 #define CONFIG_SYS_TEXT_BASE 0x00201000 40 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 41 #define CONFIG_SPL_PAD_TO 0x40000 42 #define CONFIG_SPL_MAX_SIZE 0x28000 43 #define RESET_VECTOR_OFFSET 0x27FFC 44 #define BOOT_PAGE_OFFSET 0x27000 45 46 #ifdef CONFIG_SDCARD 47 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 48 #define CONFIG_SPL_MMC_SUPPORT 49 #define CONFIG_SPL_MMC_MINIMAL 50 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 51 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 52 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 53 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 54 #ifndef CONFIG_SPL_BUILD 55 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 56 #endif 57 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 58 #define CONFIG_SPL_MMC_BOOT 59 #endif 60 61 #ifdef CONFIG_SPL_BUILD 62 #define CONFIG_SPL_SKIP_RELOCATE 63 #define CONFIG_SPL_COMMON_INIT_DDR 64 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 65 #define CONFIG_SYS_NO_FLASH 66 #endif 67 68 #endif 69 #endif /* CONFIG_RAMBOOT_PBL */ 70 71 #define CONFIG_DDR_ECC 72 73 #define CONFIG_CMD_REGINFO 74 75 /* High Level Configuration Options */ 76 #define CONFIG_BOOKE 77 #define CONFIG_E500 /* BOOKE e500 family */ 78 #define CONFIG_E500MC /* BOOKE e500mc family */ 79 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 80 #define CONFIG_MP /* support multiple processors */ 81 82 #ifndef CONFIG_SYS_TEXT_BASE 83 #define CONFIG_SYS_TEXT_BASE 0xeff40000 84 #endif 85 86 #ifndef CONFIG_RESET_VECTOR_ADDRESS 87 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 88 #endif 89 90 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 91 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 92 #define CONFIG_FSL_IFC /* Enable IFC Support */ 93 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 94 #define CONFIG_PCI /* Enable PCI/PCIE */ 95 #define CONFIG_PCIE1 /* PCIE controler 1 */ 96 #define CONFIG_PCIE2 /* PCIE controler 2 */ 97 #define CONFIG_PCIE3 /* PCIE controler 3 */ 98 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 99 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 100 101 #define CONFIG_FSL_LAW /* Use common FSL init code */ 102 103 #define CONFIG_ENV_OVERWRITE 104 105 /* 106 * These can be toggled for performance analysis, otherwise use default. 107 */ 108 #define CONFIG_SYS_CACHE_STASHING 109 #define CONFIG_BTB /* toggle branch predition */ 110 #ifdef CONFIG_DDR_ECC 111 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 112 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 113 #endif 114 115 #define CONFIG_ENABLE_36BIT_PHYS 116 117 #define CONFIG_ADDR_MAP 118 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 119 120 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 121 #define CONFIG_SYS_MEMTEST_END 0x00400000 122 #define CONFIG_SYS_ALT_MEMTEST 123 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 124 125 /* 126 * Config the L3 Cache as L3 SRAM 127 */ 128 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 129 #define CONFIG_SYS_L3_SIZE (512 << 10) 130 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 131 #ifdef CONFIG_RAMBOOT_PBL 132 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 133 #endif 134 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 135 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 136 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 137 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 138 139 #define CONFIG_SYS_DCSRBAR 0xf0000000 140 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 141 142 /* 143 * DDR Setup 144 */ 145 #define CONFIG_VERY_BIG_RAM 146 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 147 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 148 149 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 150 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 151 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 152 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 153 154 #define CONFIG_DDR_SPD 155 #define CONFIG_SYS_FSL_DDR3 156 157 158 /* 159 * IFC Definitions 160 */ 161 #define CONFIG_SYS_FLASH_BASE 0xe0000000 162 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 163 164 165 #ifdef CONFIG_SPL_BUILD 166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 167 #else 168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 169 #endif 170 171 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 172 #define CONFIG_MISC_INIT_R 173 174 #define CONFIG_HWCONFIG 175 176 /* define to use L1 as initial stack */ 177 #define CONFIG_L1_INIT_RAM 178 #define CONFIG_SYS_INIT_RAM_LOCK 179 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 180 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 182 /* The assembler doesn't like typecast */ 183 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 184 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 185 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 186 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 187 188 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 189 GENERATED_GBL_DATA_SIZE) 190 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 191 192 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 193 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 194 195 /* Serial Port - controlled on board with jumper J8 196 * open - index 2 197 * shorted - index 1 198 */ 199 #define CONFIG_CONS_INDEX 1 200 #define CONFIG_SYS_NS16550_SERIAL 201 #define CONFIG_SYS_NS16550_REG_SIZE 1 202 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 203 204 #define CONFIG_SYS_BAUDRATE_TABLE \ 205 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 206 207 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 208 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 209 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 210 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 211 212 /* I2C */ 213 #define CONFIG_SYS_I2C 214 #define CONFIG_SYS_I2C_FSL 215 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 216 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 217 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 218 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 219 220 /* 221 * General PCI 222 * Memory space is mapped 1-1, but I/O space must start from 0. 223 */ 224 225 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 226 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 227 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 228 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 229 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 230 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 231 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 232 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 233 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 234 235 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 236 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 237 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 238 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 239 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 240 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 241 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 242 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 243 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 244 245 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 246 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 247 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 248 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 249 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 250 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 251 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 252 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 253 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 254 255 /* controller 4, Base address 203000 */ 256 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 257 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 258 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 259 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 260 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 261 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 262 263 #ifdef CONFIG_PCI 264 #define CONFIG_PCI_INDIRECT_BRIDGE 265 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 266 267 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 268 #define CONFIG_DOS_PARTITION 269 #endif /* CONFIG_PCI */ 270 271 /* SATA */ 272 #ifdef CONFIG_FSL_SATA_V2 273 #define CONFIG_LIBATA 274 #define CONFIG_FSL_SATA 275 276 #define CONFIG_SYS_SATA_MAX_DEVICE 2 277 #define CONFIG_SATA1 278 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 279 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 280 #define CONFIG_SATA2 281 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 282 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 283 284 #define CONFIG_LBA48 285 #define CONFIG_CMD_SATA 286 #define CONFIG_DOS_PARTITION 287 #define CONFIG_CMD_EXT2 288 #endif 289 290 #ifdef CONFIG_FMAN_ENET 291 #define CONFIG_MII /* MII PHY management */ 292 #define CONFIG_ETHPRIME "FM1@DTSEC1" 293 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 294 #endif 295 296 /* 297 * Environment 298 */ 299 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 300 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 301 302 /* 303 * Command line configuration. 304 */ 305 #define CONFIG_CMD_ERRATA 306 #define CONFIG_CMD_GREPENV 307 #define CONFIG_CMD_IRQ 308 #define CONFIG_CMD_MII 309 310 #ifdef CONFIG_PCI 311 #define CONFIG_CMD_PCI 312 #endif 313 314 /* 315 * Miscellaneous configurable options 316 */ 317 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 318 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 319 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 320 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 321 #ifdef CONFIG_CMD_KGDB 322 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 323 #else 324 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 325 #endif 326 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 327 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 328 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 329 330 /* 331 * For booting Linux, the board info and command line data 332 * have to be in the first 64 MB of memory, since this is 333 * the maximum mapped by the Linux kernel during initialization. 334 */ 335 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 336 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 337 338 #ifdef CONFIG_CMD_KGDB 339 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 340 #endif 341 342 /* 343 * Environment Configuration 344 */ 345 #define CONFIG_ROOTPATH "/opt/nfsroot" 346 #define CONFIG_BOOTFILE "uImage" 347 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 348 349 /* default location for tftp and bootm */ 350 #define CONFIG_LOADADDR 1000000 351 352 353 #define CONFIG_BAUDRATE 115200 354 355 #define CONFIG_HVBOOT \ 356 "setenv bootargs config-addr=0x60000000; " \ 357 "bootm 0x01000000 - 0x00f00000" 358 359 #ifdef CONFIG_SYS_NO_FLASH 360 #ifndef CONFIG_RAMBOOT_PBL 361 #define CONFIG_ENV_IS_NOWHERE 362 #endif 363 #else 364 #define CONFIG_FLASH_CFI_DRIVER 365 #define CONFIG_SYS_FLASH_CFI 366 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 367 #endif 368 369 #if defined(CONFIG_SPIFLASH) 370 #define CONFIG_SYS_EXTRA_ENV_RELOC 371 #define CONFIG_ENV_IS_IN_SPI_FLASH 372 #define CONFIG_ENV_SPI_BUS 0 373 #define CONFIG_ENV_SPI_CS 0 374 #define CONFIG_ENV_SPI_MAX_HZ 10000000 375 #define CONFIG_ENV_SPI_MODE 0 376 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 377 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 378 #define CONFIG_ENV_SECT_SIZE 0x10000 379 #elif defined(CONFIG_SDCARD) 380 #define CONFIG_SYS_EXTRA_ENV_RELOC 381 #define CONFIG_ENV_IS_IN_MMC 382 #define CONFIG_SYS_MMC_ENV_DEV 0 383 #define CONFIG_ENV_SIZE 0x2000 384 #define CONFIG_ENV_OFFSET (512 * 0x800) 385 #elif defined(CONFIG_NAND) 386 #define CONFIG_SYS_EXTRA_ENV_RELOC 387 #define CONFIG_ENV_IS_IN_NAND 388 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 389 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 390 #elif defined(CONFIG_ENV_IS_NOWHERE) 391 #define CONFIG_ENV_SIZE 0x2000 392 #else 393 #define CONFIG_ENV_IS_IN_FLASH 394 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 395 #define CONFIG_ENV_SIZE 0x2000 396 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 397 #endif 398 399 #define CONFIG_SYS_CLK_FREQ 66666666 400 #define CONFIG_DDR_CLK_FREQ 133333333 401 402 #ifndef __ASSEMBLY__ 403 unsigned long get_board_sys_clk(void); 404 unsigned long get_board_ddr_clk(void); 405 #endif 406 407 /* 408 * DDR Setup 409 */ 410 #define CONFIG_SYS_SPD_BUS_NUM 0 411 #define SPD_EEPROM_ADDRESS1 0x52 412 #define SPD_EEPROM_ADDRESS2 0x54 413 #define SPD_EEPROM_ADDRESS3 0x56 414 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 415 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 416 417 /* 418 * IFC Definitions 419 */ 420 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 421 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 422 + 0x8000000) | \ 423 CSPR_PORT_SIZE_16 | \ 424 CSPR_MSEL_NOR | \ 425 CSPR_V) 426 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 427 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 428 CSPR_PORT_SIZE_16 | \ 429 CSPR_MSEL_NOR | \ 430 CSPR_V) 431 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 432 /* NOR Flash Timing Params */ 433 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 434 435 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 436 FTIM0_NOR_TEADC(0x5) | \ 437 FTIM0_NOR_TEAHC(0x5)) 438 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 439 FTIM1_NOR_TRAD_NOR(0x1A) |\ 440 FTIM1_NOR_TSEQRAD_NOR(0x13)) 441 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 442 FTIM2_NOR_TCH(0x4) | \ 443 FTIM2_NOR_TWPH(0x0E) | \ 444 FTIM2_NOR_TWP(0x1c)) 445 #define CONFIG_SYS_NOR_FTIM3 0x0 446 447 #define CONFIG_SYS_FLASH_QUIET_TEST 448 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 449 450 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 451 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 452 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 453 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 454 455 #define CONFIG_SYS_FLASH_EMPTY_INFO 456 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 457 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 458 459 /* NAND Flash on IFC */ 460 #define CONFIG_NAND_FSL_IFC 461 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 462 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 463 #define CONFIG_SYS_NAND_BASE 0xff800000 464 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 465 466 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 467 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 468 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 469 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 470 | CSPR_V) 471 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 472 473 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 474 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 475 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 476 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 477 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 478 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 479 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 480 481 #define CONFIG_SYS_NAND_ONFI_DETECTION 482 483 /* ONFI NAND Flash mode0 Timing Params */ 484 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 485 FTIM0_NAND_TWP(0x18) | \ 486 FTIM0_NAND_TWCHT(0x07) | \ 487 FTIM0_NAND_TWH(0x0a)) 488 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 489 FTIM1_NAND_TWBE(0x39) | \ 490 FTIM1_NAND_TRR(0x0e) | \ 491 FTIM1_NAND_TRP(0x18)) 492 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 493 FTIM2_NAND_TREH(0x0a) | \ 494 FTIM2_NAND_TWHRE(0x1e)) 495 #define CONFIG_SYS_NAND_FTIM3 0x0 496 497 #define CONFIG_SYS_NAND_DDR_LAW 11 498 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 499 #define CONFIG_SYS_MAX_NAND_DEVICE 1 500 #define CONFIG_CMD_NAND 501 502 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 503 504 #if defined(CONFIG_NAND) 505 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 506 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 507 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 508 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 509 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 510 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 511 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 512 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 513 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 514 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 515 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 516 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 517 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 518 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 519 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 520 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 521 #else 522 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 523 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 524 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 525 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 526 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 527 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 528 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 529 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 530 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 531 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 532 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 533 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 534 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 535 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 536 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 537 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 538 #endif 539 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 540 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 541 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 542 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 543 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 544 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 545 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 546 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 547 548 /* CPLD on IFC */ 549 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 550 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 551 #define CONFIG_SYS_CSPR3_EXT (0xf) 552 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 553 | CSPR_PORT_SIZE_8 \ 554 | CSPR_MSEL_GPCM \ 555 | CSPR_V) 556 557 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 558 #define CONFIG_SYS_CSOR3 0x0 559 560 /* CPLD Timing parameters for IFC CS3 */ 561 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 562 FTIM0_GPCM_TEADC(0x0e) | \ 563 FTIM0_GPCM_TEAHC(0x0e)) 564 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 565 FTIM1_GPCM_TRAD(0x1f)) 566 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 567 FTIM2_GPCM_TCH(0x8) | \ 568 FTIM2_GPCM_TWP(0x1f)) 569 #define CONFIG_SYS_CS3_FTIM3 0x0 570 571 #if defined(CONFIG_RAMBOOT_PBL) 572 #define CONFIG_SYS_RAMBOOT 573 #endif 574 575 576 /* I2C */ 577 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 578 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 579 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 580 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 581 582 #define I2C_MUX_CH_DEFAULT 0x8 583 #define I2C_MUX_CH_VOL_MONITOR 0xa 584 #define I2C_MUX_CH_VSC3316_FS 0xc 585 #define I2C_MUX_CH_VSC3316_BS 0xd 586 587 /* Voltage monitor on channel 2*/ 588 #define I2C_VOL_MONITOR_ADDR 0x40 589 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 590 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 591 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 592 593 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 594 #ifndef CONFIG_SPL_BUILD 595 #define CONFIG_VID 596 #endif 597 #define CONFIG_VOL_MONITOR_IR36021_SET 598 #define CONFIG_VOL_MONITOR_IR36021_READ 599 /* The lowest and highest voltage allowed for T4240RDB */ 600 #define VDD_MV_MIN 819 601 #define VDD_MV_MAX 1212 602 603 /* 604 * eSPI - Enhanced SPI 605 */ 606 #define CONFIG_SF_DEFAULT_SPEED 10000000 607 #define CONFIG_SF_DEFAULT_MODE 0 608 609 610 /* Qman/Bman */ 611 #ifndef CONFIG_NOBQFMAN 612 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 613 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 614 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 615 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 616 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 617 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 618 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 619 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 620 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 621 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 622 CONFIG_SYS_BMAN_CENA_SIZE) 623 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 624 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 625 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 626 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 627 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 628 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 629 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 630 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 631 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 632 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 633 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 634 CONFIG_SYS_QMAN_CENA_SIZE) 635 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 636 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 637 638 #define CONFIG_SYS_DPAA_FMAN 639 #define CONFIG_SYS_DPAA_PME 640 #define CONFIG_SYS_PMAN 641 #define CONFIG_SYS_DPAA_DCE 642 #define CONFIG_SYS_DPAA_RMAN 643 #define CONFIG_SYS_INTERLAKEN 644 645 /* Default address of microcode for the Linux Fman driver */ 646 #if defined(CONFIG_SPIFLASH) 647 /* 648 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 649 * env, so we got 0x110000. 650 */ 651 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 652 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 653 #elif defined(CONFIG_SDCARD) 654 /* 655 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 656 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 657 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 658 */ 659 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 660 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 661 #elif defined(CONFIG_NAND) 662 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 663 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 664 #else 665 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 666 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 667 #endif 668 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 669 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 670 #endif /* CONFIG_NOBQFMAN */ 671 672 #ifdef CONFIG_SYS_DPAA_FMAN 673 #define CONFIG_FMAN_ENET 674 #define CONFIG_PHYLIB_10G 675 #define CONFIG_PHY_VITESSE 676 #define CONFIG_PHY_CORTINA 677 #define CONFIG_SYS_CORTINA_FW_IN_NOR 678 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 679 #define CONFIG_CORTINA_FW_LENGTH 0x40000 680 #define CONFIG_PHY_TERANETICS 681 #define SGMII_PHY_ADDR1 0x0 682 #define SGMII_PHY_ADDR2 0x1 683 #define SGMII_PHY_ADDR3 0x2 684 #define SGMII_PHY_ADDR4 0x3 685 #define SGMII_PHY_ADDR5 0x4 686 #define SGMII_PHY_ADDR6 0x5 687 #define SGMII_PHY_ADDR7 0x6 688 #define SGMII_PHY_ADDR8 0x7 689 #define FM1_10GEC1_PHY_ADDR 0x10 690 #define FM1_10GEC2_PHY_ADDR 0x11 691 #define FM2_10GEC1_PHY_ADDR 0x12 692 #define FM2_10GEC2_PHY_ADDR 0x13 693 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 694 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 695 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 696 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 697 #endif 698 699 700 /* SATA */ 701 #ifdef CONFIG_FSL_SATA_V2 702 #define CONFIG_LIBATA 703 #define CONFIG_FSL_SATA 704 705 #define CONFIG_SYS_SATA_MAX_DEVICE 2 706 #define CONFIG_SATA1 707 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 708 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 709 #define CONFIG_SATA2 710 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 711 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 712 713 #define CONFIG_LBA48 714 #define CONFIG_CMD_SATA 715 #define CONFIG_DOS_PARTITION 716 #define CONFIG_CMD_EXT2 717 #endif 718 719 #ifdef CONFIG_FMAN_ENET 720 #define CONFIG_MII /* MII PHY management */ 721 #define CONFIG_ETHPRIME "FM1@DTSEC1" 722 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 723 #endif 724 725 /* 726 * USB 727 */ 728 #define CONFIG_USB_STORAGE 729 #define CONFIG_USB_EHCI 730 #define CONFIG_USB_EHCI_FSL 731 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 732 #define CONFIG_CMD_EXT2 733 #define CONFIG_HAS_FSL_DR_USB 734 735 #define CONFIG_MMC 736 737 #ifdef CONFIG_MMC 738 #define CONFIG_FSL_ESDHC 739 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 740 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 741 #define CONFIG_CMD_MMC 742 #define CONFIG_GENERIC_MMC 743 #define CONFIG_CMD_EXT2 744 #define CONFIG_CMD_FAT 745 #define CONFIG_DOS_PARTITION 746 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 747 #endif 748 749 /* Hash command with SHA acceleration supported in hardware */ 750 #ifdef CONFIG_FSL_CAAM 751 #define CONFIG_CMD_HASH 752 #define CONFIG_SHA_HW_ACCEL 753 #endif 754 755 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 756 757 #define __USB_PHY_TYPE utmi 758 759 /* 760 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 761 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 762 * interleaving. It can be cacheline, page, bank, superbank. 763 * See doc/README.fsl-ddr for details. 764 */ 765 #ifdef CONFIG_PPC_T4240 766 #define CTRL_INTLV_PREFERED 3way_4KB 767 #else 768 #define CTRL_INTLV_PREFERED cacheline 769 #endif 770 771 #define CONFIG_EXTRA_ENV_SETTINGS \ 772 "hwconfig=fsl_ddr:" \ 773 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 774 "bank_intlv=auto;" \ 775 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 776 "netdev=eth0\0" \ 777 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 778 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 779 "tftpflash=tftpboot $loadaddr $uboot && " \ 780 "protect off $ubootaddr +$filesize && " \ 781 "erase $ubootaddr +$filesize && " \ 782 "cp.b $loadaddr $ubootaddr $filesize && " \ 783 "protect on $ubootaddr +$filesize && " \ 784 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 785 "consoledev=ttyS0\0" \ 786 "ramdiskaddr=2000000\0" \ 787 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 788 "fdtaddr=c00000\0" \ 789 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 790 "bdev=sda3\0" 791 792 #define CONFIG_HVBOOT \ 793 "setenv bootargs config-addr=0x60000000; " \ 794 "bootm 0x01000000 - 0x00f00000" 795 796 #define CONFIG_LINUX \ 797 "setenv bootargs root=/dev/ram rw " \ 798 "console=$consoledev,$baudrate $othbootargs;" \ 799 "setenv ramdiskaddr 0x02000000;" \ 800 "setenv fdtaddr 0x00c00000;" \ 801 "setenv loadaddr 0x1000000;" \ 802 "bootm $loadaddr $ramdiskaddr $fdtaddr" 803 804 #define CONFIG_HDBOOT \ 805 "setenv bootargs root=/dev/$bdev rw " \ 806 "console=$consoledev,$baudrate $othbootargs;" \ 807 "tftp $loadaddr $bootfile;" \ 808 "tftp $fdtaddr $fdtfile;" \ 809 "bootm $loadaddr - $fdtaddr" 810 811 #define CONFIG_NFSBOOTCOMMAND \ 812 "setenv bootargs root=/dev/nfs rw " \ 813 "nfsroot=$serverip:$rootpath " \ 814 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 815 "console=$consoledev,$baudrate $othbootargs;" \ 816 "tftp $loadaddr $bootfile;" \ 817 "tftp $fdtaddr $fdtfile;" \ 818 "bootm $loadaddr - $fdtaddr" 819 820 #define CONFIG_RAMBOOTCOMMAND \ 821 "setenv bootargs root=/dev/ram rw " \ 822 "console=$consoledev,$baudrate $othbootargs;" \ 823 "tftp $ramdiskaddr $ramdiskfile;" \ 824 "tftp $loadaddr $bootfile;" \ 825 "tftp $fdtaddr $fdtfile;" \ 826 "bootm $loadaddr $ramdiskaddr $fdtaddr" 827 828 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 829 830 #include <asm/fsl_secure_boot.h> 831 832 #endif /* __CONFIG_H */ 833