1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240RDB 14 #define CONFIG_PHYS_64BIT 15 #define CONFIG_DISPLAY_BOARDINFO 16 17 #define CONFIG_FSL_SATA_V2 18 #define CONFIG_PCIE4 19 20 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 21 22 #ifdef CONFIG_RAMBOOT_PBL 23 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 24 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg 25 #ifndef CONFIG_SDCARD 26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 28 #else 29 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 30 #define CONFIG_SPL_ENV_SUPPORT 31 #define CONFIG_SPL_SERIAL_SUPPORT 32 #define CONFIG_SPL_FLUSH_IMAGE 33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 34 #define CONFIG_SPL_LIBGENERIC_SUPPORT 35 #define CONFIG_SPL_LIBCOMMON_SUPPORT 36 #define CONFIG_SPL_I2C_SUPPORT 37 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 38 #define CONFIG_FSL_LAW /* Use common FSL init code */ 39 #define CONFIG_SYS_TEXT_BASE 0x00201000 40 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 41 #define CONFIG_SPL_PAD_TO 0x40000 42 #define CONFIG_SPL_MAX_SIZE 0x28000 43 #define RESET_VECTOR_OFFSET 0x27FFC 44 #define BOOT_PAGE_OFFSET 0x27000 45 46 #ifdef CONFIG_SDCARD 47 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 48 #define CONFIG_SPL_MMC_SUPPORT 49 #define CONFIG_SPL_MMC_MINIMAL 50 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 51 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 52 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 53 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 54 #ifndef CONFIG_SPL_BUILD 55 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 56 #endif 57 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 58 #define CONFIG_SPL_MMC_BOOT 59 #endif 60 61 #ifdef CONFIG_SPL_BUILD 62 #define CONFIG_SPL_SKIP_RELOCATE 63 #define CONFIG_SPL_COMMON_INIT_DDR 64 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 65 #define CONFIG_SYS_NO_FLASH 66 #endif 67 68 #endif 69 #endif /* CONFIG_RAMBOOT_PBL */ 70 71 #define CONFIG_DDR_ECC 72 73 #define CONFIG_CMD_REGINFO 74 75 /* High Level Configuration Options */ 76 #define CONFIG_BOOKE 77 #define CONFIG_E500 /* BOOKE e500 family */ 78 #define CONFIG_E500MC /* BOOKE e500mc family */ 79 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 80 #define CONFIG_MP /* support multiple processors */ 81 82 #ifndef CONFIG_SYS_TEXT_BASE 83 #define CONFIG_SYS_TEXT_BASE 0xeff40000 84 #endif 85 86 #ifndef CONFIG_RESET_VECTOR_ADDRESS 87 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 88 #endif 89 90 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 91 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 92 #define CONFIG_FSL_IFC /* Enable IFC Support */ 93 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 94 #define CONFIG_PCI /* Enable PCI/PCIE */ 95 #define CONFIG_PCIE1 /* PCIE controler 1 */ 96 #define CONFIG_PCIE2 /* PCIE controler 2 */ 97 #define CONFIG_PCIE3 /* PCIE controler 3 */ 98 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 99 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 100 101 #define CONFIG_FSL_LAW /* Use common FSL init code */ 102 103 #define CONFIG_ENV_OVERWRITE 104 105 /* 106 * These can be toggled for performance analysis, otherwise use default. 107 */ 108 #define CONFIG_SYS_CACHE_STASHING 109 #define CONFIG_BTB /* toggle branch predition */ 110 #ifdef CONFIG_DDR_ECC 111 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 112 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 113 #endif 114 115 #define CONFIG_ENABLE_36BIT_PHYS 116 117 #define CONFIG_ADDR_MAP 118 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 119 120 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 121 #define CONFIG_SYS_MEMTEST_END 0x00400000 122 #define CONFIG_SYS_ALT_MEMTEST 123 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 124 125 /* 126 * Config the L3 Cache as L3 SRAM 127 */ 128 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 129 #define CONFIG_SYS_L3_SIZE (512 << 10) 130 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 131 #ifdef CONFIG_RAMBOOT_PBL 132 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 133 #endif 134 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 135 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 136 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 137 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 138 139 #define CONFIG_SYS_DCSRBAR 0xf0000000 140 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 141 142 /* 143 * DDR Setup 144 */ 145 #define CONFIG_VERY_BIG_RAM 146 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 147 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 148 149 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 150 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 151 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 152 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 153 154 #define CONFIG_DDR_SPD 155 #define CONFIG_SYS_FSL_DDR3 156 157 158 /* 159 * IFC Definitions 160 */ 161 #define CONFIG_SYS_FLASH_BASE 0xe0000000 162 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 163 164 165 #ifdef CONFIG_SPL_BUILD 166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 167 #else 168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 169 #endif 170 171 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 172 #define CONFIG_MISC_INIT_R 173 174 #define CONFIG_HWCONFIG 175 176 /* define to use L1 as initial stack */ 177 #define CONFIG_L1_INIT_RAM 178 #define CONFIG_SYS_INIT_RAM_LOCK 179 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 180 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 182 /* The assembler doesn't like typecast */ 183 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 184 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 185 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 186 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 187 188 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 189 GENERATED_GBL_DATA_SIZE) 190 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 191 192 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 193 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 194 195 /* Serial Port - controlled on board with jumper J8 196 * open - index 2 197 * shorted - index 1 198 */ 199 #define CONFIG_CONS_INDEX 1 200 #define CONFIG_SYS_NS16550_SERIAL 201 #define CONFIG_SYS_NS16550_REG_SIZE 1 202 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 203 204 #define CONFIG_SYS_BAUDRATE_TABLE \ 205 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 206 207 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 208 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 209 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 210 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 211 212 /* Use the HUSH parser */ 213 #define CONFIG_SYS_HUSH_PARSER 214 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 215 216 /* pass open firmware flat tree */ 217 #define CONFIG_OF_BOARD_SETUP 218 #define CONFIG_OF_STDOUT_VIA_ALIAS 219 220 /* new uImage format support */ 221 #define CONFIG_FIT 222 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 223 224 /* I2C */ 225 #define CONFIG_SYS_I2C 226 #define CONFIG_SYS_I2C_FSL 227 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 228 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 229 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 230 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 231 232 /* 233 * General PCI 234 * Memory space is mapped 1-1, but I/O space must start from 0. 235 */ 236 237 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 238 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 239 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 240 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 241 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 242 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 243 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 244 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 245 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 246 247 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 248 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 249 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 250 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 251 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 252 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 253 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 254 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 255 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 256 257 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 258 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 259 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 260 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 261 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 262 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 263 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 264 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 265 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 266 267 /* controller 4, Base address 203000 */ 268 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 269 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 270 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 271 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 272 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 273 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 274 275 #ifdef CONFIG_PCI 276 #define CONFIG_PCI_INDIRECT_BRIDGE 277 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 278 279 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 280 #define CONFIG_DOS_PARTITION 281 #endif /* CONFIG_PCI */ 282 283 /* SATA */ 284 #ifdef CONFIG_FSL_SATA_V2 285 #define CONFIG_LIBATA 286 #define CONFIG_FSL_SATA 287 288 #define CONFIG_SYS_SATA_MAX_DEVICE 2 289 #define CONFIG_SATA1 290 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 291 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 292 #define CONFIG_SATA2 293 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 294 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 295 296 #define CONFIG_LBA48 297 #define CONFIG_CMD_SATA 298 #define CONFIG_DOS_PARTITION 299 #define CONFIG_CMD_EXT2 300 #endif 301 302 #ifdef CONFIG_FMAN_ENET 303 #define CONFIG_MII /* MII PHY management */ 304 #define CONFIG_ETHPRIME "FM1@DTSEC1" 305 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 306 #endif 307 308 /* 309 * Environment 310 */ 311 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 312 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 313 314 /* 315 * Command line configuration. 316 */ 317 #define CONFIG_CMD_DHCP 318 #define CONFIG_CMD_ERRATA 319 #define CONFIG_CMD_GREPENV 320 #define CONFIG_CMD_IRQ 321 #define CONFIG_CMD_I2C 322 #define CONFIG_CMD_MII 323 #define CONFIG_CMD_PING 324 325 #ifdef CONFIG_PCI 326 #define CONFIG_CMD_PCI 327 #endif 328 329 /* 330 * Miscellaneous configurable options 331 */ 332 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 333 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 334 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 335 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 336 #ifdef CONFIG_CMD_KGDB 337 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 338 #else 339 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 340 #endif 341 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 342 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 343 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 344 345 /* 346 * For booting Linux, the board info and command line data 347 * have to be in the first 64 MB of memory, since this is 348 * the maximum mapped by the Linux kernel during initialization. 349 */ 350 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 351 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 352 353 #ifdef CONFIG_CMD_KGDB 354 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 355 #endif 356 357 /* 358 * Environment Configuration 359 */ 360 #define CONFIG_ROOTPATH "/opt/nfsroot" 361 #define CONFIG_BOOTFILE "uImage" 362 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 363 364 /* default location for tftp and bootm */ 365 #define CONFIG_LOADADDR 1000000 366 367 368 #define CONFIG_BAUDRATE 115200 369 370 #define CONFIG_HVBOOT \ 371 "setenv bootargs config-addr=0x60000000; " \ 372 "bootm 0x01000000 - 0x00f00000" 373 374 #ifdef CONFIG_SYS_NO_FLASH 375 #ifndef CONFIG_RAMBOOT_PBL 376 #define CONFIG_ENV_IS_NOWHERE 377 #endif 378 #else 379 #define CONFIG_FLASH_CFI_DRIVER 380 #define CONFIG_SYS_FLASH_CFI 381 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 382 #endif 383 384 #if defined(CONFIG_SPIFLASH) 385 #define CONFIG_SYS_EXTRA_ENV_RELOC 386 #define CONFIG_ENV_IS_IN_SPI_FLASH 387 #define CONFIG_ENV_SPI_BUS 0 388 #define CONFIG_ENV_SPI_CS 0 389 #define CONFIG_ENV_SPI_MAX_HZ 10000000 390 #define CONFIG_ENV_SPI_MODE 0 391 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 392 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 393 #define CONFIG_ENV_SECT_SIZE 0x10000 394 #elif defined(CONFIG_SDCARD) 395 #define CONFIG_SYS_EXTRA_ENV_RELOC 396 #define CONFIG_ENV_IS_IN_MMC 397 #define CONFIG_SYS_MMC_ENV_DEV 0 398 #define CONFIG_ENV_SIZE 0x2000 399 #define CONFIG_ENV_OFFSET (512 * 0x800) 400 #elif defined(CONFIG_NAND) 401 #define CONFIG_SYS_EXTRA_ENV_RELOC 402 #define CONFIG_ENV_IS_IN_NAND 403 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 404 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 405 #elif defined(CONFIG_ENV_IS_NOWHERE) 406 #define CONFIG_ENV_SIZE 0x2000 407 #else 408 #define CONFIG_ENV_IS_IN_FLASH 409 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 410 #define CONFIG_ENV_SIZE 0x2000 411 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 412 #endif 413 414 #define CONFIG_SYS_CLK_FREQ 66666666 415 #define CONFIG_DDR_CLK_FREQ 133333333 416 417 #ifndef __ASSEMBLY__ 418 unsigned long get_board_sys_clk(void); 419 unsigned long get_board_ddr_clk(void); 420 #endif 421 422 /* 423 * DDR Setup 424 */ 425 #define CONFIG_SYS_SPD_BUS_NUM 0 426 #define SPD_EEPROM_ADDRESS1 0x52 427 #define SPD_EEPROM_ADDRESS2 0x54 428 #define SPD_EEPROM_ADDRESS3 0x56 429 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 430 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 431 432 /* 433 * IFC Definitions 434 */ 435 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 436 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 437 + 0x8000000) | \ 438 CSPR_PORT_SIZE_16 | \ 439 CSPR_MSEL_NOR | \ 440 CSPR_V) 441 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 442 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 443 CSPR_PORT_SIZE_16 | \ 444 CSPR_MSEL_NOR | \ 445 CSPR_V) 446 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 447 /* NOR Flash Timing Params */ 448 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 449 450 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 451 FTIM0_NOR_TEADC(0x5) | \ 452 FTIM0_NOR_TEAHC(0x5)) 453 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 454 FTIM1_NOR_TRAD_NOR(0x1A) |\ 455 FTIM1_NOR_TSEQRAD_NOR(0x13)) 456 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 457 FTIM2_NOR_TCH(0x4) | \ 458 FTIM2_NOR_TWPH(0x0E) | \ 459 FTIM2_NOR_TWP(0x1c)) 460 #define CONFIG_SYS_NOR_FTIM3 0x0 461 462 #define CONFIG_SYS_FLASH_QUIET_TEST 463 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 464 465 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 466 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 467 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 468 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 469 470 #define CONFIG_SYS_FLASH_EMPTY_INFO 471 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 472 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 473 474 /* NAND Flash on IFC */ 475 #define CONFIG_NAND_FSL_IFC 476 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 477 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 478 #define CONFIG_SYS_NAND_BASE 0xff800000 479 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 480 481 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 482 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 483 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 484 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 485 | CSPR_V) 486 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 487 488 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 489 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 490 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 491 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 492 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 493 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 494 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 495 496 #define CONFIG_SYS_NAND_ONFI_DETECTION 497 498 /* ONFI NAND Flash mode0 Timing Params */ 499 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 500 FTIM0_NAND_TWP(0x18) | \ 501 FTIM0_NAND_TWCHT(0x07) | \ 502 FTIM0_NAND_TWH(0x0a)) 503 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 504 FTIM1_NAND_TWBE(0x39) | \ 505 FTIM1_NAND_TRR(0x0e) | \ 506 FTIM1_NAND_TRP(0x18)) 507 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 508 FTIM2_NAND_TREH(0x0a) | \ 509 FTIM2_NAND_TWHRE(0x1e)) 510 #define CONFIG_SYS_NAND_FTIM3 0x0 511 512 #define CONFIG_SYS_NAND_DDR_LAW 11 513 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 514 #define CONFIG_SYS_MAX_NAND_DEVICE 1 515 #define CONFIG_CMD_NAND 516 517 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 518 519 #if defined(CONFIG_NAND) 520 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 521 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 522 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 523 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 524 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 525 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 526 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 527 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 528 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 529 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 530 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 531 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 532 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 533 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 534 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 535 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 536 #else 537 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 538 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 539 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 540 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 541 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 542 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 543 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 544 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 545 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 546 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 547 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 548 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 549 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 550 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 551 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 552 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 553 #endif 554 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 555 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 556 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 557 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 558 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 559 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 560 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 561 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 562 563 /* CPLD on IFC */ 564 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 565 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 566 #define CONFIG_SYS_CSPR3_EXT (0xf) 567 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 568 | CSPR_PORT_SIZE_8 \ 569 | CSPR_MSEL_GPCM \ 570 | CSPR_V) 571 572 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 573 #define CONFIG_SYS_CSOR3 0x0 574 575 /* CPLD Timing parameters for IFC CS3 */ 576 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 577 FTIM0_GPCM_TEADC(0x0e) | \ 578 FTIM0_GPCM_TEAHC(0x0e)) 579 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 580 FTIM1_GPCM_TRAD(0x1f)) 581 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 582 FTIM2_GPCM_TCH(0x8) | \ 583 FTIM2_GPCM_TWP(0x1f)) 584 #define CONFIG_SYS_CS3_FTIM3 0x0 585 586 #if defined(CONFIG_RAMBOOT_PBL) 587 #define CONFIG_SYS_RAMBOOT 588 #endif 589 590 591 /* I2C */ 592 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 593 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 594 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 595 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 596 597 #define I2C_MUX_CH_DEFAULT 0x8 598 #define I2C_MUX_CH_VOL_MONITOR 0xa 599 #define I2C_MUX_CH_VSC3316_FS 0xc 600 #define I2C_MUX_CH_VSC3316_BS 0xd 601 602 /* Voltage monitor on channel 2*/ 603 #define I2C_VOL_MONITOR_ADDR 0x40 604 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 605 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 606 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 607 608 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 609 #ifndef CONFIG_SPL_BUILD 610 #define CONFIG_VID 611 #endif 612 #define CONFIG_VOL_MONITOR_IR36021_SET 613 #define CONFIG_VOL_MONITOR_IR36021_READ 614 /* The lowest and highest voltage allowed for T4240RDB */ 615 #define VDD_MV_MIN 819 616 #define VDD_MV_MAX 1212 617 618 /* 619 * eSPI - Enhanced SPI 620 */ 621 #define CONFIG_CMD_SF 622 #define CONFIG_SF_DEFAULT_SPEED 10000000 623 #define CONFIG_SF_DEFAULT_MODE 0 624 625 626 /* Qman/Bman */ 627 #ifndef CONFIG_NOBQFMAN 628 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 629 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 630 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 631 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 632 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 633 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 634 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 635 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 636 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 637 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 638 CONFIG_SYS_BMAN_CENA_SIZE) 639 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 640 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 641 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 642 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 643 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 644 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 645 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 646 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 647 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 648 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 649 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 650 CONFIG_SYS_QMAN_CENA_SIZE) 651 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 652 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 653 654 #define CONFIG_SYS_DPAA_FMAN 655 #define CONFIG_SYS_DPAA_PME 656 #define CONFIG_SYS_PMAN 657 #define CONFIG_SYS_DPAA_DCE 658 #define CONFIG_SYS_DPAA_RMAN 659 #define CONFIG_SYS_INTERLAKEN 660 661 /* Default address of microcode for the Linux Fman driver */ 662 #if defined(CONFIG_SPIFLASH) 663 /* 664 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 665 * env, so we got 0x110000. 666 */ 667 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 668 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 669 #elif defined(CONFIG_SDCARD) 670 /* 671 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 672 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 673 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 674 */ 675 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 676 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 677 #elif defined(CONFIG_NAND) 678 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 679 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 680 #else 681 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 682 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 683 #endif 684 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 685 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 686 #endif /* CONFIG_NOBQFMAN */ 687 688 #ifdef CONFIG_SYS_DPAA_FMAN 689 #define CONFIG_FMAN_ENET 690 #define CONFIG_PHYLIB_10G 691 #define CONFIG_PHY_VITESSE 692 #define CONFIG_PHY_CORTINA 693 #define CONFIG_SYS_CORTINA_FW_IN_NOR 694 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 695 #define CONFIG_CORTINA_FW_LENGTH 0x40000 696 #define CONFIG_PHY_TERANETICS 697 #define SGMII_PHY_ADDR1 0x0 698 #define SGMII_PHY_ADDR2 0x1 699 #define SGMII_PHY_ADDR3 0x2 700 #define SGMII_PHY_ADDR4 0x3 701 #define SGMII_PHY_ADDR5 0x4 702 #define SGMII_PHY_ADDR6 0x5 703 #define SGMII_PHY_ADDR7 0x6 704 #define SGMII_PHY_ADDR8 0x7 705 #define FM1_10GEC1_PHY_ADDR 0x10 706 #define FM1_10GEC2_PHY_ADDR 0x11 707 #define FM2_10GEC1_PHY_ADDR 0x12 708 #define FM2_10GEC2_PHY_ADDR 0x13 709 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 710 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 711 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 712 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 713 #endif 714 715 716 /* SATA */ 717 #ifdef CONFIG_FSL_SATA_V2 718 #define CONFIG_LIBATA 719 #define CONFIG_FSL_SATA 720 721 #define CONFIG_SYS_SATA_MAX_DEVICE 2 722 #define CONFIG_SATA1 723 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 724 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 725 #define CONFIG_SATA2 726 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 727 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 728 729 #define CONFIG_LBA48 730 #define CONFIG_CMD_SATA 731 #define CONFIG_DOS_PARTITION 732 #define CONFIG_CMD_EXT2 733 #endif 734 735 #ifdef CONFIG_FMAN_ENET 736 #define CONFIG_MII /* MII PHY management */ 737 #define CONFIG_ETHPRIME "FM1@DTSEC1" 738 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 739 #endif 740 741 /* 742 * USB 743 */ 744 #define CONFIG_CMD_USB 745 #define CONFIG_USB_STORAGE 746 #define CONFIG_USB_EHCI 747 #define CONFIG_USB_EHCI_FSL 748 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 749 #define CONFIG_CMD_EXT2 750 #define CONFIG_HAS_FSL_DR_USB 751 752 #define CONFIG_MMC 753 754 #ifdef CONFIG_MMC 755 #define CONFIG_FSL_ESDHC 756 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 757 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 758 #define CONFIG_CMD_MMC 759 #define CONFIG_GENERIC_MMC 760 #define CONFIG_CMD_EXT2 761 #define CONFIG_CMD_FAT 762 #define CONFIG_DOS_PARTITION 763 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 764 #endif 765 766 /* Hash command with SHA acceleration supported in hardware */ 767 #ifdef CONFIG_FSL_CAAM 768 #define CONFIG_CMD_HASH 769 #define CONFIG_SHA_HW_ACCEL 770 #endif 771 772 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 773 774 #define __USB_PHY_TYPE utmi 775 776 /* 777 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 778 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 779 * interleaving. It can be cacheline, page, bank, superbank. 780 * See doc/README.fsl-ddr for details. 781 */ 782 #ifdef CONFIG_PPC_T4240 783 #define CTRL_INTLV_PREFERED 3way_4KB 784 #else 785 #define CTRL_INTLV_PREFERED cacheline 786 #endif 787 788 #define CONFIG_EXTRA_ENV_SETTINGS \ 789 "hwconfig=fsl_ddr:" \ 790 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 791 "bank_intlv=auto;" \ 792 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 793 "netdev=eth0\0" \ 794 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 795 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 796 "tftpflash=tftpboot $loadaddr $uboot && " \ 797 "protect off $ubootaddr +$filesize && " \ 798 "erase $ubootaddr +$filesize && " \ 799 "cp.b $loadaddr $ubootaddr $filesize && " \ 800 "protect on $ubootaddr +$filesize && " \ 801 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 802 "consoledev=ttyS0\0" \ 803 "ramdiskaddr=2000000\0" \ 804 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 805 "fdtaddr=c00000\0" \ 806 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 807 "bdev=sda3\0" 808 809 #define CONFIG_HVBOOT \ 810 "setenv bootargs config-addr=0x60000000; " \ 811 "bootm 0x01000000 - 0x00f00000" 812 813 #define CONFIG_LINUX \ 814 "setenv bootargs root=/dev/ram rw " \ 815 "console=$consoledev,$baudrate $othbootargs;" \ 816 "setenv ramdiskaddr 0x02000000;" \ 817 "setenv fdtaddr 0x00c00000;" \ 818 "setenv loadaddr 0x1000000;" \ 819 "bootm $loadaddr $ramdiskaddr $fdtaddr" 820 821 #define CONFIG_HDBOOT \ 822 "setenv bootargs root=/dev/$bdev rw " \ 823 "console=$consoledev,$baudrate $othbootargs;" \ 824 "tftp $loadaddr $bootfile;" \ 825 "tftp $fdtaddr $fdtfile;" \ 826 "bootm $loadaddr - $fdtaddr" 827 828 #define CONFIG_NFSBOOTCOMMAND \ 829 "setenv bootargs root=/dev/nfs rw " \ 830 "nfsroot=$serverip:$rootpath " \ 831 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 832 "console=$consoledev,$baudrate $othbootargs;" \ 833 "tftp $loadaddr $bootfile;" \ 834 "tftp $fdtaddr $fdtfile;" \ 835 "bootm $loadaddr - $fdtaddr" 836 837 #define CONFIG_RAMBOOTCOMMAND \ 838 "setenv bootargs root=/dev/ram rw " \ 839 "console=$consoledev,$baudrate $othbootargs;" \ 840 "tftp $ramdiskaddr $ramdiskfile;" \ 841 "tftp $loadaddr $bootfile;" \ 842 "tftp $fdtaddr $fdtfile;" \ 843 "bootm $loadaddr $ramdiskaddr $fdtaddr" 844 845 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 846 847 #include <asm/fsl_secure_boot.h> 848 849 #endif /* __CONFIG_H */ 850