1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_FSL_SATA_V2 14 #define CONFIG_PCIE4 15 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 20 #ifndef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 23 #else 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x00201000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #define RESET_VECTOR_OFFSET 0x27FFC 31 #define BOOT_PAGE_OFFSET 0x27000 32 33 #ifdef CONFIG_SDCARD 34 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 35 #define CONFIG_SPL_MMC_MINIMAL 36 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 37 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 38 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 39 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 40 #ifndef CONFIG_SPL_BUILD 41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 42 #endif 43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 44 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg 45 #define CONFIG_SPL_MMC_BOOT 46 #endif 47 48 #ifdef CONFIG_SPL_BUILD 49 #define CONFIG_SPL_SKIP_RELOCATE 50 #define CONFIG_SPL_COMMON_INIT_DDR 51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 52 #define CONFIG_SYS_NO_FLASH 53 #endif 54 55 #endif 56 #endif /* CONFIG_RAMBOOT_PBL */ 57 58 #define CONFIG_DDR_ECC 59 60 #define CONFIG_CMD_REGINFO 61 62 /* High Level Configuration Options */ 63 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 64 #define CONFIG_MP /* support multiple processors */ 65 66 #ifndef CONFIG_SYS_TEXT_BASE 67 #define CONFIG_SYS_TEXT_BASE 0xeff40000 68 #endif 69 70 #ifndef CONFIG_RESET_VECTOR_ADDRESS 71 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 72 #endif 73 74 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 75 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 76 #define CONFIG_FSL_IFC /* Enable IFC Support */ 77 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 78 #define CONFIG_PCIE1 /* PCIE controller 1 */ 79 #define CONFIG_PCIE2 /* PCIE controller 2 */ 80 #define CONFIG_PCIE3 /* PCIE controller 3 */ 81 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 82 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 83 84 #define CONFIG_ENV_OVERWRITE 85 86 /* 87 * These can be toggled for performance analysis, otherwise use default. 88 */ 89 #define CONFIG_SYS_CACHE_STASHING 90 #define CONFIG_BTB /* toggle branch predition */ 91 #ifdef CONFIG_DDR_ECC 92 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 93 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 94 #endif 95 96 #define CONFIG_ENABLE_36BIT_PHYS 97 98 #define CONFIG_ADDR_MAP 99 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 100 101 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 102 #define CONFIG_SYS_MEMTEST_END 0x00400000 103 #define CONFIG_SYS_ALT_MEMTEST 104 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 105 106 /* 107 * Config the L3 Cache as L3 SRAM 108 */ 109 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 110 #define CONFIG_SYS_L3_SIZE (512 << 10) 111 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 112 #ifdef CONFIG_RAMBOOT_PBL 113 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 114 #endif 115 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 116 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 117 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 118 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 119 120 #define CONFIG_SYS_DCSRBAR 0xf0000000 121 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 122 123 /* 124 * DDR Setup 125 */ 126 #define CONFIG_VERY_BIG_RAM 127 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 128 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 129 130 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 131 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 132 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 133 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 134 135 #define CONFIG_DDR_SPD 136 #define CONFIG_SYS_FSL_DDR3 137 138 /* 139 * IFC Definitions 140 */ 141 #define CONFIG_SYS_FLASH_BASE 0xe0000000 142 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 143 144 #ifdef CONFIG_SPL_BUILD 145 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 146 #else 147 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 148 #endif 149 150 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 151 #define CONFIG_MISC_INIT_R 152 153 #define CONFIG_HWCONFIG 154 155 /* define to use L1 as initial stack */ 156 #define CONFIG_L1_INIT_RAM 157 #define CONFIG_SYS_INIT_RAM_LOCK 158 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 159 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 160 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 161 /* The assembler doesn't like typecast */ 162 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 163 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 164 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 165 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 166 167 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 168 GENERATED_GBL_DATA_SIZE) 169 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 170 171 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 172 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 173 174 /* Serial Port - controlled on board with jumper J8 175 * open - index 2 176 * shorted - index 1 177 */ 178 #define CONFIG_CONS_INDEX 1 179 #define CONFIG_SYS_NS16550_SERIAL 180 #define CONFIG_SYS_NS16550_REG_SIZE 1 181 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 182 183 #define CONFIG_SYS_BAUDRATE_TABLE \ 184 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 185 186 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 187 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 188 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 189 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 190 191 /* I2C */ 192 #define CONFIG_SYS_I2C 193 #define CONFIG_SYS_I2C_FSL 194 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 195 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 196 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 197 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 198 199 /* 200 * General PCI 201 * Memory space is mapped 1-1, but I/O space must start from 0. 202 */ 203 204 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 205 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 206 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 207 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 208 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 209 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 210 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 211 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 212 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 213 214 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 215 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 216 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 217 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 218 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 219 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 220 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 221 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 222 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 223 224 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 225 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 226 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 227 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 228 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 229 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 230 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 231 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 232 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 233 234 /* controller 4, Base address 203000 */ 235 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 236 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 237 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 238 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 239 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 240 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 241 242 #ifdef CONFIG_PCI 243 #define CONFIG_PCI_INDIRECT_BRIDGE 244 245 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 246 #define CONFIG_DOS_PARTITION 247 #endif /* CONFIG_PCI */ 248 249 /* SATA */ 250 #ifdef CONFIG_FSL_SATA_V2 251 #define CONFIG_LIBATA 252 #define CONFIG_FSL_SATA 253 254 #define CONFIG_SYS_SATA_MAX_DEVICE 2 255 #define CONFIG_SATA1 256 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 257 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 258 #define CONFIG_SATA2 259 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 260 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 261 262 #define CONFIG_LBA48 263 #define CONFIG_CMD_SATA 264 #define CONFIG_DOS_PARTITION 265 #endif 266 267 #ifdef CONFIG_FMAN_ENET 268 #define CONFIG_MII /* MII PHY management */ 269 #define CONFIG_ETHPRIME "FM1@DTSEC1" 270 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 271 #endif 272 273 /* 274 * Environment 275 */ 276 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 277 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 278 279 /* 280 * Command line configuration. 281 */ 282 #define CONFIG_CMD_ERRATA 283 #define CONFIG_CMD_IRQ 284 285 #ifdef CONFIG_PCI 286 #define CONFIG_CMD_PCI 287 #endif 288 289 /* 290 * Miscellaneous configurable options 291 */ 292 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 293 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 294 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 295 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 296 #ifdef CONFIG_CMD_KGDB 297 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 298 #else 299 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 300 #endif 301 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 302 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 303 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 304 305 /* 306 * For booting Linux, the board info and command line data 307 * have to be in the first 64 MB of memory, since this is 308 * the maximum mapped by the Linux kernel during initialization. 309 */ 310 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 311 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 312 313 #ifdef CONFIG_CMD_KGDB 314 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 315 #endif 316 317 /* 318 * Environment Configuration 319 */ 320 #define CONFIG_ROOTPATH "/opt/nfsroot" 321 #define CONFIG_BOOTFILE "uImage" 322 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 323 324 /* default location for tftp and bootm */ 325 #define CONFIG_LOADADDR 1000000 326 327 #define CONFIG_BAUDRATE 115200 328 329 #define CONFIG_HVBOOT \ 330 "setenv bootargs config-addr=0x60000000; " \ 331 "bootm 0x01000000 - 0x00f00000" 332 333 #ifdef CONFIG_SYS_NO_FLASH 334 #ifndef CONFIG_RAMBOOT_PBL 335 #define CONFIG_ENV_IS_NOWHERE 336 #endif 337 #else 338 #define CONFIG_FLASH_CFI_DRIVER 339 #define CONFIG_SYS_FLASH_CFI 340 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 341 #endif 342 343 #if defined(CONFIG_SPIFLASH) 344 #define CONFIG_SYS_EXTRA_ENV_RELOC 345 #define CONFIG_ENV_IS_IN_SPI_FLASH 346 #define CONFIG_ENV_SPI_BUS 0 347 #define CONFIG_ENV_SPI_CS 0 348 #define CONFIG_ENV_SPI_MAX_HZ 10000000 349 #define CONFIG_ENV_SPI_MODE 0 350 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 351 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 352 #define CONFIG_ENV_SECT_SIZE 0x10000 353 #elif defined(CONFIG_SDCARD) 354 #define CONFIG_SYS_EXTRA_ENV_RELOC 355 #define CONFIG_ENV_IS_IN_MMC 356 #define CONFIG_SYS_MMC_ENV_DEV 0 357 #define CONFIG_ENV_SIZE 0x2000 358 #define CONFIG_ENV_OFFSET (512 * 0x800) 359 #elif defined(CONFIG_NAND) 360 #define CONFIG_SYS_EXTRA_ENV_RELOC 361 #define CONFIG_ENV_IS_IN_NAND 362 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 363 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 364 #elif defined(CONFIG_ENV_IS_NOWHERE) 365 #define CONFIG_ENV_SIZE 0x2000 366 #else 367 #define CONFIG_ENV_IS_IN_FLASH 368 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 369 #define CONFIG_ENV_SIZE 0x2000 370 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 371 #endif 372 373 #define CONFIG_SYS_CLK_FREQ 66666666 374 #define CONFIG_DDR_CLK_FREQ 133333333 375 376 #ifndef __ASSEMBLY__ 377 unsigned long get_board_sys_clk(void); 378 unsigned long get_board_ddr_clk(void); 379 #endif 380 381 /* 382 * DDR Setup 383 */ 384 #define CONFIG_SYS_SPD_BUS_NUM 0 385 #define SPD_EEPROM_ADDRESS1 0x52 386 #define SPD_EEPROM_ADDRESS2 0x54 387 #define SPD_EEPROM_ADDRESS3 0x56 388 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 389 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 390 391 /* 392 * IFC Definitions 393 */ 394 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 395 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 396 + 0x8000000) | \ 397 CSPR_PORT_SIZE_16 | \ 398 CSPR_MSEL_NOR | \ 399 CSPR_V) 400 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 401 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 402 CSPR_PORT_SIZE_16 | \ 403 CSPR_MSEL_NOR | \ 404 CSPR_V) 405 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 406 /* NOR Flash Timing Params */ 407 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 408 409 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 410 FTIM0_NOR_TEADC(0x5) | \ 411 FTIM0_NOR_TEAHC(0x5)) 412 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 413 FTIM1_NOR_TRAD_NOR(0x1A) |\ 414 FTIM1_NOR_TSEQRAD_NOR(0x13)) 415 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 416 FTIM2_NOR_TCH(0x4) | \ 417 FTIM2_NOR_TWPH(0x0E) | \ 418 FTIM2_NOR_TWP(0x1c)) 419 #define CONFIG_SYS_NOR_FTIM3 0x0 420 421 #define CONFIG_SYS_FLASH_QUIET_TEST 422 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 423 424 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 425 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 426 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 427 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 428 429 #define CONFIG_SYS_FLASH_EMPTY_INFO 430 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 431 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 432 433 /* NAND Flash on IFC */ 434 #define CONFIG_NAND_FSL_IFC 435 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 436 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 437 #define CONFIG_SYS_NAND_BASE 0xff800000 438 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 439 440 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 441 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 442 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 443 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 444 | CSPR_V) 445 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 446 447 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 448 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 449 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 450 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 451 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 452 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 453 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 454 455 #define CONFIG_SYS_NAND_ONFI_DETECTION 456 457 /* ONFI NAND Flash mode0 Timing Params */ 458 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 459 FTIM0_NAND_TWP(0x18) | \ 460 FTIM0_NAND_TWCHT(0x07) | \ 461 FTIM0_NAND_TWH(0x0a)) 462 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 463 FTIM1_NAND_TWBE(0x39) | \ 464 FTIM1_NAND_TRR(0x0e) | \ 465 FTIM1_NAND_TRP(0x18)) 466 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 467 FTIM2_NAND_TREH(0x0a) | \ 468 FTIM2_NAND_TWHRE(0x1e)) 469 #define CONFIG_SYS_NAND_FTIM3 0x0 470 471 #define CONFIG_SYS_NAND_DDR_LAW 11 472 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 473 #define CONFIG_SYS_MAX_NAND_DEVICE 1 474 #define CONFIG_CMD_NAND 475 476 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 477 478 #if defined(CONFIG_NAND) 479 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 480 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 481 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 482 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 483 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 484 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 485 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 486 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 487 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 488 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 489 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 490 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 491 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 492 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 493 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 494 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 495 #else 496 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 497 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 498 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 499 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 500 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 501 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 502 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 503 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 504 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 505 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 506 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 507 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 508 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 509 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 510 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 511 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 512 #endif 513 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 514 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 515 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 516 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 517 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 518 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 519 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 520 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 521 522 /* CPLD on IFC */ 523 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 524 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 525 #define CONFIG_SYS_CSPR3_EXT (0xf) 526 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 527 | CSPR_PORT_SIZE_8 \ 528 | CSPR_MSEL_GPCM \ 529 | CSPR_V) 530 531 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 532 #define CONFIG_SYS_CSOR3 0x0 533 534 /* CPLD Timing parameters for IFC CS3 */ 535 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 536 FTIM0_GPCM_TEADC(0x0e) | \ 537 FTIM0_GPCM_TEAHC(0x0e)) 538 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 539 FTIM1_GPCM_TRAD(0x1f)) 540 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 541 FTIM2_GPCM_TCH(0x8) | \ 542 FTIM2_GPCM_TWP(0x1f)) 543 #define CONFIG_SYS_CS3_FTIM3 0x0 544 545 #if defined(CONFIG_RAMBOOT_PBL) 546 #define CONFIG_SYS_RAMBOOT 547 #endif 548 549 /* I2C */ 550 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 551 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 552 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 553 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 554 555 #define I2C_MUX_CH_DEFAULT 0x8 556 #define I2C_MUX_CH_VOL_MONITOR 0xa 557 #define I2C_MUX_CH_VSC3316_FS 0xc 558 #define I2C_MUX_CH_VSC3316_BS 0xd 559 560 /* Voltage monitor on channel 2*/ 561 #define I2C_VOL_MONITOR_ADDR 0x40 562 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 563 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 564 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 565 566 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 567 #ifndef CONFIG_SPL_BUILD 568 #define CONFIG_VID 569 #endif 570 #define CONFIG_VOL_MONITOR_IR36021_SET 571 #define CONFIG_VOL_MONITOR_IR36021_READ 572 /* The lowest and highest voltage allowed for T4240RDB */ 573 #define VDD_MV_MIN 819 574 #define VDD_MV_MAX 1212 575 576 /* 577 * eSPI - Enhanced SPI 578 */ 579 #define CONFIG_SF_DEFAULT_SPEED 10000000 580 #define CONFIG_SF_DEFAULT_MODE 0 581 582 /* Qman/Bman */ 583 #ifndef CONFIG_NOBQFMAN 584 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 585 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 586 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 587 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 588 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 589 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 590 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 591 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 592 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 593 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 594 CONFIG_SYS_BMAN_CENA_SIZE) 595 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 596 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 597 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 598 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 599 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 600 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 601 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 602 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 603 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 604 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 605 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 606 CONFIG_SYS_QMAN_CENA_SIZE) 607 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 608 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 609 610 #define CONFIG_SYS_DPAA_FMAN 611 #define CONFIG_SYS_DPAA_PME 612 #define CONFIG_SYS_PMAN 613 #define CONFIG_SYS_DPAA_DCE 614 #define CONFIG_SYS_DPAA_RMAN 615 #define CONFIG_SYS_INTERLAKEN 616 617 /* Default address of microcode for the Linux Fman driver */ 618 #if defined(CONFIG_SPIFLASH) 619 /* 620 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 621 * env, so we got 0x110000. 622 */ 623 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 624 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 625 #elif defined(CONFIG_SDCARD) 626 /* 627 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 628 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 629 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 630 */ 631 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 632 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 633 #elif defined(CONFIG_NAND) 634 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 635 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 636 #else 637 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 638 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 639 #endif 640 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 641 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 642 #endif /* CONFIG_NOBQFMAN */ 643 644 #ifdef CONFIG_SYS_DPAA_FMAN 645 #define CONFIG_FMAN_ENET 646 #define CONFIG_PHYLIB_10G 647 #define CONFIG_PHY_VITESSE 648 #define CONFIG_PHY_CORTINA 649 #define CONFIG_SYS_CORTINA_FW_IN_NOR 650 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 651 #define CONFIG_CORTINA_FW_LENGTH 0x40000 652 #define CONFIG_PHY_TERANETICS 653 #define SGMII_PHY_ADDR1 0x0 654 #define SGMII_PHY_ADDR2 0x1 655 #define SGMII_PHY_ADDR3 0x2 656 #define SGMII_PHY_ADDR4 0x3 657 #define SGMII_PHY_ADDR5 0x4 658 #define SGMII_PHY_ADDR6 0x5 659 #define SGMII_PHY_ADDR7 0x6 660 #define SGMII_PHY_ADDR8 0x7 661 #define FM1_10GEC1_PHY_ADDR 0x10 662 #define FM1_10GEC2_PHY_ADDR 0x11 663 #define FM2_10GEC1_PHY_ADDR 0x12 664 #define FM2_10GEC2_PHY_ADDR 0x13 665 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 666 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 667 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 668 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 669 #endif 670 671 /* SATA */ 672 #ifdef CONFIG_FSL_SATA_V2 673 #define CONFIG_LIBATA 674 #define CONFIG_FSL_SATA 675 676 #define CONFIG_SYS_SATA_MAX_DEVICE 2 677 #define CONFIG_SATA1 678 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 679 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 680 #define CONFIG_SATA2 681 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 682 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 683 684 #define CONFIG_LBA48 685 #define CONFIG_CMD_SATA 686 #define CONFIG_DOS_PARTITION 687 #endif 688 689 #ifdef CONFIG_FMAN_ENET 690 #define CONFIG_MII /* MII PHY management */ 691 #define CONFIG_ETHPRIME "FM1@DTSEC1" 692 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 693 #endif 694 695 /* 696 * USB 697 */ 698 #define CONFIG_USB_EHCI 699 #define CONFIG_USB_EHCI_FSL 700 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 701 #define CONFIG_HAS_FSL_DR_USB 702 703 #ifdef CONFIG_MMC 704 #define CONFIG_FSL_ESDHC 705 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 706 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 707 #define CONFIG_GENERIC_MMC 708 #define CONFIG_DOS_PARTITION 709 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 710 #endif 711 712 /* Hash command with SHA acceleration supported in hardware */ 713 #ifdef CONFIG_FSL_CAAM 714 #define CONFIG_CMD_HASH 715 #define CONFIG_SHA_HW_ACCEL 716 #endif 717 718 719 #define __USB_PHY_TYPE utmi 720 721 /* 722 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 723 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 724 * interleaving. It can be cacheline, page, bank, superbank. 725 * See doc/README.fsl-ddr for details. 726 */ 727 #ifdef CONFIG_ARCH_T4240 728 #define CTRL_INTLV_PREFERED 3way_4KB 729 #else 730 #define CTRL_INTLV_PREFERED cacheline 731 #endif 732 733 #define CONFIG_EXTRA_ENV_SETTINGS \ 734 "hwconfig=fsl_ddr:" \ 735 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 736 "bank_intlv=auto;" \ 737 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 738 "netdev=eth0\0" \ 739 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 740 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 741 "tftpflash=tftpboot $loadaddr $uboot && " \ 742 "protect off $ubootaddr +$filesize && " \ 743 "erase $ubootaddr +$filesize && " \ 744 "cp.b $loadaddr $ubootaddr $filesize && " \ 745 "protect on $ubootaddr +$filesize && " \ 746 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 747 "consoledev=ttyS0\0" \ 748 "ramdiskaddr=2000000\0" \ 749 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 750 "fdtaddr=1e00000\0" \ 751 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 752 "bdev=sda3\0" 753 754 #define CONFIG_HVBOOT \ 755 "setenv bootargs config-addr=0x60000000; " \ 756 "bootm 0x01000000 - 0x00f00000" 757 758 #define CONFIG_LINUX \ 759 "setenv bootargs root=/dev/ram rw " \ 760 "console=$consoledev,$baudrate $othbootargs;" \ 761 "setenv ramdiskaddr 0x02000000;" \ 762 "setenv fdtaddr 0x00c00000;" \ 763 "setenv loadaddr 0x1000000;" \ 764 "bootm $loadaddr $ramdiskaddr $fdtaddr" 765 766 #define CONFIG_HDBOOT \ 767 "setenv bootargs root=/dev/$bdev rw " \ 768 "console=$consoledev,$baudrate $othbootargs;" \ 769 "tftp $loadaddr $bootfile;" \ 770 "tftp $fdtaddr $fdtfile;" \ 771 "bootm $loadaddr - $fdtaddr" 772 773 #define CONFIG_NFSBOOTCOMMAND \ 774 "setenv bootargs root=/dev/nfs rw " \ 775 "nfsroot=$serverip:$rootpath " \ 776 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 777 "console=$consoledev,$baudrate $othbootargs;" \ 778 "tftp $loadaddr $bootfile;" \ 779 "tftp $fdtaddr $fdtfile;" \ 780 "bootm $loadaddr - $fdtaddr" 781 782 #define CONFIG_RAMBOOTCOMMAND \ 783 "setenv bootargs root=/dev/ram rw " \ 784 "console=$consoledev,$baudrate $othbootargs;" \ 785 "tftp $ramdiskaddr $ramdiskfile;" \ 786 "tftp $loadaddr $bootfile;" \ 787 "tftp $fdtaddr $fdtfile;" \ 788 "bootm $loadaddr $ramdiskaddr $fdtaddr" 789 790 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 791 792 #include <asm/fsl_secure_boot.h> 793 794 #endif /* __CONFIG_H */ 795