1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_FSL_SATA_V2 14 #define CONFIG_PCIE4 15 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 20 #ifndef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 23 #else 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x00201000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #define RESET_VECTOR_OFFSET 0x27FFC 31 #define BOOT_PAGE_OFFSET 0x27000 32 33 #ifdef CONFIG_SDCARD 34 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 35 #define CONFIG_SPL_MMC_MINIMAL 36 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 37 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 38 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 39 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 40 #ifndef CONFIG_SPL_BUILD 41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 42 #endif 43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 44 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg 45 #define CONFIG_SPL_MMC_BOOT 46 #endif 47 48 #ifdef CONFIG_SPL_BUILD 49 #define CONFIG_SPL_SKIP_RELOCATE 50 #define CONFIG_SPL_COMMON_INIT_DDR 51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 52 #endif 53 54 #endif 55 #endif /* CONFIG_RAMBOOT_PBL */ 56 57 #define CONFIG_DDR_ECC 58 59 /* High Level Configuration Options */ 60 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 61 #define CONFIG_MP /* support multiple processors */ 62 63 #ifndef CONFIG_SYS_TEXT_BASE 64 #define CONFIG_SYS_TEXT_BASE 0xeff40000 65 #endif 66 67 #ifndef CONFIG_RESET_VECTOR_ADDRESS 68 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 69 #endif 70 71 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 72 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 73 #define CONFIG_PCIE1 /* PCIE controller 1 */ 74 #define CONFIG_PCIE2 /* PCIE controller 2 */ 75 #define CONFIG_PCIE3 /* PCIE controller 3 */ 76 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 77 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 78 79 #define CONFIG_ENV_OVERWRITE 80 81 /* 82 * These can be toggled for performance analysis, otherwise use default. 83 */ 84 #define CONFIG_SYS_CACHE_STASHING 85 #define CONFIG_BTB /* toggle branch predition */ 86 #ifdef CONFIG_DDR_ECC 87 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 88 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 89 #endif 90 91 #define CONFIG_ENABLE_36BIT_PHYS 92 93 #define CONFIG_ADDR_MAP 94 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 95 96 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 97 #define CONFIG_SYS_MEMTEST_END 0x00400000 98 #define CONFIG_SYS_ALT_MEMTEST 99 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 100 101 /* 102 * Config the L3 Cache as L3 SRAM 103 */ 104 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 105 #define CONFIG_SYS_L3_SIZE (512 << 10) 106 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 107 #ifdef CONFIG_RAMBOOT_PBL 108 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 109 #endif 110 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 111 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 112 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 113 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 114 115 #define CONFIG_SYS_DCSRBAR 0xf0000000 116 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 117 118 /* 119 * DDR Setup 120 */ 121 #define CONFIG_VERY_BIG_RAM 122 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 123 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 124 125 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 126 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 127 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 128 129 #define CONFIG_DDR_SPD 130 131 /* 132 * IFC Definitions 133 */ 134 #define CONFIG_SYS_FLASH_BASE 0xe0000000 135 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 136 137 #ifdef CONFIG_SPL_BUILD 138 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 139 #else 140 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 141 #endif 142 143 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 144 #define CONFIG_MISC_INIT_R 145 146 #define CONFIG_HWCONFIG 147 148 /* define to use L1 as initial stack */ 149 #define CONFIG_L1_INIT_RAM 150 #define CONFIG_SYS_INIT_RAM_LOCK 151 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 152 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 153 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 154 /* The assembler doesn't like typecast */ 155 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 156 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 157 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 158 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 159 160 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 161 GENERATED_GBL_DATA_SIZE) 162 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 163 164 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 165 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 166 167 /* Serial Port - controlled on board with jumper J8 168 * open - index 2 169 * shorted - index 1 170 */ 171 #define CONFIG_CONS_INDEX 1 172 #define CONFIG_SYS_NS16550_SERIAL 173 #define CONFIG_SYS_NS16550_REG_SIZE 1 174 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 175 176 #define CONFIG_SYS_BAUDRATE_TABLE \ 177 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 178 179 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 180 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 181 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 182 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 183 184 /* I2C */ 185 #define CONFIG_SYS_I2C 186 #define CONFIG_SYS_I2C_FSL 187 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 188 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 189 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 190 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 191 192 /* 193 * General PCI 194 * Memory space is mapped 1-1, but I/O space must start from 0. 195 */ 196 197 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 198 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 199 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 200 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 201 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 202 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 203 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 204 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 205 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 206 207 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 208 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 209 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 210 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 211 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 212 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 213 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 214 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 215 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 216 217 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 218 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 219 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 220 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 221 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 222 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 223 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 224 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 225 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 226 227 /* controller 4, Base address 203000 */ 228 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 229 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 230 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 231 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 232 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 233 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 234 235 #ifdef CONFIG_PCI 236 #define CONFIG_PCI_INDIRECT_BRIDGE 237 238 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 239 #endif /* CONFIG_PCI */ 240 241 /* SATA */ 242 #ifdef CONFIG_FSL_SATA_V2 243 #define CONFIG_LIBATA 244 #define CONFIG_FSL_SATA 245 246 #define CONFIG_SYS_SATA_MAX_DEVICE 2 247 #define CONFIG_SATA1 248 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 249 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 250 #define CONFIG_SATA2 251 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 252 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 253 254 #define CONFIG_LBA48 255 #endif 256 257 #ifdef CONFIG_FMAN_ENET 258 #define CONFIG_MII /* MII PHY management */ 259 #define CONFIG_ETHPRIME "FM1@DTSEC1" 260 #endif 261 262 /* 263 * Environment 264 */ 265 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 266 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 267 268 /* 269 * Command line configuration. 270 */ 271 272 /* 273 * Miscellaneous configurable options 274 */ 275 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 276 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 277 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 278 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 279 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 280 281 /* 282 * For booting Linux, the board info and command line data 283 * have to be in the first 64 MB of memory, since this is 284 * the maximum mapped by the Linux kernel during initialization. 285 */ 286 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 287 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 288 289 #ifdef CONFIG_CMD_KGDB 290 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 291 #endif 292 293 /* 294 * Environment Configuration 295 */ 296 #define CONFIG_ROOTPATH "/opt/nfsroot" 297 #define CONFIG_BOOTFILE "uImage" 298 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 299 300 /* default location for tftp and bootm */ 301 #define CONFIG_LOADADDR 1000000 302 303 #define CONFIG_HVBOOT \ 304 "setenv bootargs config-addr=0x60000000; " \ 305 "bootm 0x01000000 - 0x00f00000" 306 307 #ifndef CONFIG_MTD_NOR_FLASH 308 #else 309 #define CONFIG_FLASH_CFI_DRIVER 310 #define CONFIG_SYS_FLASH_CFI 311 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 312 #endif 313 314 #if defined(CONFIG_SPIFLASH) 315 #define CONFIG_SYS_EXTRA_ENV_RELOC 316 #define CONFIG_ENV_SPI_BUS 0 317 #define CONFIG_ENV_SPI_CS 0 318 #define CONFIG_ENV_SPI_MAX_HZ 10000000 319 #define CONFIG_ENV_SPI_MODE 0 320 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 321 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 322 #define CONFIG_ENV_SECT_SIZE 0x10000 323 #elif defined(CONFIG_SDCARD) 324 #define CONFIG_SYS_EXTRA_ENV_RELOC 325 #define CONFIG_SYS_MMC_ENV_DEV 0 326 #define CONFIG_ENV_SIZE 0x2000 327 #define CONFIG_ENV_OFFSET (512 * 0x800) 328 #elif defined(CONFIG_NAND) 329 #define CONFIG_SYS_EXTRA_ENV_RELOC 330 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 331 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 332 #elif defined(CONFIG_ENV_IS_NOWHERE) 333 #define CONFIG_ENV_SIZE 0x2000 334 #else 335 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 336 #define CONFIG_ENV_SIZE 0x2000 337 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 338 #endif 339 340 #define CONFIG_SYS_CLK_FREQ 66666666 341 #define CONFIG_DDR_CLK_FREQ 133333333 342 343 #ifndef __ASSEMBLY__ 344 unsigned long get_board_sys_clk(void); 345 unsigned long get_board_ddr_clk(void); 346 #endif 347 348 /* 349 * DDR Setup 350 */ 351 #define CONFIG_SYS_SPD_BUS_NUM 0 352 #define SPD_EEPROM_ADDRESS1 0x52 353 #define SPD_EEPROM_ADDRESS2 0x54 354 #define SPD_EEPROM_ADDRESS3 0x56 355 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 356 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 357 358 /* 359 * IFC Definitions 360 */ 361 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 362 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 363 + 0x8000000) | \ 364 CSPR_PORT_SIZE_16 | \ 365 CSPR_MSEL_NOR | \ 366 CSPR_V) 367 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 368 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 369 CSPR_PORT_SIZE_16 | \ 370 CSPR_MSEL_NOR | \ 371 CSPR_V) 372 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 373 /* NOR Flash Timing Params */ 374 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 375 376 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 377 FTIM0_NOR_TEADC(0x5) | \ 378 FTIM0_NOR_TEAHC(0x5)) 379 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 380 FTIM1_NOR_TRAD_NOR(0x1A) |\ 381 FTIM1_NOR_TSEQRAD_NOR(0x13)) 382 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 383 FTIM2_NOR_TCH(0x4) | \ 384 FTIM2_NOR_TWPH(0x0E) | \ 385 FTIM2_NOR_TWP(0x1c)) 386 #define CONFIG_SYS_NOR_FTIM3 0x0 387 388 #define CONFIG_SYS_FLASH_QUIET_TEST 389 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 390 391 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 392 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 393 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 394 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 395 396 #define CONFIG_SYS_FLASH_EMPTY_INFO 397 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 398 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 399 400 /* NAND Flash on IFC */ 401 #define CONFIG_NAND_FSL_IFC 402 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 403 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 404 #define CONFIG_SYS_NAND_BASE 0xff800000 405 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 406 407 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 408 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 409 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 410 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 411 | CSPR_V) 412 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 413 414 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 415 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 416 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 417 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 418 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 419 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 420 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 421 422 #define CONFIG_SYS_NAND_ONFI_DETECTION 423 424 /* ONFI NAND Flash mode0 Timing Params */ 425 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 426 FTIM0_NAND_TWP(0x18) | \ 427 FTIM0_NAND_TWCHT(0x07) | \ 428 FTIM0_NAND_TWH(0x0a)) 429 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 430 FTIM1_NAND_TWBE(0x39) | \ 431 FTIM1_NAND_TRR(0x0e) | \ 432 FTIM1_NAND_TRP(0x18)) 433 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 434 FTIM2_NAND_TREH(0x0a) | \ 435 FTIM2_NAND_TWHRE(0x1e)) 436 #define CONFIG_SYS_NAND_FTIM3 0x0 437 438 #define CONFIG_SYS_NAND_DDR_LAW 11 439 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 440 #define CONFIG_SYS_MAX_NAND_DEVICE 1 441 442 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 443 444 #if defined(CONFIG_NAND) 445 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 446 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 447 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 448 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 449 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 450 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 451 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 452 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 453 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 454 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 455 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 456 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 457 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 458 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 459 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 460 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 461 #else 462 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 463 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 464 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 465 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 466 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 467 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 468 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 469 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 470 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 471 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 472 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 473 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 474 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 475 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 476 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 477 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 478 #endif 479 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 480 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 481 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 482 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 483 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 484 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 485 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 486 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 487 488 /* CPLD on IFC */ 489 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 490 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 491 #define CONFIG_SYS_CSPR3_EXT (0xf) 492 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 493 | CSPR_PORT_SIZE_8 \ 494 | CSPR_MSEL_GPCM \ 495 | CSPR_V) 496 497 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 498 #define CONFIG_SYS_CSOR3 0x0 499 500 /* CPLD Timing parameters for IFC CS3 */ 501 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 502 FTIM0_GPCM_TEADC(0x0e) | \ 503 FTIM0_GPCM_TEAHC(0x0e)) 504 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 505 FTIM1_GPCM_TRAD(0x1f)) 506 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 507 FTIM2_GPCM_TCH(0x8) | \ 508 FTIM2_GPCM_TWP(0x1f)) 509 #define CONFIG_SYS_CS3_FTIM3 0x0 510 511 #if defined(CONFIG_RAMBOOT_PBL) 512 #define CONFIG_SYS_RAMBOOT 513 #endif 514 515 /* I2C */ 516 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 517 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 518 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 519 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 520 521 #define I2C_MUX_CH_DEFAULT 0x8 522 #define I2C_MUX_CH_VOL_MONITOR 0xa 523 #define I2C_MUX_CH_VSC3316_FS 0xc 524 #define I2C_MUX_CH_VSC3316_BS 0xd 525 526 /* Voltage monitor on channel 2*/ 527 #define I2C_VOL_MONITOR_ADDR 0x40 528 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 529 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 530 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 531 532 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 533 #ifndef CONFIG_SPL_BUILD 534 #define CONFIG_VID 535 #endif 536 #define CONFIG_VOL_MONITOR_IR36021_SET 537 #define CONFIG_VOL_MONITOR_IR36021_READ 538 /* The lowest and highest voltage allowed for T4240RDB */ 539 #define VDD_MV_MIN 819 540 #define VDD_MV_MAX 1212 541 542 /* 543 * eSPI - Enhanced SPI 544 */ 545 #define CONFIG_SF_DEFAULT_SPEED 10000000 546 #define CONFIG_SF_DEFAULT_MODE 0 547 548 /* Qman/Bman */ 549 #ifndef CONFIG_NOBQFMAN 550 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 551 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 552 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 553 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 554 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 555 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 556 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 557 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 558 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 559 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 560 CONFIG_SYS_BMAN_CENA_SIZE) 561 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 562 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 563 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 564 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 565 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 566 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 567 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 568 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 569 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 570 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 571 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 572 CONFIG_SYS_QMAN_CENA_SIZE) 573 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 574 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 575 576 #define CONFIG_SYS_DPAA_FMAN 577 #define CONFIG_SYS_DPAA_PME 578 #define CONFIG_SYS_PMAN 579 #define CONFIG_SYS_DPAA_DCE 580 #define CONFIG_SYS_DPAA_RMAN 581 #define CONFIG_SYS_INTERLAKEN 582 583 /* Default address of microcode for the Linux Fman driver */ 584 #if defined(CONFIG_SPIFLASH) 585 /* 586 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 587 * env, so we got 0x110000. 588 */ 589 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 590 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 591 #elif defined(CONFIG_SDCARD) 592 /* 593 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 594 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 595 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 596 */ 597 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 598 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 599 #elif defined(CONFIG_NAND) 600 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 601 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 602 #else 603 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 604 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 605 #endif 606 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 607 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 608 #endif /* CONFIG_NOBQFMAN */ 609 610 #ifdef CONFIG_SYS_DPAA_FMAN 611 #define CONFIG_FMAN_ENET 612 #define CONFIG_PHYLIB_10G 613 #define CONFIG_PHY_VITESSE 614 #define CONFIG_PHY_CORTINA 615 #define CONFIG_SYS_CORTINA_FW_IN_NOR 616 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 617 #define CONFIG_CORTINA_FW_LENGTH 0x40000 618 #define CONFIG_PHY_TERANETICS 619 #define SGMII_PHY_ADDR1 0x0 620 #define SGMII_PHY_ADDR2 0x1 621 #define SGMII_PHY_ADDR3 0x2 622 #define SGMII_PHY_ADDR4 0x3 623 #define SGMII_PHY_ADDR5 0x4 624 #define SGMII_PHY_ADDR6 0x5 625 #define SGMII_PHY_ADDR7 0x6 626 #define SGMII_PHY_ADDR8 0x7 627 #define FM1_10GEC1_PHY_ADDR 0x10 628 #define FM1_10GEC2_PHY_ADDR 0x11 629 #define FM2_10GEC1_PHY_ADDR 0x12 630 #define FM2_10GEC2_PHY_ADDR 0x13 631 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 632 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 633 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 634 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 635 #endif 636 637 /* SATA */ 638 #ifdef CONFIG_FSL_SATA_V2 639 #define CONFIG_LIBATA 640 #define CONFIG_FSL_SATA 641 642 #define CONFIG_SYS_SATA_MAX_DEVICE 2 643 #define CONFIG_SATA1 644 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 645 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 646 #define CONFIG_SATA2 647 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 648 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 649 650 #define CONFIG_LBA48 651 #endif 652 653 #ifdef CONFIG_FMAN_ENET 654 #define CONFIG_MII /* MII PHY management */ 655 #define CONFIG_ETHPRIME "FM1@DTSEC1" 656 #endif 657 658 /* 659 * USB 660 */ 661 #define CONFIG_USB_EHCI_FSL 662 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 663 #define CONFIG_HAS_FSL_DR_USB 664 665 #ifdef CONFIG_MMC 666 #define CONFIG_FSL_ESDHC 667 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 668 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 669 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 670 #endif 671 672 673 #define __USB_PHY_TYPE utmi 674 675 /* 676 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 677 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 678 * interleaving. It can be cacheline, page, bank, superbank. 679 * See doc/README.fsl-ddr for details. 680 */ 681 #ifdef CONFIG_ARCH_T4240 682 #define CTRL_INTLV_PREFERED 3way_4KB 683 #else 684 #define CTRL_INTLV_PREFERED cacheline 685 #endif 686 687 #define CONFIG_EXTRA_ENV_SETTINGS \ 688 "hwconfig=fsl_ddr:" \ 689 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 690 "bank_intlv=auto;" \ 691 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 692 "netdev=eth0\0" \ 693 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 694 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 695 "tftpflash=tftpboot $loadaddr $uboot && " \ 696 "protect off $ubootaddr +$filesize && " \ 697 "erase $ubootaddr +$filesize && " \ 698 "cp.b $loadaddr $ubootaddr $filesize && " \ 699 "protect on $ubootaddr +$filesize && " \ 700 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 701 "consoledev=ttyS0\0" \ 702 "ramdiskaddr=2000000\0" \ 703 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 704 "fdtaddr=1e00000\0" \ 705 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 706 "bdev=sda3\0" 707 708 #define CONFIG_HVBOOT \ 709 "setenv bootargs config-addr=0x60000000; " \ 710 "bootm 0x01000000 - 0x00f00000" 711 712 #define CONFIG_LINUX \ 713 "setenv bootargs root=/dev/ram rw " \ 714 "console=$consoledev,$baudrate $othbootargs;" \ 715 "setenv ramdiskaddr 0x02000000;" \ 716 "setenv fdtaddr 0x00c00000;" \ 717 "setenv loadaddr 0x1000000;" \ 718 "bootm $loadaddr $ramdiskaddr $fdtaddr" 719 720 #define CONFIG_HDBOOT \ 721 "setenv bootargs root=/dev/$bdev rw " \ 722 "console=$consoledev,$baudrate $othbootargs;" \ 723 "tftp $loadaddr $bootfile;" \ 724 "tftp $fdtaddr $fdtfile;" \ 725 "bootm $loadaddr - $fdtaddr" 726 727 #define CONFIG_NFSBOOTCOMMAND \ 728 "setenv bootargs root=/dev/nfs rw " \ 729 "nfsroot=$serverip:$rootpath " \ 730 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 731 "console=$consoledev,$baudrate $othbootargs;" \ 732 "tftp $loadaddr $bootfile;" \ 733 "tftp $fdtaddr $fdtfile;" \ 734 "bootm $loadaddr - $fdtaddr" 735 736 #define CONFIG_RAMBOOTCOMMAND \ 737 "setenv bootargs root=/dev/ram rw " \ 738 "console=$consoledev,$baudrate $othbootargs;" \ 739 "tftp $ramdiskaddr $ramdiskfile;" \ 740 "tftp $loadaddr $bootfile;" \ 741 "tftp $fdtaddr $fdtfile;" \ 742 "bootm $loadaddr $ramdiskaddr $fdtaddr" 743 744 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 745 746 #include <asm/fsl_secure_boot.h> 747 748 #endif /* __CONFIG_H */ 749