1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 QDS board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240QDS 14 #define CONFIG_PHYS_64BIT 15 16 #define CONFIG_FSL_SATA_V2 17 #define CONFIG_PCIE4 18 19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 23 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 24 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg 25 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg 26 #endif 27 28 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 29 /* Set 1M boot space */ 30 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 31 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 32 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #define CONFIG_SYS_NO_FLASH 35 #endif 36 37 #define CONFIG_SRIO_PCIE_BOOT_MASTER 38 #define CONFIG_DDR_ECC 39 40 #include "t4qds.h" 41 42 #ifdef CONFIG_SYS_NO_FLASH 43 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 44 #define CONFIG_ENV_IS_NOWHERE 45 #endif 46 #else 47 #define CONFIG_FLASH_CFI_DRIVER 48 #define CONFIG_SYS_FLASH_CFI 49 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 50 #endif 51 52 #if defined(CONFIG_SPIFLASH) 53 #define CONFIG_SYS_EXTRA_ENV_RELOC 54 #define CONFIG_ENV_IS_IN_SPI_FLASH 55 #define CONFIG_ENV_SPI_BUS 0 56 #define CONFIG_ENV_SPI_CS 0 57 #define CONFIG_ENV_SPI_MAX_HZ 10000000 58 #define CONFIG_ENV_SPI_MODE 0 59 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 60 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 61 #define CONFIG_ENV_SECT_SIZE 0x10000 62 #elif defined(CONFIG_SDCARD) 63 #define CONFIG_SYS_EXTRA_ENV_RELOC 64 #define CONFIG_ENV_IS_IN_MMC 65 #define CONFIG_SYS_MMC_ENV_DEV 0 66 #define CONFIG_ENV_SIZE 0x2000 67 #define CONFIG_ENV_OFFSET (512 * 1658) 68 #elif defined(CONFIG_NAND) 69 #define CONFIG_SYS_EXTRA_ENV_RELOC 70 #define CONFIG_ENV_IS_IN_NAND 71 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 72 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 73 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 74 #define CONFIG_ENV_IS_IN_REMOTE 75 #define CONFIG_ENV_ADDR 0xffe20000 76 #define CONFIG_ENV_SIZE 0x2000 77 #elif defined(CONFIG_ENV_IS_NOWHERE) 78 #define CONFIG_ENV_SIZE 0x2000 79 #else 80 #define CONFIG_ENV_IS_IN_FLASH 81 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 82 #define CONFIG_ENV_SIZE 0x2000 83 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 84 #endif 85 86 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 87 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 88 89 #ifndef __ASSEMBLY__ 90 unsigned long get_board_sys_clk(void); 91 unsigned long get_board_ddr_clk(void); 92 #endif 93 94 /* EEPROM */ 95 #define CONFIG_ID_EEPROM 96 #define CONFIG_SYS_I2C_EEPROM_NXID 97 #define CONFIG_SYS_EEPROM_BUS_NUM 0 98 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 99 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 100 101 /* 102 * DDR Setup 103 */ 104 #define CONFIG_SYS_SPD_BUS_NUM 0 105 #define SPD_EEPROM_ADDRESS1 0x51 106 #define SPD_EEPROM_ADDRESS2 0x52 107 #define SPD_EEPROM_ADDRESS3 0x53 108 #define SPD_EEPROM_ADDRESS4 0x54 109 #define SPD_EEPROM_ADDRESS5 0x55 110 #define SPD_EEPROM_ADDRESS6 0x56 111 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 112 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 113 114 /* 115 * IFC Definitions 116 */ 117 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 118 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 119 + 0x8000000) | \ 120 CSPR_PORT_SIZE_16 | \ 121 CSPR_MSEL_NOR | \ 122 CSPR_V) 123 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 124 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 125 CSPR_PORT_SIZE_16 | \ 126 CSPR_MSEL_NOR | \ 127 CSPR_V) 128 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 129 /* NOR Flash Timing Params */ 130 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 131 132 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 133 FTIM0_NOR_TEADC(0x5) | \ 134 FTIM0_NOR_TEAHC(0x5)) 135 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 136 FTIM1_NOR_TRAD_NOR(0x1A) |\ 137 FTIM1_NOR_TSEQRAD_NOR(0x13)) 138 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 139 FTIM2_NOR_TCH(0x4) | \ 140 FTIM2_NOR_TWPH(0x0E) | \ 141 FTIM2_NOR_TWP(0x1c)) 142 #define CONFIG_SYS_NOR_FTIM3 0x0 143 144 #define CONFIG_SYS_FLASH_QUIET_TEST 145 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 146 147 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 148 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 149 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 150 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 151 152 #define CONFIG_SYS_FLASH_EMPTY_INFO 153 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 154 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 155 156 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 157 #define QIXIS_BASE 0xffdf0000 158 #define QIXIS_LBMAP_SWITCH 6 159 #define QIXIS_LBMAP_MASK 0x0f 160 #define QIXIS_LBMAP_SHIFT 0 161 #define QIXIS_LBMAP_DFLTBANK 0x00 162 #define QIXIS_LBMAP_ALTBANK 0x04 163 #define QIXIS_RST_CTL_RESET 0x83 164 #define QIXIS_RST_FORCE_MEM 0x1 165 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 166 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 167 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 168 #define QIXIS_BRDCFG5 0x55 169 #define QIXIS_MUX_SDHC 2 170 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 171 172 #define CONFIG_SYS_CSPR3_EXT (0xf) 173 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 174 | CSPR_PORT_SIZE_8 \ 175 | CSPR_MSEL_GPCM \ 176 | CSPR_V) 177 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 178 #define CONFIG_SYS_CSOR3 0x0 179 /* QIXIS Timing parameters for IFC CS3 */ 180 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 181 FTIM0_GPCM_TEADC(0x0e) | \ 182 FTIM0_GPCM_TEAHC(0x0e)) 183 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 184 FTIM1_GPCM_TRAD(0x3f)) 185 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 186 FTIM2_GPCM_TCH(0x0) | \ 187 FTIM2_GPCM_TWP(0x1f)) 188 #define CONFIG_SYS_CS3_FTIM3 0x0 189 190 /* NAND Flash on IFC */ 191 #define CONFIG_NAND_FSL_IFC 192 #define CONFIG_SYS_NAND_BASE 0xff800000 193 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 194 195 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 196 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 197 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 198 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 199 | CSPR_V) 200 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 201 202 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 203 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 204 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 205 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 206 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 207 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 208 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 209 210 #define CONFIG_SYS_NAND_ONFI_DETECTION 211 212 /* ONFI NAND Flash mode0 Timing Params */ 213 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 214 FTIM0_NAND_TWP(0x18) | \ 215 FTIM0_NAND_TWCHT(0x07) | \ 216 FTIM0_NAND_TWH(0x0a)) 217 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 218 FTIM1_NAND_TWBE(0x39) | \ 219 FTIM1_NAND_TRR(0x0e) | \ 220 FTIM1_NAND_TRP(0x18)) 221 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 222 FTIM2_NAND_TREH(0x0a) | \ 223 FTIM2_NAND_TWHRE(0x1e)) 224 #define CONFIG_SYS_NAND_FTIM3 0x0 225 226 #define CONFIG_SYS_NAND_DDR_LAW 11 227 228 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 229 #define CONFIG_SYS_MAX_NAND_DEVICE 1 230 #define CONFIG_MTD_NAND_VERIFY_WRITE 231 #define CONFIG_CMD_NAND 232 233 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 234 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 235 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 236 237 #if defined(CONFIG_NAND) 238 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 239 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 240 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 241 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 242 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 243 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 244 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 245 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 246 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 247 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 248 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 249 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 250 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 251 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 252 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 253 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 254 #else 255 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 256 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 257 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 258 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 259 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 260 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 261 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 262 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 263 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 264 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 265 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 266 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 267 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 268 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 269 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 270 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 271 #endif 272 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 273 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 274 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 275 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 276 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 277 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 278 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 279 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 280 281 #if defined(CONFIG_RAMBOOT_PBL) 282 #define CONFIG_SYS_RAMBOOT 283 #endif 284 285 286 /* I2C */ 287 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 288 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 289 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 290 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 291 292 #define I2C_MUX_CH_DEFAULT 0x8 293 #define I2C_MUX_CH_VOL_MONITOR 0xa 294 #define I2C_MUX_CH_VSC3316_FS 0xc 295 #define I2C_MUX_CH_VSC3316_BS 0xd 296 297 /* Voltage monitor on channel 2*/ 298 #define I2C_VOL_MONITOR_ADDR 0x40 299 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 300 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 301 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 302 303 /* VSC Crossbar switches */ 304 #define CONFIG_VSC_CROSSBAR 305 #define VSC3316_FSM_TX_ADDR 0x70 306 #define VSC3316_FSM_RX_ADDR 0x71 307 308 /* 309 * RapidIO 310 */ 311 312 /* 313 * for slave u-boot IMAGE instored in master memory space, 314 * PHYS must be aligned based on the SIZE 315 */ 316 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 317 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 318 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 319 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 320 /* 321 * for slave UCODE and ENV instored in master memory space, 322 * PHYS must be aligned based on the SIZE 323 */ 324 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 325 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 326 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 327 328 /* slave core release by master*/ 329 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 330 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 331 332 /* 333 * SRIO_PCIE_BOOT - SLAVE 334 */ 335 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 336 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 337 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 338 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 339 #endif 340 /* 341 * eSPI - Enhanced SPI 342 */ 343 #define CONFIG_FSL_ESPI 344 #define CONFIG_SPI_FLASH 345 #define CONFIG_SPI_FLASH_SST 346 #define CONFIG_CMD_SF 347 #define CONFIG_SF_DEFAULT_SPEED 10000000 348 #define CONFIG_SF_DEFAULT_MODE 0 349 350 351 /* Qman/Bman */ 352 #ifndef CONFIG_NOBQFMAN 353 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 354 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 355 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 356 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 357 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 358 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 359 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 360 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 361 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 362 363 #define CONFIG_SYS_DPAA_FMAN 364 #define CONFIG_SYS_DPAA_PME 365 #define CONFIG_SYS_PMAN 366 #define CONFIG_SYS_DPAA_DCE 367 #define CONFIG_SYS_DPAA_RMAN 368 #define CONFIG_SYS_INTERLAKEN 369 370 /* Default address of microcode for the Linux Fman driver */ 371 #if defined(CONFIG_SPIFLASH) 372 /* 373 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 374 * env, so we got 0x110000. 375 */ 376 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 377 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 378 #elif defined(CONFIG_SDCARD) 379 /* 380 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 381 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 382 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 383 */ 384 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 385 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) 386 #elif defined(CONFIG_NAND) 387 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 388 #define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 389 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 390 /* 391 * Slave has no ucode locally, it can fetch this from remote. When implementing 392 * in two corenet boards, slave's ucode could be stored in master's memory 393 * space, the address can be mapped from slave TLB->slave LAW-> 394 * slave SRIO or PCIE outbound window->master inbound window-> 395 * master LAW->the ucode address in master's memory space. 396 */ 397 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 398 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 399 #else 400 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 401 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 402 #endif 403 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 404 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 405 #endif /* CONFIG_NOBQFMAN */ 406 407 #ifdef CONFIG_SYS_DPAA_FMAN 408 #define CONFIG_FMAN_ENET 409 #define CONFIG_PHYLIB_10G 410 #define CONFIG_PHY_VITESSE 411 #define CONFIG_PHY_TERANETICS 412 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 413 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 414 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 415 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 416 #define FM1_10GEC1_PHY_ADDR 0x0 417 #define FM1_10GEC2_PHY_ADDR 0x1 418 #define FM2_10GEC1_PHY_ADDR 0x2 419 #define FM2_10GEC2_PHY_ADDR 0x3 420 #endif 421 422 423 /* SATA */ 424 #ifdef CONFIG_FSL_SATA_V2 425 #define CONFIG_LIBATA 426 #define CONFIG_FSL_SATA 427 428 #define CONFIG_SYS_SATA_MAX_DEVICE 2 429 #define CONFIG_SATA1 430 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 431 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 432 #define CONFIG_SATA2 433 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 434 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 435 436 #define CONFIG_LBA48 437 #define CONFIG_CMD_SATA 438 #define CONFIG_DOS_PARTITION 439 #define CONFIG_CMD_EXT2 440 #endif 441 442 #ifdef CONFIG_FMAN_ENET 443 #define CONFIG_MII /* MII PHY management */ 444 #define CONFIG_ETHPRIME "FM1@DTSEC1" 445 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 446 #endif 447 448 /* 449 * USB 450 */ 451 #define CONFIG_CMD_USB 452 #define CONFIG_USB_STORAGE 453 #define CONFIG_USB_EHCI 454 #define CONFIG_USB_EHCI_FSL 455 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 456 #define CONFIG_CMD_EXT2 457 #define CONFIG_HAS_FSL_DR_USB 458 459 #define CONFIG_MMC 460 461 #ifdef CONFIG_MMC 462 #define CONFIG_FSL_ESDHC 463 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 464 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 465 #define CONFIG_CMD_MMC 466 #define CONFIG_GENERIC_MMC 467 #define CONFIG_CMD_EXT2 468 #define CONFIG_CMD_FAT 469 #define CONFIG_DOS_PARTITION 470 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 471 #define CONFIG_ESDHC_DETECT_QUIRK \ 472 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ 473 IS_SVR_REV(get_svr(), 1, 0)) 474 #endif 475 476 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 477 478 #define __USB_PHY_TYPE utmi 479 480 /* 481 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 482 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 483 * interleaving. It can be cacheline, page, bank, superbank. 484 * See doc/README.fsl-ddr for details. 485 */ 486 #ifdef CONFIG_PPC_T4240 487 #define CTRL_INTLV_PREFERED 3way_4KB 488 #else 489 #define CTRL_INTLV_PREFERED cacheline 490 #endif 491 492 #define CONFIG_EXTRA_ENV_SETTINGS \ 493 "hwconfig=fsl_ddr:" \ 494 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 495 "bank_intlv=auto;" \ 496 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 497 "netdev=eth0\0" \ 498 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 499 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 500 "tftpflash=tftpboot $loadaddr $uboot && " \ 501 "protect off $ubootaddr +$filesize && " \ 502 "erase $ubootaddr +$filesize && " \ 503 "cp.b $loadaddr $ubootaddr $filesize && " \ 504 "protect on $ubootaddr +$filesize && " \ 505 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 506 "consoledev=ttyS0\0" \ 507 "ramdiskaddr=2000000\0" \ 508 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 509 "fdtaddr=c00000\0" \ 510 "fdtfile=t4240qds/t4240qds.dtb\0" \ 511 "bdev=sda3\0" \ 512 "c=ffe\0" 513 514 #define CONFIG_HVBOOT \ 515 "setenv bootargs config-addr=0x60000000; " \ 516 "bootm 0x01000000 - 0x00f00000" 517 518 #define CONFIG_ALU \ 519 "setenv bootargs root=/dev/$bdev rw " \ 520 "console=$consoledev,$baudrate $othbootargs;" \ 521 "cpu 1 release 0x01000000 - - -;" \ 522 "cpu 2 release 0x01000000 - - -;" \ 523 "cpu 3 release 0x01000000 - - -;" \ 524 "cpu 4 release 0x01000000 - - -;" \ 525 "cpu 5 release 0x01000000 - - -;" \ 526 "cpu 6 release 0x01000000 - - -;" \ 527 "cpu 7 release 0x01000000 - - -;" \ 528 "go 0x01000000" 529 530 #define CONFIG_LINUX \ 531 "setenv bootargs root=/dev/ram rw " \ 532 "console=$consoledev,$baudrate $othbootargs;" \ 533 "setenv ramdiskaddr 0x02000000;" \ 534 "setenv fdtaddr 0x00c00000;" \ 535 "setenv loadaddr 0x1000000;" \ 536 "bootm $loadaddr $ramdiskaddr $fdtaddr" 537 538 #define CONFIG_HDBOOT \ 539 "setenv bootargs root=/dev/$bdev rw " \ 540 "console=$consoledev,$baudrate $othbootargs;" \ 541 "tftp $loadaddr $bootfile;" \ 542 "tftp $fdtaddr $fdtfile;" \ 543 "bootm $loadaddr - $fdtaddr" 544 545 #define CONFIG_NFSBOOTCOMMAND \ 546 "setenv bootargs root=/dev/nfs rw " \ 547 "nfsroot=$serverip:$rootpath " \ 548 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 549 "console=$consoledev,$baudrate $othbootargs;" \ 550 "tftp $loadaddr $bootfile;" \ 551 "tftp $fdtaddr $fdtfile;" \ 552 "bootm $loadaddr - $fdtaddr" 553 554 #define CONFIG_RAMBOOTCOMMAND \ 555 "setenv bootargs root=/dev/ram rw " \ 556 "console=$consoledev,$baudrate $othbootargs;" \ 557 "tftp $ramdiskaddr $ramdiskfile;" \ 558 "tftp $loadaddr $bootfile;" \ 559 "tftp $fdtaddr $fdtfile;" \ 560 "bootm $loadaddr $ramdiskaddr $fdtaddr" 561 562 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 563 564 #include <asm/fsl_secure_boot.h> 565 566 #endif /* __CONFIG_H */ 567