1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 QDS board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240QDS 14 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_PCIE4 17 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 18 19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg 23 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg 24 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) 25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #else 28 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 29 #define CONFIG_SPL_ENV_SUPPORT 30 #define CONFIG_SPL_SERIAL_SUPPORT 31 #define CONFIG_SPL_FLUSH_IMAGE 32 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 33 #define CONFIG_SPL_LIBGENERIC_SUPPORT 34 #define CONFIG_SPL_LIBCOMMON_SUPPORT 35 #define CONFIG_SPL_I2C_SUPPORT 36 #define CONFIG_FSL_LAW /* Use common FSL init code */ 37 #define CONFIG_SYS_TEXT_BASE 0x00201000 38 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 39 #define CONFIG_SPL_PAD_TO 0x40000 40 #define CONFIG_SPL_MAX_SIZE 0x28000 41 #define RESET_VECTOR_OFFSET 0x27FFC 42 #define BOOT_PAGE_OFFSET 0x27000 43 44 #ifdef CONFIG_NAND 45 #define CONFIG_SPL_NAND_SUPPORT 46 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 47 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 48 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 49 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 50 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 51 #define CONFIG_SPL_NAND_BOOT 52 #endif 53 54 #ifdef CONFIG_SDCARD 55 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 56 #define CONFIG_SPL_MMC_SUPPORT 57 #define CONFIG_SPL_MMC_MINIMAL 58 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 59 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 60 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 61 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 62 #ifndef CONFIG_SPL_BUILD 63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 64 #endif 65 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 66 #define CONFIG_SPL_MMC_BOOT 67 #endif 68 69 #ifdef CONFIG_SPL_BUILD 70 #define CONFIG_SPL_SKIP_RELOCATE 71 #define CONFIG_SPL_COMMON_INIT_DDR 72 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 73 #define CONFIG_SYS_NO_FLASH 74 #endif 75 76 #endif 77 #endif /* CONFIG_RAMBOOT_PBL */ 78 79 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 80 /* Set 1M boot space */ 81 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 82 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 83 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 84 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 85 #define CONFIG_SYS_NO_FLASH 86 #endif 87 88 #define CONFIG_SRIO_PCIE_BOOT_MASTER 89 #define CONFIG_DDR_ECC 90 91 #include "t4qds.h" 92 93 #ifdef CONFIG_SYS_NO_FLASH 94 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 95 #define CONFIG_ENV_IS_NOWHERE 96 #endif 97 #else 98 #define CONFIG_FLASH_CFI_DRIVER 99 #define CONFIG_SYS_FLASH_CFI 100 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 101 #endif 102 103 #if defined(CONFIG_SPIFLASH) 104 #define CONFIG_SYS_EXTRA_ENV_RELOC 105 #define CONFIG_ENV_IS_IN_SPI_FLASH 106 #define CONFIG_ENV_SPI_BUS 0 107 #define CONFIG_ENV_SPI_CS 0 108 #define CONFIG_ENV_SPI_MAX_HZ 10000000 109 #define CONFIG_ENV_SPI_MODE 0 110 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 111 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 112 #define CONFIG_ENV_SECT_SIZE 0x10000 113 #elif defined(CONFIG_SDCARD) 114 #define CONFIG_SYS_EXTRA_ENV_RELOC 115 #define CONFIG_ENV_IS_IN_MMC 116 #define CONFIG_SYS_MMC_ENV_DEV 0 117 #define CONFIG_ENV_SIZE 0x2000 118 #define CONFIG_ENV_OFFSET (512 * 0x800) 119 #elif defined(CONFIG_NAND) 120 #define CONFIG_SYS_EXTRA_ENV_RELOC 121 #define CONFIG_ENV_IS_IN_NAND 122 #define CONFIG_ENV_SIZE 0x2000 123 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 124 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 125 #define CONFIG_ENV_IS_IN_REMOTE 126 #define CONFIG_ENV_ADDR 0xffe20000 127 #define CONFIG_ENV_SIZE 0x2000 128 #elif defined(CONFIG_ENV_IS_NOWHERE) 129 #define CONFIG_ENV_SIZE 0x2000 130 #else 131 #define CONFIG_ENV_IS_IN_FLASH 132 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 133 #define CONFIG_ENV_SIZE 0x2000 134 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 135 #endif 136 137 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 138 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 139 140 #ifndef __ASSEMBLY__ 141 unsigned long get_board_sys_clk(void); 142 unsigned long get_board_ddr_clk(void); 143 #endif 144 145 /* EEPROM */ 146 #define CONFIG_ID_EEPROM 147 #define CONFIG_SYS_I2C_EEPROM_NXID 148 #define CONFIG_SYS_EEPROM_BUS_NUM 0 149 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 150 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 151 152 /* 153 * DDR Setup 154 */ 155 #define CONFIG_SYS_SPD_BUS_NUM 0 156 #define SPD_EEPROM_ADDRESS1 0x51 157 #define SPD_EEPROM_ADDRESS2 0x52 158 #define SPD_EEPROM_ADDRESS3 0x53 159 #define SPD_EEPROM_ADDRESS4 0x54 160 #define SPD_EEPROM_ADDRESS5 0x55 161 #define SPD_EEPROM_ADDRESS6 0x56 162 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 163 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 164 165 /* 166 * IFC Definitions 167 */ 168 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 169 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 170 + 0x8000000) | \ 171 CSPR_PORT_SIZE_16 | \ 172 CSPR_MSEL_NOR | \ 173 CSPR_V) 174 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 175 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 176 CSPR_PORT_SIZE_16 | \ 177 CSPR_MSEL_NOR | \ 178 CSPR_V) 179 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 180 /* NOR Flash Timing Params */ 181 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 182 183 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 184 FTIM0_NOR_TEADC(0x5) | \ 185 FTIM0_NOR_TEAHC(0x5)) 186 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 187 FTIM1_NOR_TRAD_NOR(0x1A) |\ 188 FTIM1_NOR_TSEQRAD_NOR(0x13)) 189 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 190 FTIM2_NOR_TCH(0x4) | \ 191 FTIM2_NOR_TWPH(0x0E) | \ 192 FTIM2_NOR_TWP(0x1c)) 193 #define CONFIG_SYS_NOR_FTIM3 0x0 194 195 #define CONFIG_SYS_FLASH_QUIET_TEST 196 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 197 198 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 199 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 200 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 201 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 202 203 #define CONFIG_SYS_FLASH_EMPTY_INFO 204 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 205 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 206 207 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 208 #define QIXIS_BASE 0xffdf0000 209 #define QIXIS_LBMAP_SWITCH 6 210 #define QIXIS_LBMAP_MASK 0x0f 211 #define QIXIS_LBMAP_SHIFT 0 212 #define QIXIS_LBMAP_DFLTBANK 0x00 213 #define QIXIS_LBMAP_ALTBANK 0x04 214 #define QIXIS_RST_CTL_RESET 0x83 215 #define QIXIS_RST_FORCE_MEM 0x1 216 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 217 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 218 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 219 #define QIXIS_BRDCFG5 0x55 220 #define QIXIS_MUX_SDHC 2 221 #define QIXIS_MUX_SDHC_WIDTH8 1 222 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 223 224 #define CONFIG_SYS_CSPR3_EXT (0xf) 225 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 226 | CSPR_PORT_SIZE_8 \ 227 | CSPR_MSEL_GPCM \ 228 | CSPR_V) 229 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 230 #define CONFIG_SYS_CSOR3 0x0 231 /* QIXIS Timing parameters for IFC CS3 */ 232 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 233 FTIM0_GPCM_TEADC(0x0e) | \ 234 FTIM0_GPCM_TEAHC(0x0e)) 235 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 236 FTIM1_GPCM_TRAD(0x3f)) 237 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 238 FTIM2_GPCM_TCH(0x8) | \ 239 FTIM2_GPCM_TWP(0x1f)) 240 #define CONFIG_SYS_CS3_FTIM3 0x0 241 242 /* NAND Flash on IFC */ 243 #define CONFIG_NAND_FSL_IFC 244 #define CONFIG_SYS_NAND_BASE 0xff800000 245 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 246 247 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 248 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 249 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 250 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 251 | CSPR_V) 252 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 253 254 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 255 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 256 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 257 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 258 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 259 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 260 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 261 262 #define CONFIG_SYS_NAND_ONFI_DETECTION 263 264 /* ONFI NAND Flash mode0 Timing Params */ 265 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 266 FTIM0_NAND_TWP(0x18) | \ 267 FTIM0_NAND_TWCHT(0x07) | \ 268 FTIM0_NAND_TWH(0x0a)) 269 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 270 FTIM1_NAND_TWBE(0x39) | \ 271 FTIM1_NAND_TRR(0x0e) | \ 272 FTIM1_NAND_TRP(0x18)) 273 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 274 FTIM2_NAND_TREH(0x0a) | \ 275 FTIM2_NAND_TWHRE(0x1e)) 276 #define CONFIG_SYS_NAND_FTIM3 0x0 277 278 #define CONFIG_SYS_NAND_DDR_LAW 11 279 280 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 281 #define CONFIG_SYS_MAX_NAND_DEVICE 1 282 #define CONFIG_CMD_NAND 283 284 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 285 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 286 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 287 288 #if defined(CONFIG_NAND) 289 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 290 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 291 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 292 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 293 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 294 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 295 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 296 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 297 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 298 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 299 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 300 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 301 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 302 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 303 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 304 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 305 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 306 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 307 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 308 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 309 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 310 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 311 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 312 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 313 #else 314 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 315 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 316 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 317 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 318 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 319 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 320 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 321 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 322 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 323 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 324 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 325 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 326 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 327 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 328 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 329 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 330 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 331 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 332 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 333 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 334 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 335 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 336 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 337 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 338 #endif 339 340 #if defined(CONFIG_RAMBOOT_PBL) 341 #define CONFIG_SYS_RAMBOOT 342 #endif 343 344 /* I2C */ 345 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 346 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 347 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 348 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 349 350 #define I2C_MUX_CH_DEFAULT 0x8 351 #define I2C_MUX_CH_VOL_MONITOR 0xa 352 #define I2C_MUX_CH_VSC3316_FS 0xc 353 #define I2C_MUX_CH_VSC3316_BS 0xd 354 355 /* Voltage monitor on channel 2*/ 356 #define I2C_VOL_MONITOR_ADDR 0x40 357 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 358 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 359 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 360 361 /* VSC Crossbar switches */ 362 #define CONFIG_VSC_CROSSBAR 363 #define VSC3316_FSM_TX_ADDR 0x70 364 #define VSC3316_FSM_RX_ADDR 0x71 365 366 /* 367 * RapidIO 368 */ 369 370 /* 371 * for slave u-boot IMAGE instored in master memory space, 372 * PHYS must be aligned based on the SIZE 373 */ 374 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 375 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 376 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 377 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 378 /* 379 * for slave UCODE and ENV instored in master memory space, 380 * PHYS must be aligned based on the SIZE 381 */ 382 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 383 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 384 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 385 386 /* slave core release by master*/ 387 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 388 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 389 390 /* 391 * SRIO_PCIE_BOOT - SLAVE 392 */ 393 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 394 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 395 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 396 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 397 #endif 398 /* 399 * eSPI - Enhanced SPI 400 */ 401 #define CONFIG_SF_DEFAULT_SPEED 10000000 402 #define CONFIG_SF_DEFAULT_MODE 0 403 404 /* Qman/Bman */ 405 #ifndef CONFIG_NOBQFMAN 406 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 407 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 408 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 409 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 410 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 411 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 412 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 413 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 414 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 415 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 416 CONFIG_SYS_BMAN_CENA_SIZE) 417 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 418 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 419 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 420 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 421 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 422 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 423 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 424 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 425 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 426 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 427 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 428 CONFIG_SYS_QMAN_CENA_SIZE) 429 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 430 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 431 432 #define CONFIG_SYS_DPAA_FMAN 433 #define CONFIG_SYS_DPAA_PME 434 #define CONFIG_SYS_PMAN 435 #define CONFIG_SYS_DPAA_DCE 436 #define CONFIG_SYS_DPAA_RMAN 437 #define CONFIG_SYS_INTERLAKEN 438 439 /* Default address of microcode for the Linux Fman driver */ 440 #if defined(CONFIG_SPIFLASH) 441 /* 442 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 443 * env, so we got 0x110000. 444 */ 445 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 446 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 447 #elif defined(CONFIG_SDCARD) 448 /* 449 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 450 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 451 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 452 */ 453 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 454 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 455 #elif defined(CONFIG_NAND) 456 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 457 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 458 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 459 /* 460 * Slave has no ucode locally, it can fetch this from remote. When implementing 461 * in two corenet boards, slave's ucode could be stored in master's memory 462 * space, the address can be mapped from slave TLB->slave LAW-> 463 * slave SRIO or PCIE outbound window->master inbound window-> 464 * master LAW->the ucode address in master's memory space. 465 */ 466 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 467 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 468 #else 469 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 470 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 471 #endif 472 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 473 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 474 #endif /* CONFIG_NOBQFMAN */ 475 476 #ifdef CONFIG_SYS_DPAA_FMAN 477 #define CONFIG_FMAN_ENET 478 #define CONFIG_PHYLIB_10G 479 #define CONFIG_PHY_VITESSE 480 #define CONFIG_PHY_TERANETICS 481 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 482 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 483 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 484 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 485 #define FM1_10GEC1_PHY_ADDR 0x0 486 #define FM1_10GEC2_PHY_ADDR 0x1 487 #define FM2_10GEC1_PHY_ADDR 0x2 488 #define FM2_10GEC2_PHY_ADDR 0x3 489 #endif 490 491 /* SATA */ 492 #ifdef CONFIG_FSL_SATA_V2 493 #define CONFIG_LIBATA 494 #define CONFIG_FSL_SATA 495 496 #define CONFIG_SYS_SATA_MAX_DEVICE 2 497 #define CONFIG_SATA1 498 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 499 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 500 #define CONFIG_SATA2 501 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 502 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 503 504 #define CONFIG_LBA48 505 #define CONFIG_CMD_SATA 506 #define CONFIG_DOS_PARTITION 507 #endif 508 509 #ifdef CONFIG_FMAN_ENET 510 #define CONFIG_MII /* MII PHY management */ 511 #define CONFIG_ETHPRIME "FM1@DTSEC1" 512 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 513 #endif 514 515 /* Hash command with SHA acceleration supported in hardware */ 516 #ifdef CONFIG_FSL_CAAM 517 #define CONFIG_CMD_HASH 518 #define CONFIG_SHA_HW_ACCEL 519 #endif 520 521 /* 522 * USB 523 */ 524 #define CONFIG_USB_EHCI 525 #define CONFIG_USB_EHCI_FSL 526 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 527 #define CONFIG_HAS_FSL_DR_USB 528 529 #define CONFIG_MMC 530 531 #ifdef CONFIG_MMC 532 #define CONFIG_FSL_ESDHC 533 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 534 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 535 #define CONFIG_GENERIC_MMC 536 #define CONFIG_DOS_PARTITION 537 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 538 #define CONFIG_ESDHC_DETECT_QUIRK \ 539 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ 540 IS_SVR_REV(get_svr(), 1, 0)) 541 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ 542 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) 543 #endif 544 545 546 #define __USB_PHY_TYPE utmi 547 548 /* 549 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 550 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 551 * interleaving. It can be cacheline, page, bank, superbank. 552 * See doc/README.fsl-ddr for details. 553 */ 554 #ifdef CONFIG_PPC_T4240 555 #define CTRL_INTLV_PREFERED 3way_4KB 556 #else 557 #define CTRL_INTLV_PREFERED cacheline 558 #endif 559 560 #define CONFIG_EXTRA_ENV_SETTINGS \ 561 "hwconfig=fsl_ddr:" \ 562 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 563 "bank_intlv=auto;" \ 564 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 565 "netdev=eth0\0" \ 566 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 567 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 568 "tftpflash=tftpboot $loadaddr $uboot && " \ 569 "protect off $ubootaddr +$filesize && " \ 570 "erase $ubootaddr +$filesize && " \ 571 "cp.b $loadaddr $ubootaddr $filesize && " \ 572 "protect on $ubootaddr +$filesize && " \ 573 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 574 "consoledev=ttyS0\0" \ 575 "ramdiskaddr=2000000\0" \ 576 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 577 "fdtaddr=1e00000\0" \ 578 "fdtfile=t4240qds/t4240qds.dtb\0" \ 579 "bdev=sda3\0" 580 581 #define CONFIG_HVBOOT \ 582 "setenv bootargs config-addr=0x60000000; " \ 583 "bootm 0x01000000 - 0x00f00000" 584 585 #define CONFIG_ALU \ 586 "setenv bootargs root=/dev/$bdev rw " \ 587 "console=$consoledev,$baudrate $othbootargs;" \ 588 "cpu 1 release 0x01000000 - - -;" \ 589 "cpu 2 release 0x01000000 - - -;" \ 590 "cpu 3 release 0x01000000 - - -;" \ 591 "cpu 4 release 0x01000000 - - -;" \ 592 "cpu 5 release 0x01000000 - - -;" \ 593 "cpu 6 release 0x01000000 - - -;" \ 594 "cpu 7 release 0x01000000 - - -;" \ 595 "go 0x01000000" 596 597 #define CONFIG_LINUX \ 598 "setenv bootargs root=/dev/ram rw " \ 599 "console=$consoledev,$baudrate $othbootargs;" \ 600 "setenv ramdiskaddr 0x02000000;" \ 601 "setenv fdtaddr 0x00c00000;" \ 602 "setenv loadaddr 0x1000000;" \ 603 "bootm $loadaddr $ramdiskaddr $fdtaddr" 604 605 #define CONFIG_HDBOOT \ 606 "setenv bootargs root=/dev/$bdev rw " \ 607 "console=$consoledev,$baudrate $othbootargs;" \ 608 "tftp $loadaddr $bootfile;" \ 609 "tftp $fdtaddr $fdtfile;" \ 610 "bootm $loadaddr - $fdtaddr" 611 612 #define CONFIG_NFSBOOTCOMMAND \ 613 "setenv bootargs root=/dev/nfs rw " \ 614 "nfsroot=$serverip:$rootpath " \ 615 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 616 "console=$consoledev,$baudrate $othbootargs;" \ 617 "tftp $loadaddr $bootfile;" \ 618 "tftp $fdtaddr $fdtfile;" \ 619 "bootm $loadaddr - $fdtaddr" 620 621 #define CONFIG_RAMBOOTCOMMAND \ 622 "setenv bootargs root=/dev/ram rw " \ 623 "console=$consoledev,$baudrate $othbootargs;" \ 624 "tftp $ramdiskaddr $ramdiskfile;" \ 625 "tftp $loadaddr $bootfile;" \ 626 "tftp $fdtaddr $fdtfile;" \ 627 "bootm $loadaddr $ramdiskaddr $fdtaddr" 628 629 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 630 631 #include <asm/fsl_secure_boot.h> 632 633 #endif /* __CONFIG_H */ 634