1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 QDS board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240QDS 14 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_PCIE4 17 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 18 19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg 23 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg 24 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) 25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #else 28 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 29 #define CONFIG_SPL_SERIAL_SUPPORT 30 #define CONFIG_SPL_FLUSH_IMAGE 31 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 32 #define CONFIG_SPL_LIBGENERIC_SUPPORT 33 #define CONFIG_SPL_LIBCOMMON_SUPPORT 34 #define CONFIG_SPL_I2C_SUPPORT 35 #define CONFIG_FSL_LAW /* Use common FSL init code */ 36 #define CONFIG_SYS_TEXT_BASE 0x00201000 37 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 38 #define CONFIG_SPL_PAD_TO 0x40000 39 #define CONFIG_SPL_MAX_SIZE 0x28000 40 #define RESET_VECTOR_OFFSET 0x27FFC 41 #define BOOT_PAGE_OFFSET 0x27000 42 43 #ifdef CONFIG_NAND 44 #define CONFIG_SPL_NAND_SUPPORT 45 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 46 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 47 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 48 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 50 #define CONFIG_SPL_NAND_BOOT 51 #endif 52 53 #ifdef CONFIG_SDCARD 54 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 55 #define CONFIG_SPL_MMC_SUPPORT 56 #define CONFIG_SPL_MMC_MINIMAL 57 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 58 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 59 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 60 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 61 #ifndef CONFIG_SPL_BUILD 62 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 63 #endif 64 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 65 #define CONFIG_SPL_MMC_BOOT 66 #endif 67 68 #ifdef CONFIG_SPL_BUILD 69 #define CONFIG_SPL_SKIP_RELOCATE 70 #define CONFIG_SPL_COMMON_INIT_DDR 71 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 72 #define CONFIG_SYS_NO_FLASH 73 #endif 74 75 #endif 76 #endif /* CONFIG_RAMBOOT_PBL */ 77 78 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 79 /* Set 1M boot space */ 80 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 81 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 82 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 83 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 84 #define CONFIG_SYS_NO_FLASH 85 #endif 86 87 #define CONFIG_SRIO_PCIE_BOOT_MASTER 88 #define CONFIG_DDR_ECC 89 90 #include "t4qds.h" 91 92 #ifdef CONFIG_SYS_NO_FLASH 93 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 94 #define CONFIG_ENV_IS_NOWHERE 95 #endif 96 #else 97 #define CONFIG_FLASH_CFI_DRIVER 98 #define CONFIG_SYS_FLASH_CFI 99 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 100 #endif 101 102 #if defined(CONFIG_SPIFLASH) 103 #define CONFIG_SYS_EXTRA_ENV_RELOC 104 #define CONFIG_ENV_IS_IN_SPI_FLASH 105 #define CONFIG_ENV_SPI_BUS 0 106 #define CONFIG_ENV_SPI_CS 0 107 #define CONFIG_ENV_SPI_MAX_HZ 10000000 108 #define CONFIG_ENV_SPI_MODE 0 109 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 110 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 111 #define CONFIG_ENV_SECT_SIZE 0x10000 112 #elif defined(CONFIG_SDCARD) 113 #define CONFIG_SYS_EXTRA_ENV_RELOC 114 #define CONFIG_ENV_IS_IN_MMC 115 #define CONFIG_SYS_MMC_ENV_DEV 0 116 #define CONFIG_ENV_SIZE 0x2000 117 #define CONFIG_ENV_OFFSET (512 * 0x800) 118 #elif defined(CONFIG_NAND) 119 #define CONFIG_SYS_EXTRA_ENV_RELOC 120 #define CONFIG_ENV_IS_IN_NAND 121 #define CONFIG_ENV_SIZE 0x2000 122 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 123 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 124 #define CONFIG_ENV_IS_IN_REMOTE 125 #define CONFIG_ENV_ADDR 0xffe20000 126 #define CONFIG_ENV_SIZE 0x2000 127 #elif defined(CONFIG_ENV_IS_NOWHERE) 128 #define CONFIG_ENV_SIZE 0x2000 129 #else 130 #define CONFIG_ENV_IS_IN_FLASH 131 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 132 #define CONFIG_ENV_SIZE 0x2000 133 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 134 #endif 135 136 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 137 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 138 139 #ifndef __ASSEMBLY__ 140 unsigned long get_board_sys_clk(void); 141 unsigned long get_board_ddr_clk(void); 142 #endif 143 144 /* EEPROM */ 145 #define CONFIG_ID_EEPROM 146 #define CONFIG_SYS_I2C_EEPROM_NXID 147 #define CONFIG_SYS_EEPROM_BUS_NUM 0 148 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 149 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 150 151 /* 152 * DDR Setup 153 */ 154 #define CONFIG_SYS_SPD_BUS_NUM 0 155 #define SPD_EEPROM_ADDRESS1 0x51 156 #define SPD_EEPROM_ADDRESS2 0x52 157 #define SPD_EEPROM_ADDRESS3 0x53 158 #define SPD_EEPROM_ADDRESS4 0x54 159 #define SPD_EEPROM_ADDRESS5 0x55 160 #define SPD_EEPROM_ADDRESS6 0x56 161 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 162 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 163 164 /* 165 * IFC Definitions 166 */ 167 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 168 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 169 + 0x8000000) | \ 170 CSPR_PORT_SIZE_16 | \ 171 CSPR_MSEL_NOR | \ 172 CSPR_V) 173 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 174 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 175 CSPR_PORT_SIZE_16 | \ 176 CSPR_MSEL_NOR | \ 177 CSPR_V) 178 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 179 /* NOR Flash Timing Params */ 180 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 181 182 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 183 FTIM0_NOR_TEADC(0x5) | \ 184 FTIM0_NOR_TEAHC(0x5)) 185 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 186 FTIM1_NOR_TRAD_NOR(0x1A) |\ 187 FTIM1_NOR_TSEQRAD_NOR(0x13)) 188 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 189 FTIM2_NOR_TCH(0x4) | \ 190 FTIM2_NOR_TWPH(0x0E) | \ 191 FTIM2_NOR_TWP(0x1c)) 192 #define CONFIG_SYS_NOR_FTIM3 0x0 193 194 #define CONFIG_SYS_FLASH_QUIET_TEST 195 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 196 197 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 198 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 199 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 200 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 201 202 #define CONFIG_SYS_FLASH_EMPTY_INFO 203 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 204 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 205 206 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 207 #define QIXIS_BASE 0xffdf0000 208 #define QIXIS_LBMAP_SWITCH 6 209 #define QIXIS_LBMAP_MASK 0x0f 210 #define QIXIS_LBMAP_SHIFT 0 211 #define QIXIS_LBMAP_DFLTBANK 0x00 212 #define QIXIS_LBMAP_ALTBANK 0x04 213 #define QIXIS_RST_CTL_RESET 0x83 214 #define QIXIS_RST_FORCE_MEM 0x1 215 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 216 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 217 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 218 #define QIXIS_BRDCFG5 0x55 219 #define QIXIS_MUX_SDHC 2 220 #define QIXIS_MUX_SDHC_WIDTH8 1 221 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 222 223 #define CONFIG_SYS_CSPR3_EXT (0xf) 224 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 225 | CSPR_PORT_SIZE_8 \ 226 | CSPR_MSEL_GPCM \ 227 | CSPR_V) 228 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 229 #define CONFIG_SYS_CSOR3 0x0 230 /* QIXIS Timing parameters for IFC CS3 */ 231 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 232 FTIM0_GPCM_TEADC(0x0e) | \ 233 FTIM0_GPCM_TEAHC(0x0e)) 234 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 235 FTIM1_GPCM_TRAD(0x3f)) 236 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 237 FTIM2_GPCM_TCH(0x8) | \ 238 FTIM2_GPCM_TWP(0x1f)) 239 #define CONFIG_SYS_CS3_FTIM3 0x0 240 241 /* NAND Flash on IFC */ 242 #define CONFIG_NAND_FSL_IFC 243 #define CONFIG_SYS_NAND_BASE 0xff800000 244 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 245 246 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 247 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 248 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 249 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 250 | CSPR_V) 251 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 252 253 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 254 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 255 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 256 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 257 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 258 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 259 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 260 261 #define CONFIG_SYS_NAND_ONFI_DETECTION 262 263 /* ONFI NAND Flash mode0 Timing Params */ 264 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 265 FTIM0_NAND_TWP(0x18) | \ 266 FTIM0_NAND_TWCHT(0x07) | \ 267 FTIM0_NAND_TWH(0x0a)) 268 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 269 FTIM1_NAND_TWBE(0x39) | \ 270 FTIM1_NAND_TRR(0x0e) | \ 271 FTIM1_NAND_TRP(0x18)) 272 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 273 FTIM2_NAND_TREH(0x0a) | \ 274 FTIM2_NAND_TWHRE(0x1e)) 275 #define CONFIG_SYS_NAND_FTIM3 0x0 276 277 #define CONFIG_SYS_NAND_DDR_LAW 11 278 279 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 280 #define CONFIG_SYS_MAX_NAND_DEVICE 1 281 #define CONFIG_CMD_NAND 282 283 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 284 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 285 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 286 287 #if defined(CONFIG_NAND) 288 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 289 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 290 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 291 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 292 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 293 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 294 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 295 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 296 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 297 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 298 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 299 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 300 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 301 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 302 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 303 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 304 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 305 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 306 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 307 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 308 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 309 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 310 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 311 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 312 #else 313 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 314 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 315 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 316 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 317 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 318 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 319 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 320 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 321 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 322 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 323 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 324 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 325 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 326 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 327 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 328 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 329 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 330 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 331 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 332 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 333 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 334 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 335 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 336 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 337 #endif 338 339 #if defined(CONFIG_RAMBOOT_PBL) 340 #define CONFIG_SYS_RAMBOOT 341 #endif 342 343 /* I2C */ 344 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 345 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 346 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 347 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 348 349 #define I2C_MUX_CH_DEFAULT 0x8 350 #define I2C_MUX_CH_VOL_MONITOR 0xa 351 #define I2C_MUX_CH_VSC3316_FS 0xc 352 #define I2C_MUX_CH_VSC3316_BS 0xd 353 354 /* Voltage monitor on channel 2*/ 355 #define I2C_VOL_MONITOR_ADDR 0x40 356 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 357 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 358 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 359 360 /* VSC Crossbar switches */ 361 #define CONFIG_VSC_CROSSBAR 362 #define VSC3316_FSM_TX_ADDR 0x70 363 #define VSC3316_FSM_RX_ADDR 0x71 364 365 /* 366 * RapidIO 367 */ 368 369 /* 370 * for slave u-boot IMAGE instored in master memory space, 371 * PHYS must be aligned based on the SIZE 372 */ 373 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 374 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 375 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 376 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 377 /* 378 * for slave UCODE and ENV instored in master memory space, 379 * PHYS must be aligned based on the SIZE 380 */ 381 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 382 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 383 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 384 385 /* slave core release by master*/ 386 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 387 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 388 389 /* 390 * SRIO_PCIE_BOOT - SLAVE 391 */ 392 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 393 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 394 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 395 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 396 #endif 397 /* 398 * eSPI - Enhanced SPI 399 */ 400 #define CONFIG_SF_DEFAULT_SPEED 10000000 401 #define CONFIG_SF_DEFAULT_MODE 0 402 403 /* Qman/Bman */ 404 #ifndef CONFIG_NOBQFMAN 405 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 406 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 407 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 408 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 409 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 410 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 411 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 412 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 413 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 414 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 415 CONFIG_SYS_BMAN_CENA_SIZE) 416 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 417 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 418 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 419 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 420 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 421 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 422 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 423 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 424 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 425 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 426 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 427 CONFIG_SYS_QMAN_CENA_SIZE) 428 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 429 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 430 431 #define CONFIG_SYS_DPAA_FMAN 432 #define CONFIG_SYS_DPAA_PME 433 #define CONFIG_SYS_PMAN 434 #define CONFIG_SYS_DPAA_DCE 435 #define CONFIG_SYS_DPAA_RMAN 436 #define CONFIG_SYS_INTERLAKEN 437 438 /* Default address of microcode for the Linux Fman driver */ 439 #if defined(CONFIG_SPIFLASH) 440 /* 441 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 442 * env, so we got 0x110000. 443 */ 444 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 445 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 446 #elif defined(CONFIG_SDCARD) 447 /* 448 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 449 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 450 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 451 */ 452 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 453 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 454 #elif defined(CONFIG_NAND) 455 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 456 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 457 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 458 /* 459 * Slave has no ucode locally, it can fetch this from remote. When implementing 460 * in two corenet boards, slave's ucode could be stored in master's memory 461 * space, the address can be mapped from slave TLB->slave LAW-> 462 * slave SRIO or PCIE outbound window->master inbound window-> 463 * master LAW->the ucode address in master's memory space. 464 */ 465 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 466 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 467 #else 468 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 469 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 470 #endif 471 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 472 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 473 #endif /* CONFIG_NOBQFMAN */ 474 475 #ifdef CONFIG_SYS_DPAA_FMAN 476 #define CONFIG_FMAN_ENET 477 #define CONFIG_PHYLIB_10G 478 #define CONFIG_PHY_VITESSE 479 #define CONFIG_PHY_TERANETICS 480 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 481 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 482 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 483 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 484 #define FM1_10GEC1_PHY_ADDR 0x0 485 #define FM1_10GEC2_PHY_ADDR 0x1 486 #define FM2_10GEC1_PHY_ADDR 0x2 487 #define FM2_10GEC2_PHY_ADDR 0x3 488 #endif 489 490 /* SATA */ 491 #ifdef CONFIG_FSL_SATA_V2 492 #define CONFIG_LIBATA 493 #define CONFIG_FSL_SATA 494 495 #define CONFIG_SYS_SATA_MAX_DEVICE 2 496 #define CONFIG_SATA1 497 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 498 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 499 #define CONFIG_SATA2 500 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 501 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 502 503 #define CONFIG_LBA48 504 #define CONFIG_CMD_SATA 505 #define CONFIG_DOS_PARTITION 506 #endif 507 508 #ifdef CONFIG_FMAN_ENET 509 #define CONFIG_MII /* MII PHY management */ 510 #define CONFIG_ETHPRIME "FM1@DTSEC1" 511 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 512 #endif 513 514 /* Hash command with SHA acceleration supported in hardware */ 515 #ifdef CONFIG_FSL_CAAM 516 #define CONFIG_CMD_HASH 517 #define CONFIG_SHA_HW_ACCEL 518 #endif 519 520 /* 521 * USB 522 */ 523 #define CONFIG_USB_EHCI 524 #define CONFIG_USB_EHCI_FSL 525 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 526 #define CONFIG_HAS_FSL_DR_USB 527 528 #define CONFIG_MMC 529 530 #ifdef CONFIG_MMC 531 #define CONFIG_FSL_ESDHC 532 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 533 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 534 #define CONFIG_GENERIC_MMC 535 #define CONFIG_DOS_PARTITION 536 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 537 #define CONFIG_ESDHC_DETECT_QUIRK \ 538 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ 539 IS_SVR_REV(get_svr(), 1, 0)) 540 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ 541 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) 542 #endif 543 544 545 #define __USB_PHY_TYPE utmi 546 547 /* 548 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 549 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 550 * interleaving. It can be cacheline, page, bank, superbank. 551 * See doc/README.fsl-ddr for details. 552 */ 553 #ifdef CONFIG_PPC_T4240 554 #define CTRL_INTLV_PREFERED 3way_4KB 555 #else 556 #define CTRL_INTLV_PREFERED cacheline 557 #endif 558 559 #define CONFIG_EXTRA_ENV_SETTINGS \ 560 "hwconfig=fsl_ddr:" \ 561 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 562 "bank_intlv=auto;" \ 563 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 564 "netdev=eth0\0" \ 565 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 566 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 567 "tftpflash=tftpboot $loadaddr $uboot && " \ 568 "protect off $ubootaddr +$filesize && " \ 569 "erase $ubootaddr +$filesize && " \ 570 "cp.b $loadaddr $ubootaddr $filesize && " \ 571 "protect on $ubootaddr +$filesize && " \ 572 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 573 "consoledev=ttyS0\0" \ 574 "ramdiskaddr=2000000\0" \ 575 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 576 "fdtaddr=1e00000\0" \ 577 "fdtfile=t4240qds/t4240qds.dtb\0" \ 578 "bdev=sda3\0" 579 580 #define CONFIG_HVBOOT \ 581 "setenv bootargs config-addr=0x60000000; " \ 582 "bootm 0x01000000 - 0x00f00000" 583 584 #define CONFIG_ALU \ 585 "setenv bootargs root=/dev/$bdev rw " \ 586 "console=$consoledev,$baudrate $othbootargs;" \ 587 "cpu 1 release 0x01000000 - - -;" \ 588 "cpu 2 release 0x01000000 - - -;" \ 589 "cpu 3 release 0x01000000 - - -;" \ 590 "cpu 4 release 0x01000000 - - -;" \ 591 "cpu 5 release 0x01000000 - - -;" \ 592 "cpu 6 release 0x01000000 - - -;" \ 593 "cpu 7 release 0x01000000 - - -;" \ 594 "go 0x01000000" 595 596 #define CONFIG_LINUX \ 597 "setenv bootargs root=/dev/ram rw " \ 598 "console=$consoledev,$baudrate $othbootargs;" \ 599 "setenv ramdiskaddr 0x02000000;" \ 600 "setenv fdtaddr 0x00c00000;" \ 601 "setenv loadaddr 0x1000000;" \ 602 "bootm $loadaddr $ramdiskaddr $fdtaddr" 603 604 #define CONFIG_HDBOOT \ 605 "setenv bootargs root=/dev/$bdev rw " \ 606 "console=$consoledev,$baudrate $othbootargs;" \ 607 "tftp $loadaddr $bootfile;" \ 608 "tftp $fdtaddr $fdtfile;" \ 609 "bootm $loadaddr - $fdtaddr" 610 611 #define CONFIG_NFSBOOTCOMMAND \ 612 "setenv bootargs root=/dev/nfs rw " \ 613 "nfsroot=$serverip:$rootpath " \ 614 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 615 "console=$consoledev,$baudrate $othbootargs;" \ 616 "tftp $loadaddr $bootfile;" \ 617 "tftp $fdtaddr $fdtfile;" \ 618 "bootm $loadaddr - $fdtaddr" 619 620 #define CONFIG_RAMBOOTCOMMAND \ 621 "setenv bootargs root=/dev/ram rw " \ 622 "console=$consoledev,$baudrate $othbootargs;" \ 623 "tftp $ramdiskaddr $ramdiskfile;" \ 624 "tftp $loadaddr $bootfile;" \ 625 "tftp $fdtaddr $fdtfile;" \ 626 "bootm $loadaddr $ramdiskaddr $fdtaddr" 627 628 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 629 630 #include <asm/fsl_secure_boot.h> 631 632 #endif /* __CONFIG_H */ 633