1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 QDS board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240QDS 14 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_PCIE4 17 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 18 19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg 23 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg 24 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) 25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #else 28 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 29 #define CONFIG_SPL_SERIAL_SUPPORT 30 #define CONFIG_SPL_FLUSH_IMAGE 31 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 32 #define CONFIG_SPL_LIBGENERIC_SUPPORT 33 #define CONFIG_SPL_LIBCOMMON_SUPPORT 34 #define CONFIG_FSL_LAW /* Use common FSL init code */ 35 #define CONFIG_SYS_TEXT_BASE 0x00201000 36 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 37 #define CONFIG_SPL_PAD_TO 0x40000 38 #define CONFIG_SPL_MAX_SIZE 0x28000 39 #define RESET_VECTOR_OFFSET 0x27FFC 40 #define BOOT_PAGE_OFFSET 0x27000 41 42 #ifdef CONFIG_NAND 43 #define CONFIG_SPL_NAND_SUPPORT 44 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 45 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 46 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 47 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 48 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 49 #define CONFIG_SPL_NAND_BOOT 50 #endif 51 52 #ifdef CONFIG_SDCARD 53 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 54 #define CONFIG_SPL_MMC_SUPPORT 55 #define CONFIG_SPL_MMC_MINIMAL 56 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 57 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 58 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 59 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 60 #ifndef CONFIG_SPL_BUILD 61 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 62 #endif 63 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 64 #define CONFIG_SPL_MMC_BOOT 65 #endif 66 67 #ifdef CONFIG_SPL_BUILD 68 #define CONFIG_SPL_SKIP_RELOCATE 69 #define CONFIG_SPL_COMMON_INIT_DDR 70 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 71 #define CONFIG_SYS_NO_FLASH 72 #endif 73 74 #endif 75 #endif /* CONFIG_RAMBOOT_PBL */ 76 77 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 78 /* Set 1M boot space */ 79 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 80 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 81 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 82 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 83 #define CONFIG_SYS_NO_FLASH 84 #endif 85 86 #define CONFIG_SRIO_PCIE_BOOT_MASTER 87 #define CONFIG_DDR_ECC 88 89 #include "t4qds.h" 90 91 #ifdef CONFIG_SYS_NO_FLASH 92 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 93 #define CONFIG_ENV_IS_NOWHERE 94 #endif 95 #else 96 #define CONFIG_FLASH_CFI_DRIVER 97 #define CONFIG_SYS_FLASH_CFI 98 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 99 #endif 100 101 #if defined(CONFIG_SPIFLASH) 102 #define CONFIG_SYS_EXTRA_ENV_RELOC 103 #define CONFIG_ENV_IS_IN_SPI_FLASH 104 #define CONFIG_ENV_SPI_BUS 0 105 #define CONFIG_ENV_SPI_CS 0 106 #define CONFIG_ENV_SPI_MAX_HZ 10000000 107 #define CONFIG_ENV_SPI_MODE 0 108 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 109 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 110 #define CONFIG_ENV_SECT_SIZE 0x10000 111 #elif defined(CONFIG_SDCARD) 112 #define CONFIG_SYS_EXTRA_ENV_RELOC 113 #define CONFIG_ENV_IS_IN_MMC 114 #define CONFIG_SYS_MMC_ENV_DEV 0 115 #define CONFIG_ENV_SIZE 0x2000 116 #define CONFIG_ENV_OFFSET (512 * 0x800) 117 #elif defined(CONFIG_NAND) 118 #define CONFIG_SYS_EXTRA_ENV_RELOC 119 #define CONFIG_ENV_IS_IN_NAND 120 #define CONFIG_ENV_SIZE 0x2000 121 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 122 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 123 #define CONFIG_ENV_IS_IN_REMOTE 124 #define CONFIG_ENV_ADDR 0xffe20000 125 #define CONFIG_ENV_SIZE 0x2000 126 #elif defined(CONFIG_ENV_IS_NOWHERE) 127 #define CONFIG_ENV_SIZE 0x2000 128 #else 129 #define CONFIG_ENV_IS_IN_FLASH 130 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 131 #define CONFIG_ENV_SIZE 0x2000 132 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 133 #endif 134 135 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 136 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 137 138 #ifndef __ASSEMBLY__ 139 unsigned long get_board_sys_clk(void); 140 unsigned long get_board_ddr_clk(void); 141 #endif 142 143 /* EEPROM */ 144 #define CONFIG_ID_EEPROM 145 #define CONFIG_SYS_I2C_EEPROM_NXID 146 #define CONFIG_SYS_EEPROM_BUS_NUM 0 147 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 148 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 149 150 /* 151 * DDR Setup 152 */ 153 #define CONFIG_SYS_SPD_BUS_NUM 0 154 #define SPD_EEPROM_ADDRESS1 0x51 155 #define SPD_EEPROM_ADDRESS2 0x52 156 #define SPD_EEPROM_ADDRESS3 0x53 157 #define SPD_EEPROM_ADDRESS4 0x54 158 #define SPD_EEPROM_ADDRESS5 0x55 159 #define SPD_EEPROM_ADDRESS6 0x56 160 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 161 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 162 163 /* 164 * IFC Definitions 165 */ 166 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 167 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 168 + 0x8000000) | \ 169 CSPR_PORT_SIZE_16 | \ 170 CSPR_MSEL_NOR | \ 171 CSPR_V) 172 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 173 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 174 CSPR_PORT_SIZE_16 | \ 175 CSPR_MSEL_NOR | \ 176 CSPR_V) 177 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 178 /* NOR Flash Timing Params */ 179 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 180 181 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 182 FTIM0_NOR_TEADC(0x5) | \ 183 FTIM0_NOR_TEAHC(0x5)) 184 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 185 FTIM1_NOR_TRAD_NOR(0x1A) |\ 186 FTIM1_NOR_TSEQRAD_NOR(0x13)) 187 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 188 FTIM2_NOR_TCH(0x4) | \ 189 FTIM2_NOR_TWPH(0x0E) | \ 190 FTIM2_NOR_TWP(0x1c)) 191 #define CONFIG_SYS_NOR_FTIM3 0x0 192 193 #define CONFIG_SYS_FLASH_QUIET_TEST 194 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 195 196 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 197 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 198 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 199 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 200 201 #define CONFIG_SYS_FLASH_EMPTY_INFO 202 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 203 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 204 205 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 206 #define QIXIS_BASE 0xffdf0000 207 #define QIXIS_LBMAP_SWITCH 6 208 #define QIXIS_LBMAP_MASK 0x0f 209 #define QIXIS_LBMAP_SHIFT 0 210 #define QIXIS_LBMAP_DFLTBANK 0x00 211 #define QIXIS_LBMAP_ALTBANK 0x04 212 #define QIXIS_RST_CTL_RESET 0x83 213 #define QIXIS_RST_FORCE_MEM 0x1 214 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 215 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 216 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 217 #define QIXIS_BRDCFG5 0x55 218 #define QIXIS_MUX_SDHC 2 219 #define QIXIS_MUX_SDHC_WIDTH8 1 220 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 221 222 #define CONFIG_SYS_CSPR3_EXT (0xf) 223 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 224 | CSPR_PORT_SIZE_8 \ 225 | CSPR_MSEL_GPCM \ 226 | CSPR_V) 227 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 228 #define CONFIG_SYS_CSOR3 0x0 229 /* QIXIS Timing parameters for IFC CS3 */ 230 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 231 FTIM0_GPCM_TEADC(0x0e) | \ 232 FTIM0_GPCM_TEAHC(0x0e)) 233 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 234 FTIM1_GPCM_TRAD(0x3f)) 235 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 236 FTIM2_GPCM_TCH(0x8) | \ 237 FTIM2_GPCM_TWP(0x1f)) 238 #define CONFIG_SYS_CS3_FTIM3 0x0 239 240 /* NAND Flash on IFC */ 241 #define CONFIG_NAND_FSL_IFC 242 #define CONFIG_SYS_NAND_BASE 0xff800000 243 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 244 245 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 246 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 247 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 248 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 249 | CSPR_V) 250 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 251 252 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 253 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 254 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 255 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 256 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 257 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 258 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 259 260 #define CONFIG_SYS_NAND_ONFI_DETECTION 261 262 /* ONFI NAND Flash mode0 Timing Params */ 263 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 264 FTIM0_NAND_TWP(0x18) | \ 265 FTIM0_NAND_TWCHT(0x07) | \ 266 FTIM0_NAND_TWH(0x0a)) 267 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 268 FTIM1_NAND_TWBE(0x39) | \ 269 FTIM1_NAND_TRR(0x0e) | \ 270 FTIM1_NAND_TRP(0x18)) 271 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 272 FTIM2_NAND_TREH(0x0a) | \ 273 FTIM2_NAND_TWHRE(0x1e)) 274 #define CONFIG_SYS_NAND_FTIM3 0x0 275 276 #define CONFIG_SYS_NAND_DDR_LAW 11 277 278 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 279 #define CONFIG_SYS_MAX_NAND_DEVICE 1 280 #define CONFIG_CMD_NAND 281 282 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 283 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 284 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 285 286 #if defined(CONFIG_NAND) 287 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 288 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 289 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 290 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 291 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 292 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 293 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 294 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 295 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 296 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 297 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 298 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 299 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 300 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 301 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 302 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 303 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 304 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 305 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 306 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 307 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 308 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 309 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 310 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 311 #else 312 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 313 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 314 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 315 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 316 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 317 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 318 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 319 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 320 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 321 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 322 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 323 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 324 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 325 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 326 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 327 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 328 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 329 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 330 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 331 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 332 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 333 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 334 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 335 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 336 #endif 337 338 #if defined(CONFIG_RAMBOOT_PBL) 339 #define CONFIG_SYS_RAMBOOT 340 #endif 341 342 /* I2C */ 343 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 344 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 345 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 346 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 347 348 #define I2C_MUX_CH_DEFAULT 0x8 349 #define I2C_MUX_CH_VOL_MONITOR 0xa 350 #define I2C_MUX_CH_VSC3316_FS 0xc 351 #define I2C_MUX_CH_VSC3316_BS 0xd 352 353 /* Voltage monitor on channel 2*/ 354 #define I2C_VOL_MONITOR_ADDR 0x40 355 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 356 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 357 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 358 359 /* VSC Crossbar switches */ 360 #define CONFIG_VSC_CROSSBAR 361 #define VSC3316_FSM_TX_ADDR 0x70 362 #define VSC3316_FSM_RX_ADDR 0x71 363 364 /* 365 * RapidIO 366 */ 367 368 /* 369 * for slave u-boot IMAGE instored in master memory space, 370 * PHYS must be aligned based on the SIZE 371 */ 372 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 373 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 374 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 375 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 376 /* 377 * for slave UCODE and ENV instored in master memory space, 378 * PHYS must be aligned based on the SIZE 379 */ 380 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 381 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 382 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 383 384 /* slave core release by master*/ 385 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 386 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 387 388 /* 389 * SRIO_PCIE_BOOT - SLAVE 390 */ 391 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 392 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 393 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 394 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 395 #endif 396 /* 397 * eSPI - Enhanced SPI 398 */ 399 #define CONFIG_SF_DEFAULT_SPEED 10000000 400 #define CONFIG_SF_DEFAULT_MODE 0 401 402 /* Qman/Bman */ 403 #ifndef CONFIG_NOBQFMAN 404 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 405 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 406 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 407 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 408 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 409 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 410 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 411 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 412 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 413 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 414 CONFIG_SYS_BMAN_CENA_SIZE) 415 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 416 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 417 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 418 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 419 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 420 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 421 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 422 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 423 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 424 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 425 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 426 CONFIG_SYS_QMAN_CENA_SIZE) 427 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 428 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 429 430 #define CONFIG_SYS_DPAA_FMAN 431 #define CONFIG_SYS_DPAA_PME 432 #define CONFIG_SYS_PMAN 433 #define CONFIG_SYS_DPAA_DCE 434 #define CONFIG_SYS_DPAA_RMAN 435 #define CONFIG_SYS_INTERLAKEN 436 437 /* Default address of microcode for the Linux Fman driver */ 438 #if defined(CONFIG_SPIFLASH) 439 /* 440 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 441 * env, so we got 0x110000. 442 */ 443 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 444 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 445 #elif defined(CONFIG_SDCARD) 446 /* 447 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 448 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 449 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 450 */ 451 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 452 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 453 #elif defined(CONFIG_NAND) 454 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 455 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 456 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 457 /* 458 * Slave has no ucode locally, it can fetch this from remote. When implementing 459 * in two corenet boards, slave's ucode could be stored in master's memory 460 * space, the address can be mapped from slave TLB->slave LAW-> 461 * slave SRIO or PCIE outbound window->master inbound window-> 462 * master LAW->the ucode address in master's memory space. 463 */ 464 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 465 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 466 #else 467 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 468 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 469 #endif 470 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 471 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 472 #endif /* CONFIG_NOBQFMAN */ 473 474 #ifdef CONFIG_SYS_DPAA_FMAN 475 #define CONFIG_FMAN_ENET 476 #define CONFIG_PHYLIB_10G 477 #define CONFIG_PHY_VITESSE 478 #define CONFIG_PHY_TERANETICS 479 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 480 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 481 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 482 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 483 #define FM1_10GEC1_PHY_ADDR 0x0 484 #define FM1_10GEC2_PHY_ADDR 0x1 485 #define FM2_10GEC1_PHY_ADDR 0x2 486 #define FM2_10GEC2_PHY_ADDR 0x3 487 #endif 488 489 /* SATA */ 490 #ifdef CONFIG_FSL_SATA_V2 491 #define CONFIG_LIBATA 492 #define CONFIG_FSL_SATA 493 494 #define CONFIG_SYS_SATA_MAX_DEVICE 2 495 #define CONFIG_SATA1 496 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 497 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 498 #define CONFIG_SATA2 499 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 500 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 501 502 #define CONFIG_LBA48 503 #define CONFIG_CMD_SATA 504 #define CONFIG_DOS_PARTITION 505 #endif 506 507 #ifdef CONFIG_FMAN_ENET 508 #define CONFIG_MII /* MII PHY management */ 509 #define CONFIG_ETHPRIME "FM1@DTSEC1" 510 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 511 #endif 512 513 /* Hash command with SHA acceleration supported in hardware */ 514 #ifdef CONFIG_FSL_CAAM 515 #define CONFIG_CMD_HASH 516 #define CONFIG_SHA_HW_ACCEL 517 #endif 518 519 /* 520 * USB 521 */ 522 #define CONFIG_USB_EHCI 523 #define CONFIG_USB_EHCI_FSL 524 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 525 #define CONFIG_HAS_FSL_DR_USB 526 527 #define CONFIG_MMC 528 529 #ifdef CONFIG_MMC 530 #define CONFIG_FSL_ESDHC 531 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 532 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 533 #define CONFIG_GENERIC_MMC 534 #define CONFIG_DOS_PARTITION 535 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 536 #define CONFIG_ESDHC_DETECT_QUIRK \ 537 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ 538 IS_SVR_REV(get_svr(), 1, 0)) 539 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ 540 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) 541 #endif 542 543 544 #define __USB_PHY_TYPE utmi 545 546 /* 547 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 548 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 549 * interleaving. It can be cacheline, page, bank, superbank. 550 * See doc/README.fsl-ddr for details. 551 */ 552 #ifdef CONFIG_PPC_T4240 553 #define CTRL_INTLV_PREFERED 3way_4KB 554 #else 555 #define CTRL_INTLV_PREFERED cacheline 556 #endif 557 558 #define CONFIG_EXTRA_ENV_SETTINGS \ 559 "hwconfig=fsl_ddr:" \ 560 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 561 "bank_intlv=auto;" \ 562 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 563 "netdev=eth0\0" \ 564 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 565 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 566 "tftpflash=tftpboot $loadaddr $uboot && " \ 567 "protect off $ubootaddr +$filesize && " \ 568 "erase $ubootaddr +$filesize && " \ 569 "cp.b $loadaddr $ubootaddr $filesize && " \ 570 "protect on $ubootaddr +$filesize && " \ 571 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 572 "consoledev=ttyS0\0" \ 573 "ramdiskaddr=2000000\0" \ 574 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 575 "fdtaddr=1e00000\0" \ 576 "fdtfile=t4240qds/t4240qds.dtb\0" \ 577 "bdev=sda3\0" 578 579 #define CONFIG_HVBOOT \ 580 "setenv bootargs config-addr=0x60000000; " \ 581 "bootm 0x01000000 - 0x00f00000" 582 583 #define CONFIG_ALU \ 584 "setenv bootargs root=/dev/$bdev rw " \ 585 "console=$consoledev,$baudrate $othbootargs;" \ 586 "cpu 1 release 0x01000000 - - -;" \ 587 "cpu 2 release 0x01000000 - - -;" \ 588 "cpu 3 release 0x01000000 - - -;" \ 589 "cpu 4 release 0x01000000 - - -;" \ 590 "cpu 5 release 0x01000000 - - -;" \ 591 "cpu 6 release 0x01000000 - - -;" \ 592 "cpu 7 release 0x01000000 - - -;" \ 593 "go 0x01000000" 594 595 #define CONFIG_LINUX \ 596 "setenv bootargs root=/dev/ram rw " \ 597 "console=$consoledev,$baudrate $othbootargs;" \ 598 "setenv ramdiskaddr 0x02000000;" \ 599 "setenv fdtaddr 0x00c00000;" \ 600 "setenv loadaddr 0x1000000;" \ 601 "bootm $loadaddr $ramdiskaddr $fdtaddr" 602 603 #define CONFIG_HDBOOT \ 604 "setenv bootargs root=/dev/$bdev rw " \ 605 "console=$consoledev,$baudrate $othbootargs;" \ 606 "tftp $loadaddr $bootfile;" \ 607 "tftp $fdtaddr $fdtfile;" \ 608 "bootm $loadaddr - $fdtaddr" 609 610 #define CONFIG_NFSBOOTCOMMAND \ 611 "setenv bootargs root=/dev/nfs rw " \ 612 "nfsroot=$serverip:$rootpath " \ 613 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 614 "console=$consoledev,$baudrate $othbootargs;" \ 615 "tftp $loadaddr $bootfile;" \ 616 "tftp $fdtaddr $fdtfile;" \ 617 "bootm $loadaddr - $fdtaddr" 618 619 #define CONFIG_RAMBOOTCOMMAND \ 620 "setenv bootargs root=/dev/ram rw " \ 621 "console=$consoledev,$baudrate $othbootargs;" \ 622 "tftp $ramdiskaddr $ramdiskfile;" \ 623 "tftp $loadaddr $bootfile;" \ 624 "tftp $fdtaddr $fdtfile;" \ 625 "bootm $loadaddr $ramdiskaddr $fdtaddr" 626 627 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 628 629 #include <asm/fsl_secure_boot.h> 630 631 #endif /* __CONFIG_H */ 632