1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 QDS board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240QDS 14 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_PCIE4 17 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 18 19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg 23 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg 24 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) 25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #else 28 #define CONFIG_SPL_SERIAL_SUPPORT 29 #define CONFIG_SPL_FLUSH_IMAGE 30 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 31 #define CONFIG_FSL_LAW /* Use common FSL init code */ 32 #define CONFIG_SYS_TEXT_BASE 0x00201000 33 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 34 #define CONFIG_SPL_PAD_TO 0x40000 35 #define CONFIG_SPL_MAX_SIZE 0x28000 36 #define RESET_VECTOR_OFFSET 0x27FFC 37 #define BOOT_PAGE_OFFSET 0x27000 38 39 #ifdef CONFIG_NAND 40 #define CONFIG_SPL_NAND_SUPPORT 41 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 42 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 43 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 44 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 45 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 46 #define CONFIG_SPL_NAND_BOOT 47 #endif 48 49 #ifdef CONFIG_SDCARD 50 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 51 #define CONFIG_SPL_MMC_MINIMAL 52 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 53 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 54 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 55 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 56 #ifndef CONFIG_SPL_BUILD 57 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 58 #endif 59 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 60 #define CONFIG_SPL_MMC_BOOT 61 #endif 62 63 #ifdef CONFIG_SPL_BUILD 64 #define CONFIG_SPL_SKIP_RELOCATE 65 #define CONFIG_SPL_COMMON_INIT_DDR 66 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 67 #define CONFIG_SYS_NO_FLASH 68 #endif 69 70 #endif 71 #endif /* CONFIG_RAMBOOT_PBL */ 72 73 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 74 /* Set 1M boot space */ 75 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 76 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 77 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 78 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 79 #define CONFIG_SYS_NO_FLASH 80 #endif 81 82 #define CONFIG_SRIO_PCIE_BOOT_MASTER 83 #define CONFIG_DDR_ECC 84 85 #include "t4qds.h" 86 87 #ifdef CONFIG_SYS_NO_FLASH 88 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 89 #define CONFIG_ENV_IS_NOWHERE 90 #endif 91 #else 92 #define CONFIG_FLASH_CFI_DRIVER 93 #define CONFIG_SYS_FLASH_CFI 94 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 95 #endif 96 97 #if defined(CONFIG_SPIFLASH) 98 #define CONFIG_SYS_EXTRA_ENV_RELOC 99 #define CONFIG_ENV_IS_IN_SPI_FLASH 100 #define CONFIG_ENV_SPI_BUS 0 101 #define CONFIG_ENV_SPI_CS 0 102 #define CONFIG_ENV_SPI_MAX_HZ 10000000 103 #define CONFIG_ENV_SPI_MODE 0 104 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 105 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 106 #define CONFIG_ENV_SECT_SIZE 0x10000 107 #elif defined(CONFIG_SDCARD) 108 #define CONFIG_SYS_EXTRA_ENV_RELOC 109 #define CONFIG_ENV_IS_IN_MMC 110 #define CONFIG_SYS_MMC_ENV_DEV 0 111 #define CONFIG_ENV_SIZE 0x2000 112 #define CONFIG_ENV_OFFSET (512 * 0x800) 113 #elif defined(CONFIG_NAND) 114 #define CONFIG_SYS_EXTRA_ENV_RELOC 115 #define CONFIG_ENV_IS_IN_NAND 116 #define CONFIG_ENV_SIZE 0x2000 117 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 118 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 119 #define CONFIG_ENV_IS_IN_REMOTE 120 #define CONFIG_ENV_ADDR 0xffe20000 121 #define CONFIG_ENV_SIZE 0x2000 122 #elif defined(CONFIG_ENV_IS_NOWHERE) 123 #define CONFIG_ENV_SIZE 0x2000 124 #else 125 #define CONFIG_ENV_IS_IN_FLASH 126 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 127 #define CONFIG_ENV_SIZE 0x2000 128 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 129 #endif 130 131 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 132 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 133 134 #ifndef __ASSEMBLY__ 135 unsigned long get_board_sys_clk(void); 136 unsigned long get_board_ddr_clk(void); 137 #endif 138 139 /* EEPROM */ 140 #define CONFIG_ID_EEPROM 141 #define CONFIG_SYS_I2C_EEPROM_NXID 142 #define CONFIG_SYS_EEPROM_BUS_NUM 0 143 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 145 146 /* 147 * DDR Setup 148 */ 149 #define CONFIG_SYS_SPD_BUS_NUM 0 150 #define SPD_EEPROM_ADDRESS1 0x51 151 #define SPD_EEPROM_ADDRESS2 0x52 152 #define SPD_EEPROM_ADDRESS3 0x53 153 #define SPD_EEPROM_ADDRESS4 0x54 154 #define SPD_EEPROM_ADDRESS5 0x55 155 #define SPD_EEPROM_ADDRESS6 0x56 156 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 157 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 158 159 /* 160 * IFC Definitions 161 */ 162 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 163 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 164 + 0x8000000) | \ 165 CSPR_PORT_SIZE_16 | \ 166 CSPR_MSEL_NOR | \ 167 CSPR_V) 168 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 169 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 170 CSPR_PORT_SIZE_16 | \ 171 CSPR_MSEL_NOR | \ 172 CSPR_V) 173 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 174 /* NOR Flash Timing Params */ 175 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 176 177 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 178 FTIM0_NOR_TEADC(0x5) | \ 179 FTIM0_NOR_TEAHC(0x5)) 180 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 181 FTIM1_NOR_TRAD_NOR(0x1A) |\ 182 FTIM1_NOR_TSEQRAD_NOR(0x13)) 183 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 184 FTIM2_NOR_TCH(0x4) | \ 185 FTIM2_NOR_TWPH(0x0E) | \ 186 FTIM2_NOR_TWP(0x1c)) 187 #define CONFIG_SYS_NOR_FTIM3 0x0 188 189 #define CONFIG_SYS_FLASH_QUIET_TEST 190 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 191 192 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 193 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 194 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 195 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 196 197 #define CONFIG_SYS_FLASH_EMPTY_INFO 198 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 199 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 200 201 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 202 #define QIXIS_BASE 0xffdf0000 203 #define QIXIS_LBMAP_SWITCH 6 204 #define QIXIS_LBMAP_MASK 0x0f 205 #define QIXIS_LBMAP_SHIFT 0 206 #define QIXIS_LBMAP_DFLTBANK 0x00 207 #define QIXIS_LBMAP_ALTBANK 0x04 208 #define QIXIS_RST_CTL_RESET 0x83 209 #define QIXIS_RST_FORCE_MEM 0x1 210 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 211 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 212 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 213 #define QIXIS_BRDCFG5 0x55 214 #define QIXIS_MUX_SDHC 2 215 #define QIXIS_MUX_SDHC_WIDTH8 1 216 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 217 218 #define CONFIG_SYS_CSPR3_EXT (0xf) 219 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 220 | CSPR_PORT_SIZE_8 \ 221 | CSPR_MSEL_GPCM \ 222 | CSPR_V) 223 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 224 #define CONFIG_SYS_CSOR3 0x0 225 /* QIXIS Timing parameters for IFC CS3 */ 226 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 227 FTIM0_GPCM_TEADC(0x0e) | \ 228 FTIM0_GPCM_TEAHC(0x0e)) 229 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 230 FTIM1_GPCM_TRAD(0x3f)) 231 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 232 FTIM2_GPCM_TCH(0x8) | \ 233 FTIM2_GPCM_TWP(0x1f)) 234 #define CONFIG_SYS_CS3_FTIM3 0x0 235 236 /* NAND Flash on IFC */ 237 #define CONFIG_NAND_FSL_IFC 238 #define CONFIG_SYS_NAND_BASE 0xff800000 239 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 240 241 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 242 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 243 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 244 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 245 | CSPR_V) 246 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 247 248 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 249 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 250 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 251 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 252 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 253 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 254 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 255 256 #define CONFIG_SYS_NAND_ONFI_DETECTION 257 258 /* ONFI NAND Flash mode0 Timing Params */ 259 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 260 FTIM0_NAND_TWP(0x18) | \ 261 FTIM0_NAND_TWCHT(0x07) | \ 262 FTIM0_NAND_TWH(0x0a)) 263 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 264 FTIM1_NAND_TWBE(0x39) | \ 265 FTIM1_NAND_TRR(0x0e) | \ 266 FTIM1_NAND_TRP(0x18)) 267 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 268 FTIM2_NAND_TREH(0x0a) | \ 269 FTIM2_NAND_TWHRE(0x1e)) 270 #define CONFIG_SYS_NAND_FTIM3 0x0 271 272 #define CONFIG_SYS_NAND_DDR_LAW 11 273 274 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 275 #define CONFIG_SYS_MAX_NAND_DEVICE 1 276 #define CONFIG_CMD_NAND 277 278 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 279 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 280 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 281 282 #if defined(CONFIG_NAND) 283 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 284 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 285 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 286 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 287 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 288 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 289 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 290 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 291 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 292 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 293 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 294 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 295 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 296 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 297 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 298 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 299 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 300 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 301 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 302 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 303 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 304 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 305 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 306 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 307 #else 308 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 309 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 310 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 311 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 312 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 313 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 314 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 315 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 316 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 317 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 318 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 319 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 320 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 321 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 322 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 323 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 324 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 325 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 326 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 327 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 328 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 329 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 330 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 331 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 332 #endif 333 334 #if defined(CONFIG_RAMBOOT_PBL) 335 #define CONFIG_SYS_RAMBOOT 336 #endif 337 338 /* I2C */ 339 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 340 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 341 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 342 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 343 344 #define I2C_MUX_CH_DEFAULT 0x8 345 #define I2C_MUX_CH_VOL_MONITOR 0xa 346 #define I2C_MUX_CH_VSC3316_FS 0xc 347 #define I2C_MUX_CH_VSC3316_BS 0xd 348 349 /* Voltage monitor on channel 2*/ 350 #define I2C_VOL_MONITOR_ADDR 0x40 351 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 352 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 353 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 354 355 /* VSC Crossbar switches */ 356 #define CONFIG_VSC_CROSSBAR 357 #define VSC3316_FSM_TX_ADDR 0x70 358 #define VSC3316_FSM_RX_ADDR 0x71 359 360 /* 361 * RapidIO 362 */ 363 364 /* 365 * for slave u-boot IMAGE instored in master memory space, 366 * PHYS must be aligned based on the SIZE 367 */ 368 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 369 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 370 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 371 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 372 /* 373 * for slave UCODE and ENV instored in master memory space, 374 * PHYS must be aligned based on the SIZE 375 */ 376 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 377 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 378 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 379 380 /* slave core release by master*/ 381 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 382 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 383 384 /* 385 * SRIO_PCIE_BOOT - SLAVE 386 */ 387 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 388 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 389 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 390 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 391 #endif 392 /* 393 * eSPI - Enhanced SPI 394 */ 395 #define CONFIG_SF_DEFAULT_SPEED 10000000 396 #define CONFIG_SF_DEFAULT_MODE 0 397 398 /* Qman/Bman */ 399 #ifndef CONFIG_NOBQFMAN 400 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 401 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 402 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 403 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 404 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 405 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 406 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 407 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 408 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 409 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 410 CONFIG_SYS_BMAN_CENA_SIZE) 411 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 412 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 413 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 414 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 415 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 416 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 417 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 418 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 419 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 420 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 421 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 422 CONFIG_SYS_QMAN_CENA_SIZE) 423 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 424 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 425 426 #define CONFIG_SYS_DPAA_FMAN 427 #define CONFIG_SYS_DPAA_PME 428 #define CONFIG_SYS_PMAN 429 #define CONFIG_SYS_DPAA_DCE 430 #define CONFIG_SYS_DPAA_RMAN 431 #define CONFIG_SYS_INTERLAKEN 432 433 /* Default address of microcode for the Linux Fman driver */ 434 #if defined(CONFIG_SPIFLASH) 435 /* 436 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 437 * env, so we got 0x110000. 438 */ 439 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 440 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 441 #elif defined(CONFIG_SDCARD) 442 /* 443 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 444 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 445 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 446 */ 447 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 448 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 449 #elif defined(CONFIG_NAND) 450 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 451 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 452 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 453 /* 454 * Slave has no ucode locally, it can fetch this from remote. When implementing 455 * in two corenet boards, slave's ucode could be stored in master's memory 456 * space, the address can be mapped from slave TLB->slave LAW-> 457 * slave SRIO or PCIE outbound window->master inbound window-> 458 * master LAW->the ucode address in master's memory space. 459 */ 460 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 461 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 462 #else 463 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 464 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 465 #endif 466 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 467 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 468 #endif /* CONFIG_NOBQFMAN */ 469 470 #ifdef CONFIG_SYS_DPAA_FMAN 471 #define CONFIG_FMAN_ENET 472 #define CONFIG_PHYLIB_10G 473 #define CONFIG_PHY_VITESSE 474 #define CONFIG_PHY_TERANETICS 475 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 476 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 477 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 478 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 479 #define FM1_10GEC1_PHY_ADDR 0x0 480 #define FM1_10GEC2_PHY_ADDR 0x1 481 #define FM2_10GEC1_PHY_ADDR 0x2 482 #define FM2_10GEC2_PHY_ADDR 0x3 483 #endif 484 485 /* SATA */ 486 #ifdef CONFIG_FSL_SATA_V2 487 #define CONFIG_LIBATA 488 #define CONFIG_FSL_SATA 489 490 #define CONFIG_SYS_SATA_MAX_DEVICE 2 491 #define CONFIG_SATA1 492 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 493 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 494 #define CONFIG_SATA2 495 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 496 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 497 498 #define CONFIG_LBA48 499 #define CONFIG_CMD_SATA 500 #define CONFIG_DOS_PARTITION 501 #endif 502 503 #ifdef CONFIG_FMAN_ENET 504 #define CONFIG_MII /* MII PHY management */ 505 #define CONFIG_ETHPRIME "FM1@DTSEC1" 506 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 507 #endif 508 509 /* Hash command with SHA acceleration supported in hardware */ 510 #ifdef CONFIG_FSL_CAAM 511 #define CONFIG_CMD_HASH 512 #define CONFIG_SHA_HW_ACCEL 513 #endif 514 515 /* 516 * USB 517 */ 518 #define CONFIG_USB_EHCI 519 #define CONFIG_USB_EHCI_FSL 520 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 521 #define CONFIG_HAS_FSL_DR_USB 522 523 #define CONFIG_MMC 524 525 #ifdef CONFIG_MMC 526 #define CONFIG_FSL_ESDHC 527 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 528 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 529 #define CONFIG_GENERIC_MMC 530 #define CONFIG_DOS_PARTITION 531 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 532 #define CONFIG_ESDHC_DETECT_QUIRK \ 533 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ 534 IS_SVR_REV(get_svr(), 1, 0)) 535 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ 536 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) 537 #endif 538 539 540 #define __USB_PHY_TYPE utmi 541 542 /* 543 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 544 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 545 * interleaving. It can be cacheline, page, bank, superbank. 546 * See doc/README.fsl-ddr for details. 547 */ 548 #ifdef CONFIG_PPC_T4240 549 #define CTRL_INTLV_PREFERED 3way_4KB 550 #else 551 #define CTRL_INTLV_PREFERED cacheline 552 #endif 553 554 #define CONFIG_EXTRA_ENV_SETTINGS \ 555 "hwconfig=fsl_ddr:" \ 556 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 557 "bank_intlv=auto;" \ 558 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 559 "netdev=eth0\0" \ 560 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 561 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 562 "tftpflash=tftpboot $loadaddr $uboot && " \ 563 "protect off $ubootaddr +$filesize && " \ 564 "erase $ubootaddr +$filesize && " \ 565 "cp.b $loadaddr $ubootaddr $filesize && " \ 566 "protect on $ubootaddr +$filesize && " \ 567 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 568 "consoledev=ttyS0\0" \ 569 "ramdiskaddr=2000000\0" \ 570 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 571 "fdtaddr=1e00000\0" \ 572 "fdtfile=t4240qds/t4240qds.dtb\0" \ 573 "bdev=sda3\0" 574 575 #define CONFIG_HVBOOT \ 576 "setenv bootargs config-addr=0x60000000; " \ 577 "bootm 0x01000000 - 0x00f00000" 578 579 #define CONFIG_ALU \ 580 "setenv bootargs root=/dev/$bdev rw " \ 581 "console=$consoledev,$baudrate $othbootargs;" \ 582 "cpu 1 release 0x01000000 - - -;" \ 583 "cpu 2 release 0x01000000 - - -;" \ 584 "cpu 3 release 0x01000000 - - -;" \ 585 "cpu 4 release 0x01000000 - - -;" \ 586 "cpu 5 release 0x01000000 - - -;" \ 587 "cpu 6 release 0x01000000 - - -;" \ 588 "cpu 7 release 0x01000000 - - -;" \ 589 "go 0x01000000" 590 591 #define CONFIG_LINUX \ 592 "setenv bootargs root=/dev/ram rw " \ 593 "console=$consoledev,$baudrate $othbootargs;" \ 594 "setenv ramdiskaddr 0x02000000;" \ 595 "setenv fdtaddr 0x00c00000;" \ 596 "setenv loadaddr 0x1000000;" \ 597 "bootm $loadaddr $ramdiskaddr $fdtaddr" 598 599 #define CONFIG_HDBOOT \ 600 "setenv bootargs root=/dev/$bdev rw " \ 601 "console=$consoledev,$baudrate $othbootargs;" \ 602 "tftp $loadaddr $bootfile;" \ 603 "tftp $fdtaddr $fdtfile;" \ 604 "bootm $loadaddr - $fdtaddr" 605 606 #define CONFIG_NFSBOOTCOMMAND \ 607 "setenv bootargs root=/dev/nfs rw " \ 608 "nfsroot=$serverip:$rootpath " \ 609 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 610 "console=$consoledev,$baudrate $othbootargs;" \ 611 "tftp $loadaddr $bootfile;" \ 612 "tftp $fdtaddr $fdtfile;" \ 613 "bootm $loadaddr - $fdtaddr" 614 615 #define CONFIG_RAMBOOTCOMMAND \ 616 "setenv bootargs root=/dev/ram rw " \ 617 "console=$consoledev,$baudrate $othbootargs;" \ 618 "tftp $ramdiskaddr $ramdiskfile;" \ 619 "tftp $loadaddr $bootfile;" \ 620 "tftp $fdtaddr $fdtfile;" \ 621 "bootm $loadaddr $ramdiskaddr $fdtaddr" 622 623 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 624 625 #include <asm/fsl_secure_boot.h> 626 627 #endif /* __CONFIG_H */ 628