1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 QDS board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_FSL_SATA_V2 14 #define CONFIG_PCIE4 15 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg 20 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) 21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 23 #else 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x00201000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #define RESET_VECTOR_OFFSET 0x27FFC 31 #define BOOT_PAGE_OFFSET 0x27000 32 33 #ifdef CONFIG_NAND 34 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 35 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 36 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 37 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 38 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 39 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg 40 #define CONFIG_SPL_NAND_BOOT 41 #endif 42 43 #ifdef CONFIG_SDCARD 44 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 45 #define CONFIG_SPL_MMC_MINIMAL 46 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 47 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 48 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 49 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 50 #ifndef CONFIG_SPL_BUILD 51 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 52 #endif 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg 55 #define CONFIG_SPL_MMC_BOOT 56 #endif 57 58 #ifdef CONFIG_SPL_BUILD 59 #define CONFIG_SPL_SKIP_RELOCATE 60 #define CONFIG_SPL_COMMON_INIT_DDR 61 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 62 #endif 63 64 #endif 65 #endif /* CONFIG_RAMBOOT_PBL */ 66 67 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 68 /* Set 1M boot space */ 69 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 70 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 71 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 72 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 73 #endif 74 75 #define CONFIG_SRIO_PCIE_BOOT_MASTER 76 #define CONFIG_DDR_ECC 77 78 #include "t4qds.h" 79 80 #ifndef CONFIG_MTD_NOR_FLASH 81 #else 82 #define CONFIG_FLASH_CFI_DRIVER 83 #define CONFIG_SYS_FLASH_CFI 84 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 85 #endif 86 87 #if defined(CONFIG_SPIFLASH) 88 #define CONFIG_SYS_EXTRA_ENV_RELOC 89 #define CONFIG_ENV_IS_IN_SPI_FLASH 90 #define CONFIG_ENV_SPI_BUS 0 91 #define CONFIG_ENV_SPI_CS 0 92 #define CONFIG_ENV_SPI_MAX_HZ 10000000 93 #define CONFIG_ENV_SPI_MODE 0 94 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 95 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 96 #define CONFIG_ENV_SECT_SIZE 0x10000 97 #elif defined(CONFIG_SDCARD) 98 #define CONFIG_SYS_EXTRA_ENV_RELOC 99 #define CONFIG_SYS_MMC_ENV_DEV 0 100 #define CONFIG_ENV_SIZE 0x2000 101 #define CONFIG_ENV_OFFSET (512 * 0x800) 102 #elif defined(CONFIG_NAND) 103 #define CONFIG_SYS_EXTRA_ENV_RELOC 104 #define CONFIG_ENV_SIZE 0x2000 105 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 106 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 107 #define CONFIG_ENV_IS_IN_REMOTE 108 #define CONFIG_ENV_ADDR 0xffe20000 109 #define CONFIG_ENV_SIZE 0x2000 110 #elif defined(CONFIG_ENV_IS_NOWHERE) 111 #define CONFIG_ENV_SIZE 0x2000 112 #else 113 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 114 #define CONFIG_ENV_SIZE 0x2000 115 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 116 #endif 117 118 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 119 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 120 121 #ifndef __ASSEMBLY__ 122 unsigned long get_board_sys_clk(void); 123 unsigned long get_board_ddr_clk(void); 124 #endif 125 126 /* EEPROM */ 127 #define CONFIG_ID_EEPROM 128 #define CONFIG_SYS_I2C_EEPROM_NXID 129 #define CONFIG_SYS_EEPROM_BUS_NUM 0 130 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 131 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 132 133 /* 134 * DDR Setup 135 */ 136 #define CONFIG_SYS_SPD_BUS_NUM 0 137 #define SPD_EEPROM_ADDRESS1 0x51 138 #define SPD_EEPROM_ADDRESS2 0x52 139 #define SPD_EEPROM_ADDRESS3 0x53 140 #define SPD_EEPROM_ADDRESS4 0x54 141 #define SPD_EEPROM_ADDRESS5 0x55 142 #define SPD_EEPROM_ADDRESS6 0x56 143 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 144 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 145 146 /* 147 * IFC Definitions 148 */ 149 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 150 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 151 + 0x8000000) | \ 152 CSPR_PORT_SIZE_16 | \ 153 CSPR_MSEL_NOR | \ 154 CSPR_V) 155 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 156 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 157 CSPR_PORT_SIZE_16 | \ 158 CSPR_MSEL_NOR | \ 159 CSPR_V) 160 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 161 /* NOR Flash Timing Params */ 162 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 163 164 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 165 FTIM0_NOR_TEADC(0x5) | \ 166 FTIM0_NOR_TEAHC(0x5)) 167 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 168 FTIM1_NOR_TRAD_NOR(0x1A) |\ 169 FTIM1_NOR_TSEQRAD_NOR(0x13)) 170 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 171 FTIM2_NOR_TCH(0x4) | \ 172 FTIM2_NOR_TWPH(0x0E) | \ 173 FTIM2_NOR_TWP(0x1c)) 174 #define CONFIG_SYS_NOR_FTIM3 0x0 175 176 #define CONFIG_SYS_FLASH_QUIET_TEST 177 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 178 179 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 180 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 181 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 182 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 183 184 #define CONFIG_SYS_FLASH_EMPTY_INFO 185 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 186 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 187 188 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 189 #define QIXIS_BASE 0xffdf0000 190 #define QIXIS_LBMAP_SWITCH 6 191 #define QIXIS_LBMAP_MASK 0x0f 192 #define QIXIS_LBMAP_SHIFT 0 193 #define QIXIS_LBMAP_DFLTBANK 0x00 194 #define QIXIS_LBMAP_ALTBANK 0x04 195 #define QIXIS_RST_CTL_RESET 0x83 196 #define QIXIS_RST_FORCE_MEM 0x1 197 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 198 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 199 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 200 #define QIXIS_BRDCFG5 0x55 201 #define QIXIS_MUX_SDHC 2 202 #define QIXIS_MUX_SDHC_WIDTH8 1 203 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 204 205 #define CONFIG_SYS_CSPR3_EXT (0xf) 206 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 207 | CSPR_PORT_SIZE_8 \ 208 | CSPR_MSEL_GPCM \ 209 | CSPR_V) 210 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 211 #define CONFIG_SYS_CSOR3 0x0 212 /* QIXIS Timing parameters for IFC CS3 */ 213 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 214 FTIM0_GPCM_TEADC(0x0e) | \ 215 FTIM0_GPCM_TEAHC(0x0e)) 216 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 217 FTIM1_GPCM_TRAD(0x3f)) 218 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 219 FTIM2_GPCM_TCH(0x8) | \ 220 FTIM2_GPCM_TWP(0x1f)) 221 #define CONFIG_SYS_CS3_FTIM3 0x0 222 223 /* NAND Flash on IFC */ 224 #define CONFIG_NAND_FSL_IFC 225 #define CONFIG_SYS_NAND_BASE 0xff800000 226 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 227 228 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 229 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 230 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 231 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 232 | CSPR_V) 233 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 234 235 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 236 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 237 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 238 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 239 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 240 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 241 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 242 243 #define CONFIG_SYS_NAND_ONFI_DETECTION 244 245 /* ONFI NAND Flash mode0 Timing Params */ 246 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 247 FTIM0_NAND_TWP(0x18) | \ 248 FTIM0_NAND_TWCHT(0x07) | \ 249 FTIM0_NAND_TWH(0x0a)) 250 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 251 FTIM1_NAND_TWBE(0x39) | \ 252 FTIM1_NAND_TRR(0x0e) | \ 253 FTIM1_NAND_TRP(0x18)) 254 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 255 FTIM2_NAND_TREH(0x0a) | \ 256 FTIM2_NAND_TWHRE(0x1e)) 257 #define CONFIG_SYS_NAND_FTIM3 0x0 258 259 #define CONFIG_SYS_NAND_DDR_LAW 11 260 261 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 262 #define CONFIG_SYS_MAX_NAND_DEVICE 1 263 #define CONFIG_CMD_NAND 264 265 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 266 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 267 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 268 269 #if defined(CONFIG_NAND) 270 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 271 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 272 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 273 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 274 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 275 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 276 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 277 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 278 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 279 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 280 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 281 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 282 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 283 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 284 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 285 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 286 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 287 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 288 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 289 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 290 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 291 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 292 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 293 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 294 #else 295 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 296 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 297 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 298 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 299 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 300 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 301 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 302 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 303 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 304 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 305 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 306 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 307 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 308 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 309 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 310 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 311 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 312 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 313 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 314 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 315 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 316 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 317 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 318 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 319 #endif 320 321 #if defined(CONFIG_RAMBOOT_PBL) 322 #define CONFIG_SYS_RAMBOOT 323 #endif 324 325 /* I2C */ 326 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 327 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 328 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 329 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 330 331 #define I2C_MUX_CH_DEFAULT 0x8 332 #define I2C_MUX_CH_VOL_MONITOR 0xa 333 #define I2C_MUX_CH_VSC3316_FS 0xc 334 #define I2C_MUX_CH_VSC3316_BS 0xd 335 336 /* Voltage monitor on channel 2*/ 337 #define I2C_VOL_MONITOR_ADDR 0x40 338 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 339 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 340 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 341 342 /* VSC Crossbar switches */ 343 #define CONFIG_VSC_CROSSBAR 344 #define VSC3316_FSM_TX_ADDR 0x70 345 #define VSC3316_FSM_RX_ADDR 0x71 346 347 /* 348 * RapidIO 349 */ 350 351 /* 352 * for slave u-boot IMAGE instored in master memory space, 353 * PHYS must be aligned based on the SIZE 354 */ 355 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 356 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 357 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 358 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 359 /* 360 * for slave UCODE and ENV instored in master memory space, 361 * PHYS must be aligned based on the SIZE 362 */ 363 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 364 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 365 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 366 367 /* slave core release by master*/ 368 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 369 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 370 371 /* 372 * SRIO_PCIE_BOOT - SLAVE 373 */ 374 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 375 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 376 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 377 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 378 #endif 379 /* 380 * eSPI - Enhanced SPI 381 */ 382 #define CONFIG_SF_DEFAULT_SPEED 10000000 383 #define CONFIG_SF_DEFAULT_MODE 0 384 385 /* Qman/Bman */ 386 #ifndef CONFIG_NOBQFMAN 387 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 388 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 389 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 390 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 391 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 392 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 393 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 394 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 395 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 396 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 397 CONFIG_SYS_BMAN_CENA_SIZE) 398 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 399 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 400 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 401 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 402 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 403 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 404 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 405 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 406 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 407 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 408 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 409 CONFIG_SYS_QMAN_CENA_SIZE) 410 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 411 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 412 413 #define CONFIG_SYS_DPAA_FMAN 414 #define CONFIG_SYS_DPAA_PME 415 #define CONFIG_SYS_PMAN 416 #define CONFIG_SYS_DPAA_DCE 417 #define CONFIG_SYS_DPAA_RMAN 418 #define CONFIG_SYS_INTERLAKEN 419 420 /* Default address of microcode for the Linux Fman driver */ 421 #if defined(CONFIG_SPIFLASH) 422 /* 423 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 424 * env, so we got 0x110000. 425 */ 426 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 427 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 428 #elif defined(CONFIG_SDCARD) 429 /* 430 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 431 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 432 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 433 */ 434 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 435 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 436 #elif defined(CONFIG_NAND) 437 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 438 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 439 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 440 /* 441 * Slave has no ucode locally, it can fetch this from remote. When implementing 442 * in two corenet boards, slave's ucode could be stored in master's memory 443 * space, the address can be mapped from slave TLB->slave LAW-> 444 * slave SRIO or PCIE outbound window->master inbound window-> 445 * master LAW->the ucode address in master's memory space. 446 */ 447 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 448 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 449 #else 450 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 451 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 452 #endif 453 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 454 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 455 #endif /* CONFIG_NOBQFMAN */ 456 457 #ifdef CONFIG_SYS_DPAA_FMAN 458 #define CONFIG_FMAN_ENET 459 #define CONFIG_PHYLIB_10G 460 #define CONFIG_PHY_VITESSE 461 #define CONFIG_PHY_TERANETICS 462 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 463 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 464 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 465 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 466 #define FM1_10GEC1_PHY_ADDR 0x0 467 #define FM1_10GEC2_PHY_ADDR 0x1 468 #define FM2_10GEC1_PHY_ADDR 0x2 469 #define FM2_10GEC2_PHY_ADDR 0x3 470 #endif 471 472 /* SATA */ 473 #ifdef CONFIG_FSL_SATA_V2 474 #define CONFIG_LIBATA 475 #define CONFIG_FSL_SATA 476 477 #define CONFIG_SYS_SATA_MAX_DEVICE 2 478 #define CONFIG_SATA1 479 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 480 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 481 #define CONFIG_SATA2 482 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 483 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 484 485 #define CONFIG_LBA48 486 #endif 487 488 #ifdef CONFIG_FMAN_ENET 489 #define CONFIG_MII /* MII PHY management */ 490 #define CONFIG_ETHPRIME "FM1@DTSEC1" 491 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 492 #endif 493 494 /* 495 * USB 496 */ 497 #define CONFIG_USB_EHCI_FSL 498 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 499 #define CONFIG_HAS_FSL_DR_USB 500 501 #ifdef CONFIG_MMC 502 #define CONFIG_FSL_ESDHC 503 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 504 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 505 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 506 #define CONFIG_ESDHC_DETECT_QUIRK \ 507 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ 508 IS_SVR_REV(get_svr(), 1, 0)) 509 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ 510 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) 511 #endif 512 513 514 #define __USB_PHY_TYPE utmi 515 516 /* 517 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 518 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 519 * interleaving. It can be cacheline, page, bank, superbank. 520 * See doc/README.fsl-ddr for details. 521 */ 522 #ifdef CONFIG_ARCH_T4240 523 #define CTRL_INTLV_PREFERED 3way_4KB 524 #else 525 #define CTRL_INTLV_PREFERED cacheline 526 #endif 527 528 #define CONFIG_EXTRA_ENV_SETTINGS \ 529 "hwconfig=fsl_ddr:" \ 530 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 531 "bank_intlv=auto;" \ 532 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 533 "netdev=eth0\0" \ 534 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 535 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 536 "tftpflash=tftpboot $loadaddr $uboot && " \ 537 "protect off $ubootaddr +$filesize && " \ 538 "erase $ubootaddr +$filesize && " \ 539 "cp.b $loadaddr $ubootaddr $filesize && " \ 540 "protect on $ubootaddr +$filesize && " \ 541 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 542 "consoledev=ttyS0\0" \ 543 "ramdiskaddr=2000000\0" \ 544 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 545 "fdtaddr=1e00000\0" \ 546 "fdtfile=t4240qds/t4240qds.dtb\0" \ 547 "bdev=sda3\0" 548 549 #define CONFIG_HVBOOT \ 550 "setenv bootargs config-addr=0x60000000; " \ 551 "bootm 0x01000000 - 0x00f00000" 552 553 #define CONFIG_ALU \ 554 "setenv bootargs root=/dev/$bdev rw " \ 555 "console=$consoledev,$baudrate $othbootargs;" \ 556 "cpu 1 release 0x01000000 - - -;" \ 557 "cpu 2 release 0x01000000 - - -;" \ 558 "cpu 3 release 0x01000000 - - -;" \ 559 "cpu 4 release 0x01000000 - - -;" \ 560 "cpu 5 release 0x01000000 - - -;" \ 561 "cpu 6 release 0x01000000 - - -;" \ 562 "cpu 7 release 0x01000000 - - -;" \ 563 "go 0x01000000" 564 565 #define CONFIG_LINUX \ 566 "setenv bootargs root=/dev/ram rw " \ 567 "console=$consoledev,$baudrate $othbootargs;" \ 568 "setenv ramdiskaddr 0x02000000;" \ 569 "setenv fdtaddr 0x00c00000;" \ 570 "setenv loadaddr 0x1000000;" \ 571 "bootm $loadaddr $ramdiskaddr $fdtaddr" 572 573 #define CONFIG_HDBOOT \ 574 "setenv bootargs root=/dev/$bdev rw " \ 575 "console=$consoledev,$baudrate $othbootargs;" \ 576 "tftp $loadaddr $bootfile;" \ 577 "tftp $fdtaddr $fdtfile;" \ 578 "bootm $loadaddr - $fdtaddr" 579 580 #define CONFIG_NFSBOOTCOMMAND \ 581 "setenv bootargs root=/dev/nfs rw " \ 582 "nfsroot=$serverip:$rootpath " \ 583 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 584 "console=$consoledev,$baudrate $othbootargs;" \ 585 "tftp $loadaddr $bootfile;" \ 586 "tftp $fdtaddr $fdtfile;" \ 587 "bootm $loadaddr - $fdtaddr" 588 589 #define CONFIG_RAMBOOTCOMMAND \ 590 "setenv bootargs root=/dev/ram rw " \ 591 "console=$consoledev,$baudrate $othbootargs;" \ 592 "tftp $ramdiskaddr $ramdiskfile;" \ 593 "tftp $loadaddr $bootfile;" \ 594 "tftp $fdtaddr $fdtfile;" \ 595 "bootm $loadaddr $ramdiskaddr $fdtaddr" 596 597 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 598 599 #include <asm/fsl_secure_boot.h> 600 601 #endif /* __CONFIG_H */ 602