1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_T2080RDB 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 #define CONFIG_MMC 18 #define CONFIG_USB_EHCI 19 #define CONFIG_FSL_SATA_V2 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 23 #define CONFIG_E500 /* BOOKE e500 family */ 24 #define CONFIG_E500MC /* BOOKE e500mc family */ 25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 26 #define CONFIG_MP /* support multiple processors */ 27 #define CONFIG_ENABLE_36BIT_PHYS 28 29 #ifdef CONFIG_PHYS_64BIT 30 #define CONFIG_ADDR_MAP 1 31 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 32 #endif 33 34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 35 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 36 #define CONFIG_FSL_IFC /* Enable IFC Support */ 37 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 38 #define CONFIG_FSL_LAW /* Use common FSL init code */ 39 #define CONFIG_ENV_OVERWRITE 40 41 #ifdef CONFIG_RAMBOOT_PBL 42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 43 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg 44 45 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 46 #define CONFIG_SPL_ENV_SUPPORT 47 #define CONFIG_SPL_SERIAL_SUPPORT 48 #define CONFIG_SPL_FLUSH_IMAGE 49 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 50 #define CONFIG_SPL_LIBGENERIC_SUPPORT 51 #define CONFIG_SPL_LIBCOMMON_SUPPORT 52 #define CONFIG_SPL_I2C_SUPPORT 53 #define CONFIG_FSL_LAW /* Use common FSL init code */ 54 #define CONFIG_SYS_TEXT_BASE 0x00201000 55 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 56 #define CONFIG_SPL_PAD_TO 0x40000 57 #define CONFIG_SPL_MAX_SIZE 0x28000 58 #define RESET_VECTOR_OFFSET 0x27FFC 59 #define BOOT_PAGE_OFFSET 0x27000 60 #ifdef CONFIG_SPL_BUILD 61 #define CONFIG_SPL_SKIP_RELOCATE 62 #define CONFIG_SPL_COMMON_INIT_DDR 63 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 64 #define CONFIG_SYS_NO_FLASH 65 #endif 66 67 #ifdef CONFIG_NAND 68 #define CONFIG_SPL_NAND_SUPPORT 69 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 70 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 71 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 72 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 73 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 74 #define CONFIG_SPL_NAND_BOOT 75 #endif 76 77 #ifdef CONFIG_SPIFLASH 78 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 79 #define CONFIG_SPL_SPI_SUPPORT 80 #define CONFIG_SPL_SPI_FLASH_SUPPORT 81 #define CONFIG_SPL_SPI_FLASH_MINIMAL 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 86 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 87 #ifndef CONFIG_SPL_BUILD 88 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 89 #endif 90 #define CONFIG_SPL_SPI_BOOT 91 #endif 92 93 #ifdef CONFIG_SDCARD 94 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 95 #define CONFIG_SPL_MMC_SUPPORT 96 #define CONFIG_SPL_MMC_MINIMAL 97 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 98 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 99 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 100 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 101 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 102 #ifndef CONFIG_SPL_BUILD 103 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 104 #endif 105 #define CONFIG_SPL_MMC_BOOT 106 #endif 107 108 #endif /* CONFIG_RAMBOOT_PBL */ 109 110 #define CONFIG_SRIO_PCIE_BOOT_MASTER 111 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 112 /* Set 1M boot space */ 113 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 114 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 115 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 116 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 117 #define CONFIG_SYS_NO_FLASH 118 #endif 119 120 #ifndef CONFIG_SYS_TEXT_BASE 121 #define CONFIG_SYS_TEXT_BASE 0xeff40000 122 #endif 123 124 #ifndef CONFIG_RESET_VECTOR_ADDRESS 125 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 126 #endif 127 128 /* 129 * These can be toggled for performance analysis, otherwise use default. 130 */ 131 #define CONFIG_SYS_CACHE_STASHING 132 #define CONFIG_BTB /* toggle branch predition */ 133 #define CONFIG_DDR_ECC 134 #ifdef CONFIG_DDR_ECC 135 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 136 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 137 #endif 138 139 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 140 #define CONFIG_SYS_MEMTEST_END 0x00400000 141 #define CONFIG_SYS_ALT_MEMTEST 142 143 #ifndef CONFIG_SYS_NO_FLASH 144 #define CONFIG_FLASH_CFI_DRIVER 145 #define CONFIG_SYS_FLASH_CFI 146 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 147 #endif 148 149 #if defined(CONFIG_SPIFLASH) 150 #define CONFIG_SYS_EXTRA_ENV_RELOC 151 #define CONFIG_ENV_IS_IN_SPI_FLASH 152 #define CONFIG_ENV_SPI_BUS 0 153 #define CONFIG_ENV_SPI_CS 0 154 #define CONFIG_ENV_SPI_MAX_HZ 10000000 155 #define CONFIG_ENV_SPI_MODE 0 156 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 157 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 158 #define CONFIG_ENV_SECT_SIZE 0x10000 159 #elif defined(CONFIG_SDCARD) 160 #define CONFIG_SYS_EXTRA_ENV_RELOC 161 #define CONFIG_ENV_IS_IN_MMC 162 #define CONFIG_SYS_MMC_ENV_DEV 0 163 #define CONFIG_ENV_SIZE 0x2000 164 #define CONFIG_ENV_OFFSET (512 * 0x800) 165 #elif defined(CONFIG_NAND) 166 #define CONFIG_SYS_EXTRA_ENV_RELOC 167 #define CONFIG_ENV_IS_IN_NAND 168 #define CONFIG_ENV_SIZE 0x2000 169 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 170 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 171 #define CONFIG_ENV_IS_IN_REMOTE 172 #define CONFIG_ENV_ADDR 0xffe20000 173 #define CONFIG_ENV_SIZE 0x2000 174 #elif defined(CONFIG_ENV_IS_NOWHERE) 175 #define CONFIG_ENV_SIZE 0x2000 176 #else 177 #define CONFIG_ENV_IS_IN_FLASH 178 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 179 #define CONFIG_ENV_SIZE 0x2000 180 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 181 #endif 182 183 #ifndef __ASSEMBLY__ 184 unsigned long get_board_sys_clk(void); 185 unsigned long get_board_ddr_clk(void); 186 #endif 187 188 #define CONFIG_SYS_CLK_FREQ 66660000 189 #define CONFIG_DDR_CLK_FREQ 133330000 190 191 /* 192 * Config the L3 Cache as L3 SRAM 193 */ 194 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 195 #define CONFIG_SYS_L3_SIZE (512 << 10) 196 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 197 #ifdef CONFIG_RAMBOOT_PBL 198 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 199 #endif 200 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 201 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 202 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 203 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 204 205 #define CONFIG_SYS_DCSRBAR 0xf0000000 206 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 207 208 /* EEPROM */ 209 #define CONFIG_ID_EEPROM 210 #define CONFIG_SYS_I2C_EEPROM_NXID 211 #define CONFIG_SYS_EEPROM_BUS_NUM 0 212 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 213 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 214 215 /* 216 * DDR Setup 217 */ 218 #define CONFIG_VERY_BIG_RAM 219 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 220 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 221 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 222 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 223 #define CONFIG_DDR_SPD 224 #define CONFIG_SYS_FSL_DDR3 225 #undef CONFIG_FSL_DDR_INTERACTIVE 226 #define CONFIG_SYS_SPD_BUS_NUM 0 227 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 228 #define SPD_EEPROM_ADDRESS1 0x51 229 #define SPD_EEPROM_ADDRESS2 0x52 230 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 231 #define CTRL_INTLV_PREFERED cacheline 232 233 /* 234 * IFC Definitions 235 */ 236 #define CONFIG_SYS_FLASH_BASE 0xe8000000 237 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 238 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 239 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 240 CSPR_PORT_SIZE_16 | \ 241 CSPR_MSEL_NOR | \ 242 CSPR_V) 243 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 244 245 /* NOR Flash Timing Params */ 246 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 247 248 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 249 FTIM0_NOR_TEADC(0x5) | \ 250 FTIM0_NOR_TEAHC(0x5)) 251 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 252 FTIM1_NOR_TRAD_NOR(0x1A) |\ 253 FTIM1_NOR_TSEQRAD_NOR(0x13)) 254 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 255 FTIM2_NOR_TCH(0x4) | \ 256 FTIM2_NOR_TWPH(0x0E) | \ 257 FTIM2_NOR_TWP(0x1c)) 258 #define CONFIG_SYS_NOR_FTIM3 0x0 259 260 #define CONFIG_SYS_FLASH_QUIET_TEST 261 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 262 263 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 264 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 265 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 266 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 267 #define CONFIG_SYS_FLASH_EMPTY_INFO 268 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 269 270 /* CPLD on IFC */ 271 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 272 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 273 #define CONFIG_SYS_CSPR2_EXT (0xf) 274 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 275 | CSPR_PORT_SIZE_8 \ 276 | CSPR_MSEL_GPCM \ 277 | CSPR_V) 278 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 279 #define CONFIG_SYS_CSOR2 0x0 280 281 /* CPLD Timing parameters for IFC CS2 */ 282 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 283 FTIM0_GPCM_TEADC(0x0e) | \ 284 FTIM0_GPCM_TEAHC(0x0e)) 285 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 286 FTIM1_GPCM_TRAD(0x1f)) 287 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 288 FTIM2_GPCM_TCH(0x8) | \ 289 FTIM2_GPCM_TWP(0x1f)) 290 #define CONFIG_SYS_CS2_FTIM3 0x0 291 292 /* NAND Flash on IFC */ 293 #define CONFIG_NAND_FSL_IFC 294 #define CONFIG_SYS_NAND_BASE 0xff800000 295 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 296 297 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 298 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 299 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 300 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 301 | CSPR_V) 302 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 303 304 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 305 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 306 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 307 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 308 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 309 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 310 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 311 312 #define CONFIG_SYS_NAND_ONFI_DETECTION 313 314 /* ONFI NAND Flash mode0 Timing Params */ 315 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 316 FTIM0_NAND_TWP(0x18) | \ 317 FTIM0_NAND_TWCHT(0x07) | \ 318 FTIM0_NAND_TWH(0x0a)) 319 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 320 FTIM1_NAND_TWBE(0x39) | \ 321 FTIM1_NAND_TRR(0x0e) | \ 322 FTIM1_NAND_TRP(0x18)) 323 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 324 FTIM2_NAND_TREH(0x0a) | \ 325 FTIM2_NAND_TWHRE(0x1e)) 326 #define CONFIG_SYS_NAND_FTIM3 0x0 327 328 #define CONFIG_SYS_NAND_DDR_LAW 11 329 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 330 #define CONFIG_SYS_MAX_NAND_DEVICE 1 331 #define CONFIG_CMD_NAND 332 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 333 334 #if defined(CONFIG_NAND) 335 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 336 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 337 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 338 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 339 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 340 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 341 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 342 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 343 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 344 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 345 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 346 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 347 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 348 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 349 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 350 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 351 #else 352 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 353 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 354 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 355 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 356 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 357 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 358 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 359 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 360 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 361 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 362 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 363 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 364 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 365 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 366 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 367 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 368 #endif 369 370 #if defined(CONFIG_RAMBOOT_PBL) 371 #define CONFIG_SYS_RAMBOOT 372 #endif 373 374 #ifdef CONFIG_SPL_BUILD 375 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 376 #else 377 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 378 #endif 379 380 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 381 #define CONFIG_MISC_INIT_R 382 #define CONFIG_HWCONFIG 383 384 /* define to use L1 as initial stack */ 385 #define CONFIG_L1_INIT_RAM 386 #define CONFIG_SYS_INIT_RAM_LOCK 387 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 388 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 389 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 390 /* The assembler doesn't like typecast */ 391 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 392 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 393 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 394 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 395 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 396 GENERATED_GBL_DATA_SIZE) 397 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 398 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 399 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 400 401 /* 402 * Serial Port 403 */ 404 #define CONFIG_CONS_INDEX 1 405 #define CONFIG_SYS_NS16550_SERIAL 406 #define CONFIG_SYS_NS16550_REG_SIZE 1 407 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 408 #define CONFIG_SYS_BAUDRATE_TABLE \ 409 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 410 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 411 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 412 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 413 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 414 415 /* 416 * I2C 417 */ 418 #define CONFIG_SYS_I2C 419 #define CONFIG_SYS_I2C_FSL 420 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 421 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 422 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 423 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 424 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 425 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 426 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 427 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 428 #define CONFIG_SYS_FSL_I2C_SPEED 100000 429 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 430 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 431 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 432 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 433 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 434 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 435 #define I2C_MUX_CH_DEFAULT 0x8 436 437 #define I2C_MUX_CH_VOL_MONITOR 0xa 438 439 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 440 #ifndef CONFIG_SPL_BUILD 441 #define CONFIG_VID 442 #endif 443 #define CONFIG_VOL_MONITOR_IR36021_SET 444 #define CONFIG_VOL_MONITOR_IR36021_READ 445 /* The lowest and highest voltage allowed for T208xRDB */ 446 #define VDD_MV_MIN 819 447 #define VDD_MV_MAX 1212 448 449 /* 450 * RapidIO 451 */ 452 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 453 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 454 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 455 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 456 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 457 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 458 /* 459 * for slave u-boot IMAGE instored in master memory space, 460 * PHYS must be aligned based on the SIZE 461 */ 462 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 463 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 464 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 465 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 466 /* 467 * for slave UCODE and ENV instored in master memory space, 468 * PHYS must be aligned based on the SIZE 469 */ 470 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 471 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 472 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 473 474 /* slave core release by master*/ 475 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 476 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 477 478 /* 479 * SRIO_PCIE_BOOT - SLAVE 480 */ 481 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 482 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 483 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 484 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 485 #endif 486 487 /* 488 * eSPI - Enhanced SPI 489 */ 490 #ifdef CONFIG_SPI_FLASH 491 #define CONFIG_SPI_FLASH_BAR 492 #define CONFIG_SF_DEFAULT_SPEED 10000000 493 #define CONFIG_SF_DEFAULT_MODE 0 494 #endif 495 496 /* 497 * General PCI 498 * Memory space is mapped 1-1, but I/O space must start from 0. 499 */ 500 #define CONFIG_PCI /* Enable PCI/PCIE */ 501 #define CONFIG_PCIE1 /* PCIE controller 1 */ 502 #define CONFIG_PCIE2 /* PCIE controller 2 */ 503 #define CONFIG_PCIE3 /* PCIE controller 3 */ 504 #define CONFIG_PCIE4 /* PCIE controller 4 */ 505 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 506 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 507 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 508 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 509 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 510 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 511 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 512 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 513 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 514 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 515 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 516 517 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 518 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 519 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 520 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 521 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 522 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 523 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 524 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 525 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 526 527 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 528 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 529 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 530 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 531 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 532 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 533 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 534 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 535 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 536 537 /* controller 4, Base address 203000 */ 538 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 539 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 540 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 541 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 542 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 543 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 544 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 545 546 #ifdef CONFIG_PCI 547 #define CONFIG_PCI_INDIRECT_BRIDGE 548 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 549 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 550 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 551 #define CONFIG_DOS_PARTITION 552 #endif 553 554 /* Qman/Bman */ 555 #ifndef CONFIG_NOBQFMAN 556 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 557 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 558 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 559 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 560 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 561 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 562 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 563 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 564 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 565 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 566 CONFIG_SYS_BMAN_CENA_SIZE) 567 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 568 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 569 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 570 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 571 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 572 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 573 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 574 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 575 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 576 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 577 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 578 CONFIG_SYS_QMAN_CENA_SIZE) 579 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 580 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 581 582 #define CONFIG_SYS_DPAA_FMAN 583 #define CONFIG_SYS_DPAA_PME 584 #define CONFIG_SYS_PMAN 585 #define CONFIG_SYS_DPAA_DCE 586 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 587 #define CONFIG_SYS_INTERLAKEN 588 589 /* Default address of microcode for the Linux Fman driver */ 590 #if defined(CONFIG_SPIFLASH) 591 /* 592 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 593 * env, so we got 0x110000. 594 */ 595 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 596 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 597 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 598 #define CONFIG_CORTINA_FW_ADDR 0x120000 599 600 #elif defined(CONFIG_SDCARD) 601 /* 602 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 603 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 604 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 605 */ 606 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 607 #define CONFIG_SYS_CORTINA_FW_IN_MMC 608 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 609 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 610 611 #elif defined(CONFIG_NAND) 612 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 613 #define CONFIG_SYS_CORTINA_FW_IN_NAND 614 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 615 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 616 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 617 /* 618 * Slave has no ucode locally, it can fetch this from remote. When implementing 619 * in two corenet boards, slave's ucode could be stored in master's memory 620 * space, the address can be mapped from slave TLB->slave LAW-> 621 * slave SRIO or PCIE outbound window->master inbound window-> 622 * master LAW->the ucode address in master's memory space. 623 */ 624 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 625 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 626 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 627 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 628 #else 629 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 630 #define CONFIG_SYS_CORTINA_FW_IN_NOR 631 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 632 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 633 #endif 634 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 635 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 636 #endif /* CONFIG_NOBQFMAN */ 637 638 #ifdef CONFIG_SYS_DPAA_FMAN 639 #define CONFIG_FMAN_ENET 640 #define CONFIG_PHYLIB_10G 641 #define CONFIG_PHY_AQUANTIA 642 #define CONFIG_PHY_CORTINA 643 #define CONFIG_PHY_REALTEK 644 #define CONFIG_CORTINA_FW_LENGTH 0x40000 645 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 646 #define RGMII_PHY2_ADDR 0x02 647 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 648 #define CORTINA_PHY_ADDR2 0x0d 649 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 650 #define FM1_10GEC4_PHY_ADDR 0x01 651 #endif 652 653 #ifdef CONFIG_FMAN_ENET 654 #define CONFIG_MII /* MII PHY management */ 655 #define CONFIG_ETHPRIME "FM1@DTSEC3" 656 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 657 #endif 658 659 /* 660 * SATA 661 */ 662 #ifdef CONFIG_FSL_SATA_V2 663 #define CONFIG_LIBATA 664 #define CONFIG_FSL_SATA 665 #define CONFIG_SYS_SATA_MAX_DEVICE 2 666 #define CONFIG_SATA1 667 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 668 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 669 #define CONFIG_SATA2 670 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 671 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 672 #define CONFIG_LBA48 673 #define CONFIG_CMD_SATA 674 #define CONFIG_DOS_PARTITION 675 #endif 676 677 /* 678 * USB 679 */ 680 #ifdef CONFIG_USB_EHCI 681 #define CONFIG_USB_EHCI_FSL 682 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 683 #define CONFIG_HAS_FSL_DR_USB 684 #endif 685 686 /* 687 * SDHC 688 */ 689 #ifdef CONFIG_MMC 690 #define CONFIG_FSL_ESDHC 691 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 692 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 693 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 694 #define CONFIG_GENERIC_MMC 695 #define CONFIG_DOS_PARTITION 696 #endif 697 698 /* 699 * Dynamic MTD Partition support with mtdparts 700 */ 701 #ifndef CONFIG_SYS_NO_FLASH 702 #define CONFIG_MTD_DEVICE 703 #define CONFIG_MTD_PARTITIONS 704 #define CONFIG_CMD_MTDPARTS 705 #define CONFIG_FLASH_CFI_MTD 706 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 707 "spi0=spife110000.1" 708 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 709 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 710 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 711 "1m(uboot),5m(kernel),128k(dtb),-(user)" 712 #endif 713 714 /* 715 * Environment 716 */ 717 718 /* 719 * Command line configuration. 720 */ 721 #define CONFIG_CMD_ERRATA 722 #define CONFIG_CMD_REGINFO 723 724 #ifdef CONFIG_PCI 725 #define CONFIG_CMD_PCI 726 #endif 727 728 /* Hash command with SHA acceleration supported in hardware */ 729 #ifdef CONFIG_FSL_CAAM 730 #define CONFIG_CMD_HASH 731 #define CONFIG_SHA_HW_ACCEL 732 #endif 733 734 /* 735 * Miscellaneous configurable options 736 */ 737 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 738 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 739 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 740 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 741 #ifdef CONFIG_CMD_KGDB 742 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 743 #else 744 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 745 #endif 746 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 747 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 748 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 749 750 /* 751 * For booting Linux, the board info and command line data 752 * have to be in the first 64 MB of memory, since this is 753 * the maximum mapped by the Linux kernel during initialization. 754 */ 755 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 756 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 757 758 #ifdef CONFIG_CMD_KGDB 759 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 760 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 761 #endif 762 763 /* 764 * Environment Configuration 765 */ 766 #define CONFIG_ROOTPATH "/opt/nfsroot" 767 #define CONFIG_BOOTFILE "uImage" 768 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 769 770 /* default location for tftp and bootm */ 771 #define CONFIG_LOADADDR 1000000 772 #define CONFIG_BAUDRATE 115200 773 #define __USB_PHY_TYPE utmi 774 775 #define CONFIG_EXTRA_ENV_SETTINGS \ 776 "hwconfig=fsl_ddr:" \ 777 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 778 "bank_intlv=auto;" \ 779 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 780 "netdev=eth0\0" \ 781 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 782 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 783 "tftpflash=tftpboot $loadaddr $uboot && " \ 784 "protect off $ubootaddr +$filesize && " \ 785 "erase $ubootaddr +$filesize && " \ 786 "cp.b $loadaddr $ubootaddr $filesize && " \ 787 "protect on $ubootaddr +$filesize && " \ 788 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 789 "consoledev=ttyS0\0" \ 790 "ramdiskaddr=2000000\0" \ 791 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 792 "fdtaddr=1e00000\0" \ 793 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 794 "bdev=sda3\0" 795 796 /* 797 * For emulation this causes u-boot to jump to the start of the 798 * proof point app code automatically 799 */ 800 #define CONFIG_PROOF_POINTS \ 801 "setenv bootargs root=/dev/$bdev rw " \ 802 "console=$consoledev,$baudrate $othbootargs;" \ 803 "cpu 1 release 0x29000000 - - -;" \ 804 "cpu 2 release 0x29000000 - - -;" \ 805 "cpu 3 release 0x29000000 - - -;" \ 806 "cpu 4 release 0x29000000 - - -;" \ 807 "cpu 5 release 0x29000000 - - -;" \ 808 "cpu 6 release 0x29000000 - - -;" \ 809 "cpu 7 release 0x29000000 - - -;" \ 810 "go 0x29000000" 811 812 #define CONFIG_HVBOOT \ 813 "setenv bootargs config-addr=0x60000000; " \ 814 "bootm 0x01000000 - 0x00f00000" 815 816 #define CONFIG_ALU \ 817 "setenv bootargs root=/dev/$bdev rw " \ 818 "console=$consoledev,$baudrate $othbootargs;" \ 819 "cpu 1 release 0x01000000 - - -;" \ 820 "cpu 2 release 0x01000000 - - -;" \ 821 "cpu 3 release 0x01000000 - - -;" \ 822 "cpu 4 release 0x01000000 - - -;" \ 823 "cpu 5 release 0x01000000 - - -;" \ 824 "cpu 6 release 0x01000000 - - -;" \ 825 "cpu 7 release 0x01000000 - - -;" \ 826 "go 0x01000000" 827 828 #define CONFIG_LINUX \ 829 "setenv bootargs root=/dev/ram rw " \ 830 "console=$consoledev,$baudrate $othbootargs;" \ 831 "setenv ramdiskaddr 0x02000000;" \ 832 "setenv fdtaddr 0x00c00000;" \ 833 "setenv loadaddr 0x1000000;" \ 834 "bootm $loadaddr $ramdiskaddr $fdtaddr" 835 836 #define CONFIG_HDBOOT \ 837 "setenv bootargs root=/dev/$bdev rw " \ 838 "console=$consoledev,$baudrate $othbootargs;" \ 839 "tftp $loadaddr $bootfile;" \ 840 "tftp $fdtaddr $fdtfile;" \ 841 "bootm $loadaddr - $fdtaddr" 842 843 #define CONFIG_NFSBOOTCOMMAND \ 844 "setenv bootargs root=/dev/nfs rw " \ 845 "nfsroot=$serverip:$rootpath " \ 846 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 847 "console=$consoledev,$baudrate $othbootargs;" \ 848 "tftp $loadaddr $bootfile;" \ 849 "tftp $fdtaddr $fdtfile;" \ 850 "bootm $loadaddr - $fdtaddr" 851 852 #define CONFIG_RAMBOOTCOMMAND \ 853 "setenv bootargs root=/dev/ram rw " \ 854 "console=$consoledev,$baudrate $othbootargs;" \ 855 "tftp $ramdiskaddr $ramdiskfile;" \ 856 "tftp $loadaddr $bootfile;" \ 857 "tftp $fdtaddr $fdtfile;" \ 858 "bootm $loadaddr $ramdiskaddr $fdtaddr" 859 860 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 861 862 #include <asm/fsl_secure_boot.h> 863 864 #endif /* __T2080RDB_H */ 865