1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_T2080RDB 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 #define CONFIG_MMC 18 #define CONFIG_USB_EHCI 19 #define CONFIG_FSL_SATA_V2 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 23 #define CONFIG_E500 /* BOOKE e500 family */ 24 #define CONFIG_E500MC /* BOOKE e500mc family */ 25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 26 #define CONFIG_MP /* support multiple processors */ 27 #define CONFIG_ENABLE_36BIT_PHYS 28 29 #ifdef CONFIG_PHYS_64BIT 30 #define CONFIG_ADDR_MAP 1 31 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 32 #endif 33 34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 35 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 36 #define CONFIG_FSL_IFC /* Enable IFC Support */ 37 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 38 #define CONFIG_FSL_LAW /* Use common FSL init code */ 39 #define CONFIG_ENV_OVERWRITE 40 41 #ifdef CONFIG_RAMBOOT_PBL 42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 43 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg 44 45 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 46 #define CONFIG_SPL_SERIAL_SUPPORT 47 #define CONFIG_SPL_FLUSH_IMAGE 48 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 49 #define CONFIG_SPL_LIBGENERIC_SUPPORT 50 #define CONFIG_SPL_LIBCOMMON_SUPPORT 51 #define CONFIG_SPL_I2C_SUPPORT 52 #define CONFIG_FSL_LAW /* Use common FSL init code */ 53 #define CONFIG_SYS_TEXT_BASE 0x00201000 54 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 55 #define CONFIG_SPL_PAD_TO 0x40000 56 #define CONFIG_SPL_MAX_SIZE 0x28000 57 #define RESET_VECTOR_OFFSET 0x27FFC 58 #define BOOT_PAGE_OFFSET 0x27000 59 #ifdef CONFIG_SPL_BUILD 60 #define CONFIG_SPL_SKIP_RELOCATE 61 #define CONFIG_SPL_COMMON_INIT_DDR 62 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 63 #define CONFIG_SYS_NO_FLASH 64 #endif 65 66 #ifdef CONFIG_NAND 67 #define CONFIG_SPL_NAND_SUPPORT 68 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 69 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 70 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 71 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 72 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 73 #define CONFIG_SPL_NAND_BOOT 74 #endif 75 76 #ifdef CONFIG_SPIFLASH 77 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 78 #define CONFIG_SPL_SPI_SUPPORT 79 #define CONFIG_SPL_SPI_FLASH_SUPPORT 80 #define CONFIG_SPL_SPI_FLASH_MINIMAL 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 86 #ifndef CONFIG_SPL_BUILD 87 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 88 #endif 89 #define CONFIG_SPL_SPI_BOOT 90 #endif 91 92 #ifdef CONFIG_SDCARD 93 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 94 #define CONFIG_SPL_MMC_SUPPORT 95 #define CONFIG_SPL_MMC_MINIMAL 96 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 97 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 98 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 99 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 100 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 101 #ifndef CONFIG_SPL_BUILD 102 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 103 #endif 104 #define CONFIG_SPL_MMC_BOOT 105 #endif 106 107 #endif /* CONFIG_RAMBOOT_PBL */ 108 109 #define CONFIG_SRIO_PCIE_BOOT_MASTER 110 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 111 /* Set 1M boot space */ 112 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 113 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 114 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 115 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 116 #define CONFIG_SYS_NO_FLASH 117 #endif 118 119 #ifndef CONFIG_SYS_TEXT_BASE 120 #define CONFIG_SYS_TEXT_BASE 0xeff40000 121 #endif 122 123 #ifndef CONFIG_RESET_VECTOR_ADDRESS 124 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 125 #endif 126 127 /* 128 * These can be toggled for performance analysis, otherwise use default. 129 */ 130 #define CONFIG_SYS_CACHE_STASHING 131 #define CONFIG_BTB /* toggle branch predition */ 132 #define CONFIG_DDR_ECC 133 #ifdef CONFIG_DDR_ECC 134 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 135 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 136 #endif 137 138 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 139 #define CONFIG_SYS_MEMTEST_END 0x00400000 140 #define CONFIG_SYS_ALT_MEMTEST 141 142 #ifndef CONFIG_SYS_NO_FLASH 143 #define CONFIG_FLASH_CFI_DRIVER 144 #define CONFIG_SYS_FLASH_CFI 145 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 146 #endif 147 148 #if defined(CONFIG_SPIFLASH) 149 #define CONFIG_SYS_EXTRA_ENV_RELOC 150 #define CONFIG_ENV_IS_IN_SPI_FLASH 151 #define CONFIG_ENV_SPI_BUS 0 152 #define CONFIG_ENV_SPI_CS 0 153 #define CONFIG_ENV_SPI_MAX_HZ 10000000 154 #define CONFIG_ENV_SPI_MODE 0 155 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 156 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 157 #define CONFIG_ENV_SECT_SIZE 0x10000 158 #elif defined(CONFIG_SDCARD) 159 #define CONFIG_SYS_EXTRA_ENV_RELOC 160 #define CONFIG_ENV_IS_IN_MMC 161 #define CONFIG_SYS_MMC_ENV_DEV 0 162 #define CONFIG_ENV_SIZE 0x2000 163 #define CONFIG_ENV_OFFSET (512 * 0x800) 164 #elif defined(CONFIG_NAND) 165 #define CONFIG_SYS_EXTRA_ENV_RELOC 166 #define CONFIG_ENV_IS_IN_NAND 167 #define CONFIG_ENV_SIZE 0x2000 168 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 169 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 170 #define CONFIG_ENV_IS_IN_REMOTE 171 #define CONFIG_ENV_ADDR 0xffe20000 172 #define CONFIG_ENV_SIZE 0x2000 173 #elif defined(CONFIG_ENV_IS_NOWHERE) 174 #define CONFIG_ENV_SIZE 0x2000 175 #else 176 #define CONFIG_ENV_IS_IN_FLASH 177 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 178 #define CONFIG_ENV_SIZE 0x2000 179 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 180 #endif 181 182 #ifndef __ASSEMBLY__ 183 unsigned long get_board_sys_clk(void); 184 unsigned long get_board_ddr_clk(void); 185 #endif 186 187 #define CONFIG_SYS_CLK_FREQ 66660000 188 #define CONFIG_DDR_CLK_FREQ 133330000 189 190 /* 191 * Config the L3 Cache as L3 SRAM 192 */ 193 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 194 #define CONFIG_SYS_L3_SIZE (512 << 10) 195 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 196 #ifdef CONFIG_RAMBOOT_PBL 197 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 198 #endif 199 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 200 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 201 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 202 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 203 204 #define CONFIG_SYS_DCSRBAR 0xf0000000 205 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 206 207 /* EEPROM */ 208 #define CONFIG_ID_EEPROM 209 #define CONFIG_SYS_I2C_EEPROM_NXID 210 #define CONFIG_SYS_EEPROM_BUS_NUM 0 211 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 212 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 213 214 /* 215 * DDR Setup 216 */ 217 #define CONFIG_VERY_BIG_RAM 218 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 219 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 220 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 221 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 222 #define CONFIG_DDR_SPD 223 #define CONFIG_SYS_FSL_DDR3 224 #undef CONFIG_FSL_DDR_INTERACTIVE 225 #define CONFIG_SYS_SPD_BUS_NUM 0 226 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 227 #define SPD_EEPROM_ADDRESS1 0x51 228 #define SPD_EEPROM_ADDRESS2 0x52 229 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 230 #define CTRL_INTLV_PREFERED cacheline 231 232 /* 233 * IFC Definitions 234 */ 235 #define CONFIG_SYS_FLASH_BASE 0xe8000000 236 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 237 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 238 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 239 CSPR_PORT_SIZE_16 | \ 240 CSPR_MSEL_NOR | \ 241 CSPR_V) 242 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 243 244 /* NOR Flash Timing Params */ 245 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 246 247 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 248 FTIM0_NOR_TEADC(0x5) | \ 249 FTIM0_NOR_TEAHC(0x5)) 250 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 251 FTIM1_NOR_TRAD_NOR(0x1A) |\ 252 FTIM1_NOR_TSEQRAD_NOR(0x13)) 253 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 254 FTIM2_NOR_TCH(0x4) | \ 255 FTIM2_NOR_TWPH(0x0E) | \ 256 FTIM2_NOR_TWP(0x1c)) 257 #define CONFIG_SYS_NOR_FTIM3 0x0 258 259 #define CONFIG_SYS_FLASH_QUIET_TEST 260 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 261 262 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 263 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 264 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 265 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 266 #define CONFIG_SYS_FLASH_EMPTY_INFO 267 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 268 269 /* CPLD on IFC */ 270 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 271 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 272 #define CONFIG_SYS_CSPR2_EXT (0xf) 273 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 274 | CSPR_PORT_SIZE_8 \ 275 | CSPR_MSEL_GPCM \ 276 | CSPR_V) 277 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 278 #define CONFIG_SYS_CSOR2 0x0 279 280 /* CPLD Timing parameters for IFC CS2 */ 281 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 282 FTIM0_GPCM_TEADC(0x0e) | \ 283 FTIM0_GPCM_TEAHC(0x0e)) 284 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 285 FTIM1_GPCM_TRAD(0x1f)) 286 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 287 FTIM2_GPCM_TCH(0x8) | \ 288 FTIM2_GPCM_TWP(0x1f)) 289 #define CONFIG_SYS_CS2_FTIM3 0x0 290 291 /* NAND Flash on IFC */ 292 #define CONFIG_NAND_FSL_IFC 293 #define CONFIG_SYS_NAND_BASE 0xff800000 294 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 295 296 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 297 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 298 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 299 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 300 | CSPR_V) 301 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 302 303 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 304 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 305 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 306 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 307 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 308 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 309 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 310 311 #define CONFIG_SYS_NAND_ONFI_DETECTION 312 313 /* ONFI NAND Flash mode0 Timing Params */ 314 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 315 FTIM0_NAND_TWP(0x18) | \ 316 FTIM0_NAND_TWCHT(0x07) | \ 317 FTIM0_NAND_TWH(0x0a)) 318 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 319 FTIM1_NAND_TWBE(0x39) | \ 320 FTIM1_NAND_TRR(0x0e) | \ 321 FTIM1_NAND_TRP(0x18)) 322 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 323 FTIM2_NAND_TREH(0x0a) | \ 324 FTIM2_NAND_TWHRE(0x1e)) 325 #define CONFIG_SYS_NAND_FTIM3 0x0 326 327 #define CONFIG_SYS_NAND_DDR_LAW 11 328 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 329 #define CONFIG_SYS_MAX_NAND_DEVICE 1 330 #define CONFIG_CMD_NAND 331 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 332 333 #if defined(CONFIG_NAND) 334 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 335 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 336 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 337 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 338 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 339 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 340 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 341 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 342 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 343 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 344 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 345 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 346 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 347 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 348 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 349 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 350 #else 351 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 352 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 353 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 354 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 355 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 356 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 357 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 358 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 359 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 360 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 361 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 362 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 363 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 364 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 365 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 366 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 367 #endif 368 369 #if defined(CONFIG_RAMBOOT_PBL) 370 #define CONFIG_SYS_RAMBOOT 371 #endif 372 373 #ifdef CONFIG_SPL_BUILD 374 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 375 #else 376 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 377 #endif 378 379 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 380 #define CONFIG_MISC_INIT_R 381 #define CONFIG_HWCONFIG 382 383 /* define to use L1 as initial stack */ 384 #define CONFIG_L1_INIT_RAM 385 #define CONFIG_SYS_INIT_RAM_LOCK 386 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 387 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 388 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 389 /* The assembler doesn't like typecast */ 390 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 391 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 392 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 393 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 394 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 395 GENERATED_GBL_DATA_SIZE) 396 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 397 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 398 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 399 400 /* 401 * Serial Port 402 */ 403 #define CONFIG_CONS_INDEX 1 404 #define CONFIG_SYS_NS16550_SERIAL 405 #define CONFIG_SYS_NS16550_REG_SIZE 1 406 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 407 #define CONFIG_SYS_BAUDRATE_TABLE \ 408 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 409 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 410 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 411 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 412 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 413 414 /* 415 * I2C 416 */ 417 #define CONFIG_SYS_I2C 418 #define CONFIG_SYS_I2C_FSL 419 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 420 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 421 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 422 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 423 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 424 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 425 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 426 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 427 #define CONFIG_SYS_FSL_I2C_SPEED 100000 428 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 429 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 430 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 431 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 432 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 433 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 434 #define I2C_MUX_CH_DEFAULT 0x8 435 436 #define I2C_MUX_CH_VOL_MONITOR 0xa 437 438 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 439 #ifndef CONFIG_SPL_BUILD 440 #define CONFIG_VID 441 #endif 442 #define CONFIG_VOL_MONITOR_IR36021_SET 443 #define CONFIG_VOL_MONITOR_IR36021_READ 444 /* The lowest and highest voltage allowed for T208xRDB */ 445 #define VDD_MV_MIN 819 446 #define VDD_MV_MAX 1212 447 448 /* 449 * RapidIO 450 */ 451 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 452 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 453 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 454 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 455 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 456 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 457 /* 458 * for slave u-boot IMAGE instored in master memory space, 459 * PHYS must be aligned based on the SIZE 460 */ 461 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 462 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 463 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 464 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 465 /* 466 * for slave UCODE and ENV instored in master memory space, 467 * PHYS must be aligned based on the SIZE 468 */ 469 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 470 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 471 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 472 473 /* slave core release by master*/ 474 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 475 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 476 477 /* 478 * SRIO_PCIE_BOOT - SLAVE 479 */ 480 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 481 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 482 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 483 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 484 #endif 485 486 /* 487 * eSPI - Enhanced SPI 488 */ 489 #ifdef CONFIG_SPI_FLASH 490 #define CONFIG_SPI_FLASH_BAR 491 #define CONFIG_SF_DEFAULT_SPEED 10000000 492 #define CONFIG_SF_DEFAULT_MODE 0 493 #endif 494 495 /* 496 * General PCI 497 * Memory space is mapped 1-1, but I/O space must start from 0. 498 */ 499 #define CONFIG_PCI /* Enable PCI/PCIE */ 500 #define CONFIG_PCIE1 /* PCIE controller 1 */ 501 #define CONFIG_PCIE2 /* PCIE controller 2 */ 502 #define CONFIG_PCIE3 /* PCIE controller 3 */ 503 #define CONFIG_PCIE4 /* PCIE controller 4 */ 504 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 505 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 506 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 507 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 508 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 509 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 510 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 511 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 512 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 513 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 514 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 515 516 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 517 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 518 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 519 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 520 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 521 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 522 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 523 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 524 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 525 526 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 527 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 528 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 529 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 530 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 531 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 532 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 533 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 534 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 535 536 /* controller 4, Base address 203000 */ 537 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 538 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 539 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 540 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 541 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 542 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 543 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 544 545 #ifdef CONFIG_PCI 546 #define CONFIG_PCI_INDIRECT_BRIDGE 547 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 548 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 549 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 550 #define CONFIG_DOS_PARTITION 551 #endif 552 553 /* Qman/Bman */ 554 #ifndef CONFIG_NOBQFMAN 555 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 556 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 557 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 558 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 559 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 560 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 561 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 562 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 563 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 564 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 565 CONFIG_SYS_BMAN_CENA_SIZE) 566 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 567 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 568 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 569 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 570 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 571 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 572 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 573 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 574 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 575 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 576 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 577 CONFIG_SYS_QMAN_CENA_SIZE) 578 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 579 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 580 581 #define CONFIG_SYS_DPAA_FMAN 582 #define CONFIG_SYS_DPAA_PME 583 #define CONFIG_SYS_PMAN 584 #define CONFIG_SYS_DPAA_DCE 585 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 586 #define CONFIG_SYS_INTERLAKEN 587 588 /* Default address of microcode for the Linux Fman driver */ 589 #if defined(CONFIG_SPIFLASH) 590 /* 591 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 592 * env, so we got 0x110000. 593 */ 594 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 595 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 596 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 597 #define CONFIG_CORTINA_FW_ADDR 0x120000 598 599 #elif defined(CONFIG_SDCARD) 600 /* 601 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 602 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 603 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 604 */ 605 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 606 #define CONFIG_SYS_CORTINA_FW_IN_MMC 607 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 608 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 609 610 #elif defined(CONFIG_NAND) 611 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 612 #define CONFIG_SYS_CORTINA_FW_IN_NAND 613 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 614 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 615 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 616 /* 617 * Slave has no ucode locally, it can fetch this from remote. When implementing 618 * in two corenet boards, slave's ucode could be stored in master's memory 619 * space, the address can be mapped from slave TLB->slave LAW-> 620 * slave SRIO or PCIE outbound window->master inbound window-> 621 * master LAW->the ucode address in master's memory space. 622 */ 623 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 624 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 625 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 626 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 627 #else 628 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 629 #define CONFIG_SYS_CORTINA_FW_IN_NOR 630 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 631 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 632 #endif 633 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 634 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 635 #endif /* CONFIG_NOBQFMAN */ 636 637 #ifdef CONFIG_SYS_DPAA_FMAN 638 #define CONFIG_FMAN_ENET 639 #define CONFIG_PHYLIB_10G 640 #define CONFIG_PHY_AQUANTIA 641 #define CONFIG_PHY_CORTINA 642 #define CONFIG_PHY_REALTEK 643 #define CONFIG_CORTINA_FW_LENGTH 0x40000 644 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 645 #define RGMII_PHY2_ADDR 0x02 646 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 647 #define CORTINA_PHY_ADDR2 0x0d 648 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 649 #define FM1_10GEC4_PHY_ADDR 0x01 650 #endif 651 652 #ifdef CONFIG_FMAN_ENET 653 #define CONFIG_MII /* MII PHY management */ 654 #define CONFIG_ETHPRIME "FM1@DTSEC3" 655 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 656 #endif 657 658 /* 659 * SATA 660 */ 661 #ifdef CONFIG_FSL_SATA_V2 662 #define CONFIG_LIBATA 663 #define CONFIG_FSL_SATA 664 #define CONFIG_SYS_SATA_MAX_DEVICE 2 665 #define CONFIG_SATA1 666 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 667 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 668 #define CONFIG_SATA2 669 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 670 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 671 #define CONFIG_LBA48 672 #define CONFIG_CMD_SATA 673 #define CONFIG_DOS_PARTITION 674 #endif 675 676 /* 677 * USB 678 */ 679 #ifdef CONFIG_USB_EHCI 680 #define CONFIG_USB_EHCI_FSL 681 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 682 #define CONFIG_HAS_FSL_DR_USB 683 #endif 684 685 /* 686 * SDHC 687 */ 688 #ifdef CONFIG_MMC 689 #define CONFIG_FSL_ESDHC 690 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 691 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 692 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 693 #define CONFIG_GENERIC_MMC 694 #define CONFIG_DOS_PARTITION 695 #endif 696 697 /* 698 * Dynamic MTD Partition support with mtdparts 699 */ 700 #ifndef CONFIG_SYS_NO_FLASH 701 #define CONFIG_MTD_DEVICE 702 #define CONFIG_MTD_PARTITIONS 703 #define CONFIG_CMD_MTDPARTS 704 #define CONFIG_FLASH_CFI_MTD 705 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 706 "spi0=spife110000.1" 707 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 708 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 709 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 710 "1m(uboot),5m(kernel),128k(dtb),-(user)" 711 #endif 712 713 /* 714 * Environment 715 */ 716 717 /* 718 * Command line configuration. 719 */ 720 #define CONFIG_CMD_ERRATA 721 #define CONFIG_CMD_REGINFO 722 723 #ifdef CONFIG_PCI 724 #define CONFIG_CMD_PCI 725 #endif 726 727 /* Hash command with SHA acceleration supported in hardware */ 728 #ifdef CONFIG_FSL_CAAM 729 #define CONFIG_CMD_HASH 730 #define CONFIG_SHA_HW_ACCEL 731 #endif 732 733 /* 734 * Miscellaneous configurable options 735 */ 736 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 737 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 738 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 739 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 740 #ifdef CONFIG_CMD_KGDB 741 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 742 #else 743 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 744 #endif 745 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 746 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 747 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 748 749 /* 750 * For booting Linux, the board info and command line data 751 * have to be in the first 64 MB of memory, since this is 752 * the maximum mapped by the Linux kernel during initialization. 753 */ 754 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 755 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 756 757 #ifdef CONFIG_CMD_KGDB 758 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 759 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 760 #endif 761 762 /* 763 * Environment Configuration 764 */ 765 #define CONFIG_ROOTPATH "/opt/nfsroot" 766 #define CONFIG_BOOTFILE "uImage" 767 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 768 769 /* default location for tftp and bootm */ 770 #define CONFIG_LOADADDR 1000000 771 #define CONFIG_BAUDRATE 115200 772 #define __USB_PHY_TYPE utmi 773 774 #define CONFIG_EXTRA_ENV_SETTINGS \ 775 "hwconfig=fsl_ddr:" \ 776 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 777 "bank_intlv=auto;" \ 778 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 779 "netdev=eth0\0" \ 780 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 781 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 782 "tftpflash=tftpboot $loadaddr $uboot && " \ 783 "protect off $ubootaddr +$filesize && " \ 784 "erase $ubootaddr +$filesize && " \ 785 "cp.b $loadaddr $ubootaddr $filesize && " \ 786 "protect on $ubootaddr +$filesize && " \ 787 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 788 "consoledev=ttyS0\0" \ 789 "ramdiskaddr=2000000\0" \ 790 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 791 "fdtaddr=1e00000\0" \ 792 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 793 "bdev=sda3\0" 794 795 /* 796 * For emulation this causes u-boot to jump to the start of the 797 * proof point app code automatically 798 */ 799 #define CONFIG_PROOF_POINTS \ 800 "setenv bootargs root=/dev/$bdev rw " \ 801 "console=$consoledev,$baudrate $othbootargs;" \ 802 "cpu 1 release 0x29000000 - - -;" \ 803 "cpu 2 release 0x29000000 - - -;" \ 804 "cpu 3 release 0x29000000 - - -;" \ 805 "cpu 4 release 0x29000000 - - -;" \ 806 "cpu 5 release 0x29000000 - - -;" \ 807 "cpu 6 release 0x29000000 - - -;" \ 808 "cpu 7 release 0x29000000 - - -;" \ 809 "go 0x29000000" 810 811 #define CONFIG_HVBOOT \ 812 "setenv bootargs config-addr=0x60000000; " \ 813 "bootm 0x01000000 - 0x00f00000" 814 815 #define CONFIG_ALU \ 816 "setenv bootargs root=/dev/$bdev rw " \ 817 "console=$consoledev,$baudrate $othbootargs;" \ 818 "cpu 1 release 0x01000000 - - -;" \ 819 "cpu 2 release 0x01000000 - - -;" \ 820 "cpu 3 release 0x01000000 - - -;" \ 821 "cpu 4 release 0x01000000 - - -;" \ 822 "cpu 5 release 0x01000000 - - -;" \ 823 "cpu 6 release 0x01000000 - - -;" \ 824 "cpu 7 release 0x01000000 - - -;" \ 825 "go 0x01000000" 826 827 #define CONFIG_LINUX \ 828 "setenv bootargs root=/dev/ram rw " \ 829 "console=$consoledev,$baudrate $othbootargs;" \ 830 "setenv ramdiskaddr 0x02000000;" \ 831 "setenv fdtaddr 0x00c00000;" \ 832 "setenv loadaddr 0x1000000;" \ 833 "bootm $loadaddr $ramdiskaddr $fdtaddr" 834 835 #define CONFIG_HDBOOT \ 836 "setenv bootargs root=/dev/$bdev rw " \ 837 "console=$consoledev,$baudrate $othbootargs;" \ 838 "tftp $loadaddr $bootfile;" \ 839 "tftp $fdtaddr $fdtfile;" \ 840 "bootm $loadaddr - $fdtaddr" 841 842 #define CONFIG_NFSBOOTCOMMAND \ 843 "setenv bootargs root=/dev/nfs rw " \ 844 "nfsroot=$serverip:$rootpath " \ 845 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 846 "console=$consoledev,$baudrate $othbootargs;" \ 847 "tftp $loadaddr $bootfile;" \ 848 "tftp $fdtaddr $fdtfile;" \ 849 "bootm $loadaddr - $fdtaddr" 850 851 #define CONFIG_RAMBOOTCOMMAND \ 852 "setenv bootargs root=/dev/ram rw " \ 853 "console=$consoledev,$baudrate $othbootargs;" \ 854 "tftp $ramdiskaddr $ramdiskfile;" \ 855 "tftp $loadaddr $bootfile;" \ 856 "tftp $fdtaddr $fdtfile;" \ 857 "bootm $loadaddr $ramdiskaddr $fdtaddr" 858 859 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 860 861 #include <asm/fsl_secure_boot.h> 862 863 #endif /* __T2080RDB_H */ 864