1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_T2080RDB 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 #define CONFIG_MMC 18 #define CONFIG_USB_EHCI 19 #define CONFIG_FSL_SATA_V2 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 23 #define CONFIG_E500 /* BOOKE e500 family */ 24 #define CONFIG_E500MC /* BOOKE e500mc family */ 25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 26 #define CONFIG_MP /* support multiple processors */ 27 #define CONFIG_ENABLE_36BIT_PHYS 28 29 #ifdef CONFIG_PHYS_64BIT 30 #define CONFIG_ADDR_MAP 1 31 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 32 #endif 33 34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 35 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 36 #define CONFIG_FSL_IFC /* Enable IFC Support */ 37 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 38 #define CONFIG_FSL_LAW /* Use common FSL init code */ 39 #define CONFIG_ENV_OVERWRITE 40 41 #ifdef CONFIG_RAMBOOT_PBL 42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 43 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg 44 45 #define CONFIG_SPL_SERIAL_SUPPORT 46 #define CONFIG_SPL_FLUSH_IMAGE 47 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 48 #define CONFIG_FSL_LAW /* Use common FSL init code */ 49 #define CONFIG_SYS_TEXT_BASE 0x00201000 50 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 51 #define CONFIG_SPL_PAD_TO 0x40000 52 #define CONFIG_SPL_MAX_SIZE 0x28000 53 #define RESET_VECTOR_OFFSET 0x27FFC 54 #define BOOT_PAGE_OFFSET 0x27000 55 #ifdef CONFIG_SPL_BUILD 56 #define CONFIG_SPL_SKIP_RELOCATE 57 #define CONFIG_SPL_COMMON_INIT_DDR 58 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 59 #define CONFIG_SYS_NO_FLASH 60 #endif 61 62 #ifdef CONFIG_NAND 63 #define CONFIG_SPL_NAND_SUPPORT 64 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 65 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 66 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 67 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 68 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 69 #define CONFIG_SPL_NAND_BOOT 70 #endif 71 72 #ifdef CONFIG_SPIFLASH 73 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 74 #define CONFIG_SPL_SPI_SUPPORT 75 #define CONFIG_SPL_SPI_FLASH_SUPPORT 76 #define CONFIG_SPL_SPI_FLASH_MINIMAL 77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 81 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 82 #ifndef CONFIG_SPL_BUILD 83 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 84 #endif 85 #define CONFIG_SPL_SPI_BOOT 86 #endif 87 88 #ifdef CONFIG_SDCARD 89 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 90 #define CONFIG_SPL_MMC_MINIMAL 91 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 92 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 93 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 94 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 95 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 96 #ifndef CONFIG_SPL_BUILD 97 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 98 #endif 99 #define CONFIG_SPL_MMC_BOOT 100 #endif 101 102 #endif /* CONFIG_RAMBOOT_PBL */ 103 104 #define CONFIG_SRIO_PCIE_BOOT_MASTER 105 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 106 /* Set 1M boot space */ 107 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 108 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 109 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 110 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 111 #define CONFIG_SYS_NO_FLASH 112 #endif 113 114 #ifndef CONFIG_SYS_TEXT_BASE 115 #define CONFIG_SYS_TEXT_BASE 0xeff40000 116 #endif 117 118 #ifndef CONFIG_RESET_VECTOR_ADDRESS 119 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 120 #endif 121 122 /* 123 * These can be toggled for performance analysis, otherwise use default. 124 */ 125 #define CONFIG_SYS_CACHE_STASHING 126 #define CONFIG_BTB /* toggle branch predition */ 127 #define CONFIG_DDR_ECC 128 #ifdef CONFIG_DDR_ECC 129 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 130 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 131 #endif 132 133 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 134 #define CONFIG_SYS_MEMTEST_END 0x00400000 135 #define CONFIG_SYS_ALT_MEMTEST 136 137 #ifndef CONFIG_SYS_NO_FLASH 138 #define CONFIG_FLASH_CFI_DRIVER 139 #define CONFIG_SYS_FLASH_CFI 140 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 141 #endif 142 143 #if defined(CONFIG_SPIFLASH) 144 #define CONFIG_SYS_EXTRA_ENV_RELOC 145 #define CONFIG_ENV_IS_IN_SPI_FLASH 146 #define CONFIG_ENV_SPI_BUS 0 147 #define CONFIG_ENV_SPI_CS 0 148 #define CONFIG_ENV_SPI_MAX_HZ 10000000 149 #define CONFIG_ENV_SPI_MODE 0 150 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 151 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 152 #define CONFIG_ENV_SECT_SIZE 0x10000 153 #elif defined(CONFIG_SDCARD) 154 #define CONFIG_SYS_EXTRA_ENV_RELOC 155 #define CONFIG_ENV_IS_IN_MMC 156 #define CONFIG_SYS_MMC_ENV_DEV 0 157 #define CONFIG_ENV_SIZE 0x2000 158 #define CONFIG_ENV_OFFSET (512 * 0x800) 159 #elif defined(CONFIG_NAND) 160 #define CONFIG_SYS_EXTRA_ENV_RELOC 161 #define CONFIG_ENV_IS_IN_NAND 162 #define CONFIG_ENV_SIZE 0x2000 163 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 164 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 165 #define CONFIG_ENV_IS_IN_REMOTE 166 #define CONFIG_ENV_ADDR 0xffe20000 167 #define CONFIG_ENV_SIZE 0x2000 168 #elif defined(CONFIG_ENV_IS_NOWHERE) 169 #define CONFIG_ENV_SIZE 0x2000 170 #else 171 #define CONFIG_ENV_IS_IN_FLASH 172 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 173 #define CONFIG_ENV_SIZE 0x2000 174 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 175 #endif 176 177 #ifndef __ASSEMBLY__ 178 unsigned long get_board_sys_clk(void); 179 unsigned long get_board_ddr_clk(void); 180 #endif 181 182 #define CONFIG_SYS_CLK_FREQ 66660000 183 #define CONFIG_DDR_CLK_FREQ 133330000 184 185 /* 186 * Config the L3 Cache as L3 SRAM 187 */ 188 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 189 #define CONFIG_SYS_L3_SIZE (512 << 10) 190 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 191 #ifdef CONFIG_RAMBOOT_PBL 192 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 193 #endif 194 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 195 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 196 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 197 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 198 199 #define CONFIG_SYS_DCSRBAR 0xf0000000 200 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 201 202 /* EEPROM */ 203 #define CONFIG_ID_EEPROM 204 #define CONFIG_SYS_I2C_EEPROM_NXID 205 #define CONFIG_SYS_EEPROM_BUS_NUM 0 206 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 207 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 208 209 /* 210 * DDR Setup 211 */ 212 #define CONFIG_VERY_BIG_RAM 213 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 214 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 215 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 216 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 217 #define CONFIG_DDR_SPD 218 #define CONFIG_SYS_FSL_DDR3 219 #undef CONFIG_FSL_DDR_INTERACTIVE 220 #define CONFIG_SYS_SPD_BUS_NUM 0 221 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 222 #define SPD_EEPROM_ADDRESS1 0x51 223 #define SPD_EEPROM_ADDRESS2 0x52 224 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 225 #define CTRL_INTLV_PREFERED cacheline 226 227 /* 228 * IFC Definitions 229 */ 230 #define CONFIG_SYS_FLASH_BASE 0xe8000000 231 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 232 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 233 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 234 CSPR_PORT_SIZE_16 | \ 235 CSPR_MSEL_NOR | \ 236 CSPR_V) 237 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 238 239 /* NOR Flash Timing Params */ 240 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 241 242 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 243 FTIM0_NOR_TEADC(0x5) | \ 244 FTIM0_NOR_TEAHC(0x5)) 245 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 246 FTIM1_NOR_TRAD_NOR(0x1A) |\ 247 FTIM1_NOR_TSEQRAD_NOR(0x13)) 248 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 249 FTIM2_NOR_TCH(0x4) | \ 250 FTIM2_NOR_TWPH(0x0E) | \ 251 FTIM2_NOR_TWP(0x1c)) 252 #define CONFIG_SYS_NOR_FTIM3 0x0 253 254 #define CONFIG_SYS_FLASH_QUIET_TEST 255 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 256 257 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 258 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 259 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 260 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 261 #define CONFIG_SYS_FLASH_EMPTY_INFO 262 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 263 264 /* CPLD on IFC */ 265 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 266 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 267 #define CONFIG_SYS_CSPR2_EXT (0xf) 268 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 269 | CSPR_PORT_SIZE_8 \ 270 | CSPR_MSEL_GPCM \ 271 | CSPR_V) 272 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 273 #define CONFIG_SYS_CSOR2 0x0 274 275 /* CPLD Timing parameters for IFC CS2 */ 276 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 277 FTIM0_GPCM_TEADC(0x0e) | \ 278 FTIM0_GPCM_TEAHC(0x0e)) 279 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 280 FTIM1_GPCM_TRAD(0x1f)) 281 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 282 FTIM2_GPCM_TCH(0x8) | \ 283 FTIM2_GPCM_TWP(0x1f)) 284 #define CONFIG_SYS_CS2_FTIM3 0x0 285 286 /* NAND Flash on IFC */ 287 #define CONFIG_NAND_FSL_IFC 288 #define CONFIG_SYS_NAND_BASE 0xff800000 289 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 290 291 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 292 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 293 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 294 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 295 | CSPR_V) 296 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 297 298 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 299 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 300 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 301 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 302 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 303 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 304 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 305 306 #define CONFIG_SYS_NAND_ONFI_DETECTION 307 308 /* ONFI NAND Flash mode0 Timing Params */ 309 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 310 FTIM0_NAND_TWP(0x18) | \ 311 FTIM0_NAND_TWCHT(0x07) | \ 312 FTIM0_NAND_TWH(0x0a)) 313 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 314 FTIM1_NAND_TWBE(0x39) | \ 315 FTIM1_NAND_TRR(0x0e) | \ 316 FTIM1_NAND_TRP(0x18)) 317 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 318 FTIM2_NAND_TREH(0x0a) | \ 319 FTIM2_NAND_TWHRE(0x1e)) 320 #define CONFIG_SYS_NAND_FTIM3 0x0 321 322 #define CONFIG_SYS_NAND_DDR_LAW 11 323 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 324 #define CONFIG_SYS_MAX_NAND_DEVICE 1 325 #define CONFIG_CMD_NAND 326 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 327 328 #if defined(CONFIG_NAND) 329 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 330 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 331 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 332 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 333 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 334 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 335 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 336 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 337 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 338 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 339 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 340 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 341 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 342 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 343 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 344 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 345 #else 346 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 347 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 348 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 349 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 350 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 351 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 352 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 353 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 354 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 355 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 356 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 357 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 358 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 359 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 360 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 361 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 362 #endif 363 364 #if defined(CONFIG_RAMBOOT_PBL) 365 #define CONFIG_SYS_RAMBOOT 366 #endif 367 368 #ifdef CONFIG_SPL_BUILD 369 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 370 #else 371 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 372 #endif 373 374 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 375 #define CONFIG_MISC_INIT_R 376 #define CONFIG_HWCONFIG 377 378 /* define to use L1 as initial stack */ 379 #define CONFIG_L1_INIT_RAM 380 #define CONFIG_SYS_INIT_RAM_LOCK 381 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 382 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 383 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 384 /* The assembler doesn't like typecast */ 385 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 386 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 387 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 388 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 389 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 390 GENERATED_GBL_DATA_SIZE) 391 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 392 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 393 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 394 395 /* 396 * Serial Port 397 */ 398 #define CONFIG_CONS_INDEX 1 399 #define CONFIG_SYS_NS16550_SERIAL 400 #define CONFIG_SYS_NS16550_REG_SIZE 1 401 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 402 #define CONFIG_SYS_BAUDRATE_TABLE \ 403 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 404 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 405 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 406 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 407 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 408 409 /* 410 * I2C 411 */ 412 #define CONFIG_SYS_I2C 413 #define CONFIG_SYS_I2C_FSL 414 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 415 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 416 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 417 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 418 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 419 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 420 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 421 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 422 #define CONFIG_SYS_FSL_I2C_SPEED 100000 423 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 424 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 425 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 426 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 427 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 428 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 429 #define I2C_MUX_CH_DEFAULT 0x8 430 431 #define I2C_MUX_CH_VOL_MONITOR 0xa 432 433 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 434 #ifndef CONFIG_SPL_BUILD 435 #define CONFIG_VID 436 #endif 437 #define CONFIG_VOL_MONITOR_IR36021_SET 438 #define CONFIG_VOL_MONITOR_IR36021_READ 439 /* The lowest and highest voltage allowed for T208xRDB */ 440 #define VDD_MV_MIN 819 441 #define VDD_MV_MAX 1212 442 443 /* 444 * RapidIO 445 */ 446 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 447 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 448 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 449 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 450 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 451 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 452 /* 453 * for slave u-boot IMAGE instored in master memory space, 454 * PHYS must be aligned based on the SIZE 455 */ 456 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 457 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 458 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 459 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 460 /* 461 * for slave UCODE and ENV instored in master memory space, 462 * PHYS must be aligned based on the SIZE 463 */ 464 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 465 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 466 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 467 468 /* slave core release by master*/ 469 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 470 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 471 472 /* 473 * SRIO_PCIE_BOOT - SLAVE 474 */ 475 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 476 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 477 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 478 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 479 #endif 480 481 /* 482 * eSPI - Enhanced SPI 483 */ 484 #ifdef CONFIG_SPI_FLASH 485 #define CONFIG_SPI_FLASH_BAR 486 #define CONFIG_SF_DEFAULT_SPEED 10000000 487 #define CONFIG_SF_DEFAULT_MODE 0 488 #endif 489 490 /* 491 * General PCI 492 * Memory space is mapped 1-1, but I/O space must start from 0. 493 */ 494 #define CONFIG_PCI /* Enable PCI/PCIE */ 495 #define CONFIG_PCIE1 /* PCIE controller 1 */ 496 #define CONFIG_PCIE2 /* PCIE controller 2 */ 497 #define CONFIG_PCIE3 /* PCIE controller 3 */ 498 #define CONFIG_PCIE4 /* PCIE controller 4 */ 499 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 500 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 501 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 502 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 503 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 504 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 505 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 506 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 507 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 508 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 509 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 510 511 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 512 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 513 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 514 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 515 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 516 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 517 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 518 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 519 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 520 521 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 522 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 523 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 524 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 525 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 526 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 527 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 528 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 529 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 530 531 /* controller 4, Base address 203000 */ 532 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 533 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 534 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 535 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 536 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 537 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 538 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 539 540 #ifdef CONFIG_PCI 541 #define CONFIG_PCI_INDIRECT_BRIDGE 542 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 543 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 544 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 545 #define CONFIG_DOS_PARTITION 546 #endif 547 548 /* Qman/Bman */ 549 #ifndef CONFIG_NOBQFMAN 550 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 551 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 552 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 553 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 554 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 555 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 556 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 557 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 558 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 559 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 560 CONFIG_SYS_BMAN_CENA_SIZE) 561 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 562 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 563 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 564 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 565 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 566 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 567 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 568 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 569 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 570 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 571 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 572 CONFIG_SYS_QMAN_CENA_SIZE) 573 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 574 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 575 576 #define CONFIG_SYS_DPAA_FMAN 577 #define CONFIG_SYS_DPAA_PME 578 #define CONFIG_SYS_PMAN 579 #define CONFIG_SYS_DPAA_DCE 580 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 581 #define CONFIG_SYS_INTERLAKEN 582 583 /* Default address of microcode for the Linux Fman driver */ 584 #if defined(CONFIG_SPIFLASH) 585 /* 586 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 587 * env, so we got 0x110000. 588 */ 589 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 590 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 591 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 592 #define CONFIG_CORTINA_FW_ADDR 0x120000 593 594 #elif defined(CONFIG_SDCARD) 595 /* 596 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 597 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 598 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 599 */ 600 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 601 #define CONFIG_SYS_CORTINA_FW_IN_MMC 602 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 603 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 604 605 #elif defined(CONFIG_NAND) 606 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 607 #define CONFIG_SYS_CORTINA_FW_IN_NAND 608 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 609 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 610 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 611 /* 612 * Slave has no ucode locally, it can fetch this from remote. When implementing 613 * in two corenet boards, slave's ucode could be stored in master's memory 614 * space, the address can be mapped from slave TLB->slave LAW-> 615 * slave SRIO or PCIE outbound window->master inbound window-> 616 * master LAW->the ucode address in master's memory space. 617 */ 618 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 619 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 620 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 621 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 622 #else 623 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 624 #define CONFIG_SYS_CORTINA_FW_IN_NOR 625 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 626 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 627 #endif 628 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 629 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 630 #endif /* CONFIG_NOBQFMAN */ 631 632 #ifdef CONFIG_SYS_DPAA_FMAN 633 #define CONFIG_FMAN_ENET 634 #define CONFIG_PHYLIB_10G 635 #define CONFIG_PHY_AQUANTIA 636 #define CONFIG_PHY_CORTINA 637 #define CONFIG_PHY_REALTEK 638 #define CONFIG_CORTINA_FW_LENGTH 0x40000 639 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 640 #define RGMII_PHY2_ADDR 0x02 641 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 642 #define CORTINA_PHY_ADDR2 0x0d 643 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 644 #define FM1_10GEC4_PHY_ADDR 0x01 645 #endif 646 647 #ifdef CONFIG_FMAN_ENET 648 #define CONFIG_MII /* MII PHY management */ 649 #define CONFIG_ETHPRIME "FM1@DTSEC3" 650 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 651 #endif 652 653 /* 654 * SATA 655 */ 656 #ifdef CONFIG_FSL_SATA_V2 657 #define CONFIG_LIBATA 658 #define CONFIG_FSL_SATA 659 #define CONFIG_SYS_SATA_MAX_DEVICE 2 660 #define CONFIG_SATA1 661 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 662 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 663 #define CONFIG_SATA2 664 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 665 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 666 #define CONFIG_LBA48 667 #define CONFIG_CMD_SATA 668 #define CONFIG_DOS_PARTITION 669 #endif 670 671 /* 672 * USB 673 */ 674 #ifdef CONFIG_USB_EHCI 675 #define CONFIG_USB_EHCI_FSL 676 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 677 #define CONFIG_HAS_FSL_DR_USB 678 #endif 679 680 /* 681 * SDHC 682 */ 683 #ifdef CONFIG_MMC 684 #define CONFIG_FSL_ESDHC 685 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 686 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 687 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 688 #define CONFIG_GENERIC_MMC 689 #define CONFIG_DOS_PARTITION 690 #endif 691 692 /* 693 * Dynamic MTD Partition support with mtdparts 694 */ 695 #ifndef CONFIG_SYS_NO_FLASH 696 #define CONFIG_MTD_DEVICE 697 #define CONFIG_MTD_PARTITIONS 698 #define CONFIG_CMD_MTDPARTS 699 #define CONFIG_FLASH_CFI_MTD 700 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 701 "spi0=spife110000.1" 702 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 703 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 704 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 705 "1m(uboot),5m(kernel),128k(dtb),-(user)" 706 #endif 707 708 /* 709 * Environment 710 */ 711 712 /* 713 * Command line configuration. 714 */ 715 #define CONFIG_CMD_ERRATA 716 #define CONFIG_CMD_REGINFO 717 718 #ifdef CONFIG_PCI 719 #define CONFIG_CMD_PCI 720 #endif 721 722 /* Hash command with SHA acceleration supported in hardware */ 723 #ifdef CONFIG_FSL_CAAM 724 #define CONFIG_CMD_HASH 725 #define CONFIG_SHA_HW_ACCEL 726 #endif 727 728 /* 729 * Miscellaneous configurable options 730 */ 731 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 732 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 733 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 734 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 735 #ifdef CONFIG_CMD_KGDB 736 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 737 #else 738 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 739 #endif 740 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 741 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 742 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 743 744 /* 745 * For booting Linux, the board info and command line data 746 * have to be in the first 64 MB of memory, since this is 747 * the maximum mapped by the Linux kernel during initialization. 748 */ 749 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 750 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 751 752 #ifdef CONFIG_CMD_KGDB 753 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 754 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 755 #endif 756 757 /* 758 * Environment Configuration 759 */ 760 #define CONFIG_ROOTPATH "/opt/nfsroot" 761 #define CONFIG_BOOTFILE "uImage" 762 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 763 764 /* default location for tftp and bootm */ 765 #define CONFIG_LOADADDR 1000000 766 #define CONFIG_BAUDRATE 115200 767 #define __USB_PHY_TYPE utmi 768 769 #define CONFIG_EXTRA_ENV_SETTINGS \ 770 "hwconfig=fsl_ddr:" \ 771 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 772 "bank_intlv=auto;" \ 773 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 774 "netdev=eth0\0" \ 775 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 776 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 777 "tftpflash=tftpboot $loadaddr $uboot && " \ 778 "protect off $ubootaddr +$filesize && " \ 779 "erase $ubootaddr +$filesize && " \ 780 "cp.b $loadaddr $ubootaddr $filesize && " \ 781 "protect on $ubootaddr +$filesize && " \ 782 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 783 "consoledev=ttyS0\0" \ 784 "ramdiskaddr=2000000\0" \ 785 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 786 "fdtaddr=1e00000\0" \ 787 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 788 "bdev=sda3\0" 789 790 /* 791 * For emulation this causes u-boot to jump to the start of the 792 * proof point app code automatically 793 */ 794 #define CONFIG_PROOF_POINTS \ 795 "setenv bootargs root=/dev/$bdev rw " \ 796 "console=$consoledev,$baudrate $othbootargs;" \ 797 "cpu 1 release 0x29000000 - - -;" \ 798 "cpu 2 release 0x29000000 - - -;" \ 799 "cpu 3 release 0x29000000 - - -;" \ 800 "cpu 4 release 0x29000000 - - -;" \ 801 "cpu 5 release 0x29000000 - - -;" \ 802 "cpu 6 release 0x29000000 - - -;" \ 803 "cpu 7 release 0x29000000 - - -;" \ 804 "go 0x29000000" 805 806 #define CONFIG_HVBOOT \ 807 "setenv bootargs config-addr=0x60000000; " \ 808 "bootm 0x01000000 - 0x00f00000" 809 810 #define CONFIG_ALU \ 811 "setenv bootargs root=/dev/$bdev rw " \ 812 "console=$consoledev,$baudrate $othbootargs;" \ 813 "cpu 1 release 0x01000000 - - -;" \ 814 "cpu 2 release 0x01000000 - - -;" \ 815 "cpu 3 release 0x01000000 - - -;" \ 816 "cpu 4 release 0x01000000 - - -;" \ 817 "cpu 5 release 0x01000000 - - -;" \ 818 "cpu 6 release 0x01000000 - - -;" \ 819 "cpu 7 release 0x01000000 - - -;" \ 820 "go 0x01000000" 821 822 #define CONFIG_LINUX \ 823 "setenv bootargs root=/dev/ram rw " \ 824 "console=$consoledev,$baudrate $othbootargs;" \ 825 "setenv ramdiskaddr 0x02000000;" \ 826 "setenv fdtaddr 0x00c00000;" \ 827 "setenv loadaddr 0x1000000;" \ 828 "bootm $loadaddr $ramdiskaddr $fdtaddr" 829 830 #define CONFIG_HDBOOT \ 831 "setenv bootargs root=/dev/$bdev rw " \ 832 "console=$consoledev,$baudrate $othbootargs;" \ 833 "tftp $loadaddr $bootfile;" \ 834 "tftp $fdtaddr $fdtfile;" \ 835 "bootm $loadaddr - $fdtaddr" 836 837 #define CONFIG_NFSBOOTCOMMAND \ 838 "setenv bootargs root=/dev/nfs rw " \ 839 "nfsroot=$serverip:$rootpath " \ 840 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 841 "console=$consoledev,$baudrate $othbootargs;" \ 842 "tftp $loadaddr $bootfile;" \ 843 "tftp $fdtaddr $fdtfile;" \ 844 "bootm $loadaddr - $fdtaddr" 845 846 #define CONFIG_RAMBOOTCOMMAND \ 847 "setenv bootargs root=/dev/ram rw " \ 848 "console=$consoledev,$baudrate $othbootargs;" \ 849 "tftp $ramdiskaddr $ramdiskfile;" \ 850 "tftp $loadaddr $bootfile;" \ 851 "tftp $fdtaddr $fdtfile;" \ 852 "bootm $loadaddr $ramdiskaddr $fdtaddr" 853 854 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 855 856 #include <asm/fsl_secure_boot.h> 857 858 #endif /* __T2080RDB_H */ 859