1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 15 #define CONFIG_FSL_SATA_V2 16 17 /* High Level Configuration Options */ 18 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 19 #define CONFIG_MP /* support multiple processors */ 20 #define CONFIG_ENABLE_36BIT_PHYS 21 22 #ifdef CONFIG_PHYS_64BIT 23 #define CONFIG_ADDR_MAP 1 24 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 25 #endif 26 27 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 28 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 29 #define CONFIG_ENV_OVERWRITE 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 33 34 #define CONFIG_SPL_FLUSH_IMAGE 35 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 36 #define CONFIG_SYS_TEXT_BASE 0x00201000 37 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 38 #define CONFIG_SPL_PAD_TO 0x40000 39 #define CONFIG_SPL_MAX_SIZE 0x28000 40 #define RESET_VECTOR_OFFSET 0x27FFC 41 #define BOOT_PAGE_OFFSET 0x27000 42 #ifdef CONFIG_SPL_BUILD 43 #define CONFIG_SPL_SKIP_RELOCATE 44 #define CONFIG_SPL_COMMON_INIT_DDR 45 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 46 #endif 47 48 #ifdef CONFIG_NAND 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 50 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 51 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 52 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg 55 #define CONFIG_SPL_NAND_BOOT 56 #endif 57 58 #ifdef CONFIG_SPIFLASH 59 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 60 #define CONFIG_SPL_SPI_FLASH_MINIMAL 61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 65 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 66 #ifndef CONFIG_SPL_BUILD 67 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 68 #endif 69 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg 70 #define CONFIG_SPL_SPI_BOOT 71 #endif 72 73 #ifdef CONFIG_SDCARD 74 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 75 #define CONFIG_SPL_MMC_MINIMAL 76 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 77 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 78 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 79 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 80 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 81 #ifndef CONFIG_SPL_BUILD 82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 83 #endif 84 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg 85 #define CONFIG_SPL_MMC_BOOT 86 #endif 87 88 #endif /* CONFIG_RAMBOOT_PBL */ 89 90 #define CONFIG_SRIO_PCIE_BOOT_MASTER 91 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 92 /* Set 1M boot space */ 93 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 94 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 95 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 96 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 97 #endif 98 99 #ifndef CONFIG_SYS_TEXT_BASE 100 #define CONFIG_SYS_TEXT_BASE 0xeff40000 101 #endif 102 103 #ifndef CONFIG_RESET_VECTOR_ADDRESS 104 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 105 #endif 106 107 /* 108 * These can be toggled for performance analysis, otherwise use default. 109 */ 110 #define CONFIG_SYS_CACHE_STASHING 111 #define CONFIG_BTB /* toggle branch predition */ 112 #define CONFIG_DDR_ECC 113 #ifdef CONFIG_DDR_ECC 114 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 115 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 116 #endif 117 118 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 119 #define CONFIG_SYS_MEMTEST_END 0x00400000 120 #define CONFIG_SYS_ALT_MEMTEST 121 122 #ifdef CONFIG_MTD_NOR_FLASH 123 #define CONFIG_FLASH_CFI_DRIVER 124 #define CONFIG_SYS_FLASH_CFI 125 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 126 #endif 127 128 #if defined(CONFIG_SPIFLASH) 129 #define CONFIG_SYS_EXTRA_ENV_RELOC 130 #define CONFIG_ENV_SPI_BUS 0 131 #define CONFIG_ENV_SPI_CS 0 132 #define CONFIG_ENV_SPI_MAX_HZ 10000000 133 #define CONFIG_ENV_SPI_MODE 0 134 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 135 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 136 #define CONFIG_ENV_SECT_SIZE 0x10000 137 #elif defined(CONFIG_SDCARD) 138 #define CONFIG_SYS_EXTRA_ENV_RELOC 139 #define CONFIG_SYS_MMC_ENV_DEV 0 140 #define CONFIG_ENV_SIZE 0x2000 141 #define CONFIG_ENV_OFFSET (512 * 0x800) 142 #elif defined(CONFIG_NAND) 143 #define CONFIG_SYS_EXTRA_ENV_RELOC 144 #define CONFIG_ENV_SIZE 0x2000 145 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 146 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 147 #define CONFIG_ENV_IS_IN_REMOTE 148 #define CONFIG_ENV_ADDR 0xffe20000 149 #define CONFIG_ENV_SIZE 0x2000 150 #elif defined(CONFIG_ENV_IS_NOWHERE) 151 #define CONFIG_ENV_SIZE 0x2000 152 #else 153 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 154 #define CONFIG_ENV_SIZE 0x2000 155 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 156 #endif 157 158 #ifndef __ASSEMBLY__ 159 unsigned long get_board_sys_clk(void); 160 unsigned long get_board_ddr_clk(void); 161 #endif 162 163 #define CONFIG_SYS_CLK_FREQ 66660000 164 #define CONFIG_DDR_CLK_FREQ 133330000 165 166 /* 167 * Config the L3 Cache as L3 SRAM 168 */ 169 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 170 #define CONFIG_SYS_L3_SIZE (512 << 10) 171 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 172 #ifdef CONFIG_RAMBOOT_PBL 173 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 174 #endif 175 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 176 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 177 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 178 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 179 180 #define CONFIG_SYS_DCSRBAR 0xf0000000 181 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 182 183 /* EEPROM */ 184 #define CONFIG_ID_EEPROM 185 #define CONFIG_SYS_I2C_EEPROM_NXID 186 #define CONFIG_SYS_EEPROM_BUS_NUM 0 187 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 188 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 189 190 /* 191 * DDR Setup 192 */ 193 #define CONFIG_VERY_BIG_RAM 194 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 195 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 196 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 197 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 198 #define CONFIG_DDR_SPD 199 #undef CONFIG_FSL_DDR_INTERACTIVE 200 #define CONFIG_SYS_SPD_BUS_NUM 0 201 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 202 #define SPD_EEPROM_ADDRESS1 0x51 203 #define SPD_EEPROM_ADDRESS2 0x52 204 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 205 #define CTRL_INTLV_PREFERED cacheline 206 207 /* 208 * IFC Definitions 209 */ 210 #define CONFIG_SYS_FLASH_BASE 0xe8000000 211 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 212 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 213 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 214 CSPR_PORT_SIZE_16 | \ 215 CSPR_MSEL_NOR | \ 216 CSPR_V) 217 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 218 219 /* NOR Flash Timing Params */ 220 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 221 222 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 223 FTIM0_NOR_TEADC(0x5) | \ 224 FTIM0_NOR_TEAHC(0x5)) 225 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 226 FTIM1_NOR_TRAD_NOR(0x1A) |\ 227 FTIM1_NOR_TSEQRAD_NOR(0x13)) 228 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 229 FTIM2_NOR_TCH(0x4) | \ 230 FTIM2_NOR_TWPH(0x0E) | \ 231 FTIM2_NOR_TWP(0x1c)) 232 #define CONFIG_SYS_NOR_FTIM3 0x0 233 234 #define CONFIG_SYS_FLASH_QUIET_TEST 235 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 236 237 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 238 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 239 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 240 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 241 #define CONFIG_SYS_FLASH_EMPTY_INFO 242 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 243 244 /* CPLD on IFC */ 245 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 246 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 247 #define CONFIG_SYS_CSPR2_EXT (0xf) 248 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 249 | CSPR_PORT_SIZE_8 \ 250 | CSPR_MSEL_GPCM \ 251 | CSPR_V) 252 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 253 #define CONFIG_SYS_CSOR2 0x0 254 255 /* CPLD Timing parameters for IFC CS2 */ 256 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 257 FTIM0_GPCM_TEADC(0x0e) | \ 258 FTIM0_GPCM_TEAHC(0x0e)) 259 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 260 FTIM1_GPCM_TRAD(0x1f)) 261 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 262 FTIM2_GPCM_TCH(0x8) | \ 263 FTIM2_GPCM_TWP(0x1f)) 264 #define CONFIG_SYS_CS2_FTIM3 0x0 265 266 /* NAND Flash on IFC */ 267 #define CONFIG_NAND_FSL_IFC 268 #define CONFIG_SYS_NAND_BASE 0xff800000 269 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 270 271 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 272 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 273 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 274 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 275 | CSPR_V) 276 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 277 278 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 279 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 280 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 281 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 282 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 283 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 284 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 285 286 #define CONFIG_SYS_NAND_ONFI_DETECTION 287 288 /* ONFI NAND Flash mode0 Timing Params */ 289 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 290 FTIM0_NAND_TWP(0x18) | \ 291 FTIM0_NAND_TWCHT(0x07) | \ 292 FTIM0_NAND_TWH(0x0a)) 293 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 294 FTIM1_NAND_TWBE(0x39) | \ 295 FTIM1_NAND_TRR(0x0e) | \ 296 FTIM1_NAND_TRP(0x18)) 297 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 298 FTIM2_NAND_TREH(0x0a) | \ 299 FTIM2_NAND_TWHRE(0x1e)) 300 #define CONFIG_SYS_NAND_FTIM3 0x0 301 302 #define CONFIG_SYS_NAND_DDR_LAW 11 303 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 304 #define CONFIG_SYS_MAX_NAND_DEVICE 1 305 #define CONFIG_CMD_NAND 306 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 307 308 #if defined(CONFIG_NAND) 309 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 310 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 311 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 312 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 313 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 314 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 315 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 316 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 317 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 318 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 319 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 320 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 321 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 322 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 323 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 324 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 325 #else 326 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 327 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 328 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 329 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 330 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 331 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 332 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 333 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 334 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 335 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 336 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 337 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 338 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 339 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 340 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 341 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 342 #endif 343 344 #if defined(CONFIG_RAMBOOT_PBL) 345 #define CONFIG_SYS_RAMBOOT 346 #endif 347 348 #ifdef CONFIG_SPL_BUILD 349 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 350 #else 351 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 352 #endif 353 354 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 355 #define CONFIG_MISC_INIT_R 356 #define CONFIG_HWCONFIG 357 358 /* define to use L1 as initial stack */ 359 #define CONFIG_L1_INIT_RAM 360 #define CONFIG_SYS_INIT_RAM_LOCK 361 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 362 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 363 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 364 /* The assembler doesn't like typecast */ 365 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 366 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 367 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 368 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 369 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 370 GENERATED_GBL_DATA_SIZE) 371 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 372 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 373 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 374 375 /* 376 * Serial Port 377 */ 378 #define CONFIG_CONS_INDEX 1 379 #define CONFIG_SYS_NS16550_SERIAL 380 #define CONFIG_SYS_NS16550_REG_SIZE 1 381 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 382 #define CONFIG_SYS_BAUDRATE_TABLE \ 383 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 384 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 385 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 386 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 387 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 388 389 /* 390 * I2C 391 */ 392 #define CONFIG_SYS_I2C 393 #define CONFIG_SYS_I2C_FSL 394 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 395 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 396 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 397 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 398 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 399 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 400 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 401 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 402 #define CONFIG_SYS_FSL_I2C_SPEED 100000 403 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 404 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 405 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 406 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 407 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 408 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 409 #define I2C_MUX_CH_DEFAULT 0x8 410 411 #define I2C_MUX_CH_VOL_MONITOR 0xa 412 413 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 414 #ifndef CONFIG_SPL_BUILD 415 #define CONFIG_VID 416 #endif 417 #define CONFIG_VOL_MONITOR_IR36021_SET 418 #define CONFIG_VOL_MONITOR_IR36021_READ 419 /* The lowest and highest voltage allowed for T208xRDB */ 420 #define VDD_MV_MIN 819 421 #define VDD_MV_MAX 1212 422 423 /* 424 * RapidIO 425 */ 426 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 427 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 428 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 429 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 430 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 431 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 432 /* 433 * for slave u-boot IMAGE instored in master memory space, 434 * PHYS must be aligned based on the SIZE 435 */ 436 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 437 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 438 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 439 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 440 /* 441 * for slave UCODE and ENV instored in master memory space, 442 * PHYS must be aligned based on the SIZE 443 */ 444 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 445 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 446 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 447 448 /* slave core release by master*/ 449 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 450 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 451 452 /* 453 * SRIO_PCIE_BOOT - SLAVE 454 */ 455 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 456 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 457 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 458 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 459 #endif 460 461 /* 462 * eSPI - Enhanced SPI 463 */ 464 #ifdef CONFIG_SPI_FLASH 465 #define CONFIG_SPI_FLASH_BAR 466 #define CONFIG_SF_DEFAULT_SPEED 10000000 467 #define CONFIG_SF_DEFAULT_MODE 0 468 #endif 469 470 /* 471 * General PCI 472 * Memory space is mapped 1-1, but I/O space must start from 0. 473 */ 474 #define CONFIG_PCIE1 /* PCIE controller 1 */ 475 #define CONFIG_PCIE2 /* PCIE controller 2 */ 476 #define CONFIG_PCIE3 /* PCIE controller 3 */ 477 #define CONFIG_PCIE4 /* PCIE controller 4 */ 478 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 479 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 480 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 481 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 482 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 483 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 484 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 485 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 486 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 487 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 488 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 489 490 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 491 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 492 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 493 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 494 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 495 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 496 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 497 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 498 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 499 500 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 501 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 502 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 503 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 504 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 505 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 506 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 507 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 508 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 509 510 /* controller 4, Base address 203000 */ 511 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 512 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 513 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 514 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 515 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 516 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 517 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 518 519 #ifdef CONFIG_PCI 520 #define CONFIG_PCI_INDIRECT_BRIDGE 521 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 522 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 523 #endif 524 525 /* Qman/Bman */ 526 #ifndef CONFIG_NOBQFMAN 527 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 528 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 529 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 530 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 531 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 532 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 533 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 534 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 535 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 536 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 537 CONFIG_SYS_BMAN_CENA_SIZE) 538 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 539 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 540 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 541 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 542 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 543 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 544 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 545 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 546 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 547 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 548 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 549 CONFIG_SYS_QMAN_CENA_SIZE) 550 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 551 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 552 553 #define CONFIG_SYS_DPAA_FMAN 554 #define CONFIG_SYS_DPAA_PME 555 #define CONFIG_SYS_PMAN 556 #define CONFIG_SYS_DPAA_DCE 557 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 558 #define CONFIG_SYS_INTERLAKEN 559 560 /* Default address of microcode for the Linux Fman driver */ 561 #if defined(CONFIG_SPIFLASH) 562 /* 563 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 564 * env, so we got 0x110000. 565 */ 566 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 567 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 568 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 569 #define CONFIG_CORTINA_FW_ADDR 0x120000 570 571 #elif defined(CONFIG_SDCARD) 572 /* 573 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 574 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 575 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 576 */ 577 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 578 #define CONFIG_SYS_CORTINA_FW_IN_MMC 579 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 580 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 581 582 #elif defined(CONFIG_NAND) 583 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 584 #define CONFIG_SYS_CORTINA_FW_IN_NAND 585 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 586 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 587 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 588 /* 589 * Slave has no ucode locally, it can fetch this from remote. When implementing 590 * in two corenet boards, slave's ucode could be stored in master's memory 591 * space, the address can be mapped from slave TLB->slave LAW-> 592 * slave SRIO or PCIE outbound window->master inbound window-> 593 * master LAW->the ucode address in master's memory space. 594 */ 595 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 596 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 597 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 598 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 599 #else 600 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 601 #define CONFIG_SYS_CORTINA_FW_IN_NOR 602 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 603 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 604 #endif 605 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 606 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 607 #endif /* CONFIG_NOBQFMAN */ 608 609 #ifdef CONFIG_SYS_DPAA_FMAN 610 #define CONFIG_FMAN_ENET 611 #define CONFIG_PHYLIB_10G 612 #define CONFIG_PHY_AQUANTIA 613 #define CONFIG_PHY_CORTINA 614 #define CONFIG_PHY_REALTEK 615 #define CONFIG_CORTINA_FW_LENGTH 0x40000 616 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 617 #define RGMII_PHY2_ADDR 0x02 618 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 619 #define CORTINA_PHY_ADDR2 0x0d 620 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 621 #define FM1_10GEC4_PHY_ADDR 0x01 622 #endif 623 624 #ifdef CONFIG_FMAN_ENET 625 #define CONFIG_MII /* MII PHY management */ 626 #define CONFIG_ETHPRIME "FM1@DTSEC3" 627 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 628 #endif 629 630 /* 631 * SATA 632 */ 633 #ifdef CONFIG_FSL_SATA_V2 634 #define CONFIG_LIBATA 635 #define CONFIG_FSL_SATA 636 #define CONFIG_SYS_SATA_MAX_DEVICE 2 637 #define CONFIG_SATA1 638 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 639 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 640 #define CONFIG_SATA2 641 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 642 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 643 #define CONFIG_LBA48 644 #endif 645 646 /* 647 * USB 648 */ 649 #ifdef CONFIG_USB_EHCI_HCD 650 #define CONFIG_USB_EHCI_FSL 651 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 652 #define CONFIG_HAS_FSL_DR_USB 653 #endif 654 655 /* 656 * SDHC 657 */ 658 #ifdef CONFIG_MMC 659 #define CONFIG_FSL_ESDHC 660 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 661 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 662 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 663 #endif 664 665 /* 666 * Dynamic MTD Partition support with mtdparts 667 */ 668 #ifdef CONFIG_MTD_NOR_FLASH 669 #define CONFIG_MTD_DEVICE 670 #define CONFIG_MTD_PARTITIONS 671 #define CONFIG_FLASH_CFI_MTD 672 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 673 "spi0=spife110000.1" 674 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 675 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 676 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 677 "1m(uboot),5m(kernel),128k(dtb),-(user)" 678 #endif 679 680 /* 681 * Environment 682 */ 683 684 /* 685 * Command line configuration. 686 */ 687 #define CONFIG_CMD_REGINFO 688 689 #ifdef CONFIG_PCI 690 #define CONFIG_CMD_PCI 691 #endif 692 693 /* 694 * Miscellaneous configurable options 695 */ 696 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 697 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 698 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 699 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 700 #ifdef CONFIG_CMD_KGDB 701 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 702 #else 703 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 704 #endif 705 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 706 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 707 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 708 709 /* 710 * For booting Linux, the board info and command line data 711 * have to be in the first 64 MB of memory, since this is 712 * the maximum mapped by the Linux kernel during initialization. 713 */ 714 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 715 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 716 717 #ifdef CONFIG_CMD_KGDB 718 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 719 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 720 #endif 721 722 /* 723 * Environment Configuration 724 */ 725 #define CONFIG_ROOTPATH "/opt/nfsroot" 726 #define CONFIG_BOOTFILE "uImage" 727 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 728 729 /* default location for tftp and bootm */ 730 #define CONFIG_LOADADDR 1000000 731 #define __USB_PHY_TYPE utmi 732 733 #define CONFIG_EXTRA_ENV_SETTINGS \ 734 "hwconfig=fsl_ddr:" \ 735 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 736 "bank_intlv=auto;" \ 737 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 738 "netdev=eth0\0" \ 739 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 740 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 741 "tftpflash=tftpboot $loadaddr $uboot && " \ 742 "protect off $ubootaddr +$filesize && " \ 743 "erase $ubootaddr +$filesize && " \ 744 "cp.b $loadaddr $ubootaddr $filesize && " \ 745 "protect on $ubootaddr +$filesize && " \ 746 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 747 "consoledev=ttyS0\0" \ 748 "ramdiskaddr=2000000\0" \ 749 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 750 "fdtaddr=1e00000\0" \ 751 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 752 "bdev=sda3\0" 753 754 /* 755 * For emulation this causes u-boot to jump to the start of the 756 * proof point app code automatically 757 */ 758 #define CONFIG_PROOF_POINTS \ 759 "setenv bootargs root=/dev/$bdev rw " \ 760 "console=$consoledev,$baudrate $othbootargs;" \ 761 "cpu 1 release 0x29000000 - - -;" \ 762 "cpu 2 release 0x29000000 - - -;" \ 763 "cpu 3 release 0x29000000 - - -;" \ 764 "cpu 4 release 0x29000000 - - -;" \ 765 "cpu 5 release 0x29000000 - - -;" \ 766 "cpu 6 release 0x29000000 - - -;" \ 767 "cpu 7 release 0x29000000 - - -;" \ 768 "go 0x29000000" 769 770 #define CONFIG_HVBOOT \ 771 "setenv bootargs config-addr=0x60000000; " \ 772 "bootm 0x01000000 - 0x00f00000" 773 774 #define CONFIG_ALU \ 775 "setenv bootargs root=/dev/$bdev rw " \ 776 "console=$consoledev,$baudrate $othbootargs;" \ 777 "cpu 1 release 0x01000000 - - -;" \ 778 "cpu 2 release 0x01000000 - - -;" \ 779 "cpu 3 release 0x01000000 - - -;" \ 780 "cpu 4 release 0x01000000 - - -;" \ 781 "cpu 5 release 0x01000000 - - -;" \ 782 "cpu 6 release 0x01000000 - - -;" \ 783 "cpu 7 release 0x01000000 - - -;" \ 784 "go 0x01000000" 785 786 #define CONFIG_LINUX \ 787 "setenv bootargs root=/dev/ram rw " \ 788 "console=$consoledev,$baudrate $othbootargs;" \ 789 "setenv ramdiskaddr 0x02000000;" \ 790 "setenv fdtaddr 0x00c00000;" \ 791 "setenv loadaddr 0x1000000;" \ 792 "bootm $loadaddr $ramdiskaddr $fdtaddr" 793 794 #define CONFIG_HDBOOT \ 795 "setenv bootargs root=/dev/$bdev rw " \ 796 "console=$consoledev,$baudrate $othbootargs;" \ 797 "tftp $loadaddr $bootfile;" \ 798 "tftp $fdtaddr $fdtfile;" \ 799 "bootm $loadaddr - $fdtaddr" 800 801 #define CONFIG_NFSBOOTCOMMAND \ 802 "setenv bootargs root=/dev/nfs rw " \ 803 "nfsroot=$serverip:$rootpath " \ 804 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 805 "console=$consoledev,$baudrate $othbootargs;" \ 806 "tftp $loadaddr $bootfile;" \ 807 "tftp $fdtaddr $fdtfile;" \ 808 "bootm $loadaddr - $fdtaddr" 809 810 #define CONFIG_RAMBOOTCOMMAND \ 811 "setenv bootargs root=/dev/ram rw " \ 812 "console=$consoledev,$baudrate $othbootargs;" \ 813 "tftp $ramdiskaddr $ramdiskfile;" \ 814 "tftp $loadaddr $bootfile;" \ 815 "tftp $fdtaddr $fdtfile;" \ 816 "bootm $loadaddr $ramdiskaddr $fdtaddr" 817 818 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 819 820 #include <asm/fsl_secure_boot.h> 821 822 #endif /* __T2080RDB_H */ 823