1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 15 #define CONFIG_FSL_SATA_V2 16 17 /* High Level Configuration Options */ 18 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 19 #define CONFIG_MP /* support multiple processors */ 20 #define CONFIG_ENABLE_36BIT_PHYS 21 22 #ifdef CONFIG_PHYS_64BIT 23 #define CONFIG_ADDR_MAP 1 24 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 25 #endif 26 27 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 28 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 29 #define CONFIG_ENV_OVERWRITE 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 33 34 #define CONFIG_SPL_FLUSH_IMAGE 35 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 36 #define CONFIG_SYS_TEXT_BASE 0x00201000 37 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 38 #define CONFIG_SPL_PAD_TO 0x40000 39 #define CONFIG_SPL_MAX_SIZE 0x28000 40 #define RESET_VECTOR_OFFSET 0x27FFC 41 #define BOOT_PAGE_OFFSET 0x27000 42 #ifdef CONFIG_SPL_BUILD 43 #define CONFIG_SPL_SKIP_RELOCATE 44 #define CONFIG_SPL_COMMON_INIT_DDR 45 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 46 #endif 47 48 #ifdef CONFIG_NAND 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 50 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 51 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 52 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg 55 #define CONFIG_SPL_NAND_BOOT 56 #endif 57 58 #ifdef CONFIG_SPIFLASH 59 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 60 #define CONFIG_SPL_SPI_FLASH_MINIMAL 61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 65 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 66 #ifndef CONFIG_SPL_BUILD 67 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 68 #endif 69 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg 70 #define CONFIG_SPL_SPI_BOOT 71 #endif 72 73 #ifdef CONFIG_SDCARD 74 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 75 #define CONFIG_SPL_MMC_MINIMAL 76 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 77 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 78 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 79 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 80 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 81 #ifndef CONFIG_SPL_BUILD 82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 83 #endif 84 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg 85 #define CONFIG_SPL_MMC_BOOT 86 #endif 87 88 #endif /* CONFIG_RAMBOOT_PBL */ 89 90 #define CONFIG_SRIO_PCIE_BOOT_MASTER 91 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 92 /* Set 1M boot space */ 93 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 94 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 95 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 96 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 97 #endif 98 99 #ifndef CONFIG_SYS_TEXT_BASE 100 #define CONFIG_SYS_TEXT_BASE 0xeff40000 101 #endif 102 103 #ifndef CONFIG_RESET_VECTOR_ADDRESS 104 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 105 #endif 106 107 /* 108 * These can be toggled for performance analysis, otherwise use default. 109 */ 110 #define CONFIG_SYS_CACHE_STASHING 111 #define CONFIG_BTB /* toggle branch predition */ 112 #define CONFIG_DDR_ECC 113 #ifdef CONFIG_DDR_ECC 114 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 115 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 116 #endif 117 118 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 119 #define CONFIG_SYS_MEMTEST_END 0x00400000 120 #define CONFIG_SYS_ALT_MEMTEST 121 122 #ifdef CONFIG_MTD_NOR_FLASH 123 #define CONFIG_FLASH_CFI_DRIVER 124 #define CONFIG_SYS_FLASH_CFI 125 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 126 #endif 127 128 #if defined(CONFIG_SPIFLASH) 129 #define CONFIG_SYS_EXTRA_ENV_RELOC 130 #define CONFIG_ENV_IS_IN_SPI_FLASH 131 #define CONFIG_ENV_SPI_BUS 0 132 #define CONFIG_ENV_SPI_CS 0 133 #define CONFIG_ENV_SPI_MAX_HZ 10000000 134 #define CONFIG_ENV_SPI_MODE 0 135 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 136 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 137 #define CONFIG_ENV_SECT_SIZE 0x10000 138 #elif defined(CONFIG_SDCARD) 139 #define CONFIG_SYS_EXTRA_ENV_RELOC 140 #define CONFIG_SYS_MMC_ENV_DEV 0 141 #define CONFIG_ENV_SIZE 0x2000 142 #define CONFIG_ENV_OFFSET (512 * 0x800) 143 #elif defined(CONFIG_NAND) 144 #define CONFIG_SYS_EXTRA_ENV_RELOC 145 #define CONFIG_ENV_SIZE 0x2000 146 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 147 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 148 #define CONFIG_ENV_IS_IN_REMOTE 149 #define CONFIG_ENV_ADDR 0xffe20000 150 #define CONFIG_ENV_SIZE 0x2000 151 #elif defined(CONFIG_ENV_IS_NOWHERE) 152 #define CONFIG_ENV_SIZE 0x2000 153 #else 154 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 155 #define CONFIG_ENV_SIZE 0x2000 156 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 157 #endif 158 159 #ifndef __ASSEMBLY__ 160 unsigned long get_board_sys_clk(void); 161 unsigned long get_board_ddr_clk(void); 162 #endif 163 164 #define CONFIG_SYS_CLK_FREQ 66660000 165 #define CONFIG_DDR_CLK_FREQ 133330000 166 167 /* 168 * Config the L3 Cache as L3 SRAM 169 */ 170 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 171 #define CONFIG_SYS_L3_SIZE (512 << 10) 172 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 173 #ifdef CONFIG_RAMBOOT_PBL 174 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 175 #endif 176 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 177 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 178 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 179 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 180 181 #define CONFIG_SYS_DCSRBAR 0xf0000000 182 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 183 184 /* EEPROM */ 185 #define CONFIG_ID_EEPROM 186 #define CONFIG_SYS_I2C_EEPROM_NXID 187 #define CONFIG_SYS_EEPROM_BUS_NUM 0 188 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 189 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 190 191 /* 192 * DDR Setup 193 */ 194 #define CONFIG_VERY_BIG_RAM 195 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 196 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 197 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 198 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 199 #define CONFIG_DDR_SPD 200 #undef CONFIG_FSL_DDR_INTERACTIVE 201 #define CONFIG_SYS_SPD_BUS_NUM 0 202 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 203 #define SPD_EEPROM_ADDRESS1 0x51 204 #define SPD_EEPROM_ADDRESS2 0x52 205 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 206 #define CTRL_INTLV_PREFERED cacheline 207 208 /* 209 * IFC Definitions 210 */ 211 #define CONFIG_SYS_FLASH_BASE 0xe8000000 212 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 213 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 214 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 215 CSPR_PORT_SIZE_16 | \ 216 CSPR_MSEL_NOR | \ 217 CSPR_V) 218 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 219 220 /* NOR Flash Timing Params */ 221 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 222 223 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 224 FTIM0_NOR_TEADC(0x5) | \ 225 FTIM0_NOR_TEAHC(0x5)) 226 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 227 FTIM1_NOR_TRAD_NOR(0x1A) |\ 228 FTIM1_NOR_TSEQRAD_NOR(0x13)) 229 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 230 FTIM2_NOR_TCH(0x4) | \ 231 FTIM2_NOR_TWPH(0x0E) | \ 232 FTIM2_NOR_TWP(0x1c)) 233 #define CONFIG_SYS_NOR_FTIM3 0x0 234 235 #define CONFIG_SYS_FLASH_QUIET_TEST 236 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 237 238 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 239 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 240 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 241 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 242 #define CONFIG_SYS_FLASH_EMPTY_INFO 243 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 244 245 /* CPLD on IFC */ 246 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 247 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 248 #define CONFIG_SYS_CSPR2_EXT (0xf) 249 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 250 | CSPR_PORT_SIZE_8 \ 251 | CSPR_MSEL_GPCM \ 252 | CSPR_V) 253 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 254 #define CONFIG_SYS_CSOR2 0x0 255 256 /* CPLD Timing parameters for IFC CS2 */ 257 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 258 FTIM0_GPCM_TEADC(0x0e) | \ 259 FTIM0_GPCM_TEAHC(0x0e)) 260 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 261 FTIM1_GPCM_TRAD(0x1f)) 262 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 263 FTIM2_GPCM_TCH(0x8) | \ 264 FTIM2_GPCM_TWP(0x1f)) 265 #define CONFIG_SYS_CS2_FTIM3 0x0 266 267 /* NAND Flash on IFC */ 268 #define CONFIG_NAND_FSL_IFC 269 #define CONFIG_SYS_NAND_BASE 0xff800000 270 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 271 272 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 273 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 274 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 275 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 276 | CSPR_V) 277 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 278 279 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 280 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 281 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 282 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 283 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 284 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 285 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 286 287 #define CONFIG_SYS_NAND_ONFI_DETECTION 288 289 /* ONFI NAND Flash mode0 Timing Params */ 290 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 291 FTIM0_NAND_TWP(0x18) | \ 292 FTIM0_NAND_TWCHT(0x07) | \ 293 FTIM0_NAND_TWH(0x0a)) 294 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 295 FTIM1_NAND_TWBE(0x39) | \ 296 FTIM1_NAND_TRR(0x0e) | \ 297 FTIM1_NAND_TRP(0x18)) 298 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 299 FTIM2_NAND_TREH(0x0a) | \ 300 FTIM2_NAND_TWHRE(0x1e)) 301 #define CONFIG_SYS_NAND_FTIM3 0x0 302 303 #define CONFIG_SYS_NAND_DDR_LAW 11 304 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 305 #define CONFIG_SYS_MAX_NAND_DEVICE 1 306 #define CONFIG_CMD_NAND 307 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 308 309 #if defined(CONFIG_NAND) 310 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 311 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 312 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 313 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 314 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 315 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 316 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 317 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 318 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 319 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 320 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 321 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 322 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 323 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 324 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 325 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 326 #else 327 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 328 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 329 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 330 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 331 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 332 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 333 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 334 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 335 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 336 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 337 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 338 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 339 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 340 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 341 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 342 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 343 #endif 344 345 #if defined(CONFIG_RAMBOOT_PBL) 346 #define CONFIG_SYS_RAMBOOT 347 #endif 348 349 #ifdef CONFIG_SPL_BUILD 350 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 351 #else 352 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 353 #endif 354 355 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 356 #define CONFIG_MISC_INIT_R 357 #define CONFIG_HWCONFIG 358 359 /* define to use L1 as initial stack */ 360 #define CONFIG_L1_INIT_RAM 361 #define CONFIG_SYS_INIT_RAM_LOCK 362 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 363 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 364 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 365 /* The assembler doesn't like typecast */ 366 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 367 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 368 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 369 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 370 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 371 GENERATED_GBL_DATA_SIZE) 372 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 373 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 374 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 375 376 /* 377 * Serial Port 378 */ 379 #define CONFIG_CONS_INDEX 1 380 #define CONFIG_SYS_NS16550_SERIAL 381 #define CONFIG_SYS_NS16550_REG_SIZE 1 382 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 383 #define CONFIG_SYS_BAUDRATE_TABLE \ 384 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 385 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 386 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 387 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 388 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 389 390 /* 391 * I2C 392 */ 393 #define CONFIG_SYS_I2C 394 #define CONFIG_SYS_I2C_FSL 395 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 396 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 397 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 398 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 399 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 400 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 401 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 402 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 403 #define CONFIG_SYS_FSL_I2C_SPEED 100000 404 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 405 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 406 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 407 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 408 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 409 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 410 #define I2C_MUX_CH_DEFAULT 0x8 411 412 #define I2C_MUX_CH_VOL_MONITOR 0xa 413 414 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 415 #ifndef CONFIG_SPL_BUILD 416 #define CONFIG_VID 417 #endif 418 #define CONFIG_VOL_MONITOR_IR36021_SET 419 #define CONFIG_VOL_MONITOR_IR36021_READ 420 /* The lowest and highest voltage allowed for T208xRDB */ 421 #define VDD_MV_MIN 819 422 #define VDD_MV_MAX 1212 423 424 /* 425 * RapidIO 426 */ 427 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 428 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 429 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 430 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 431 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 432 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 433 /* 434 * for slave u-boot IMAGE instored in master memory space, 435 * PHYS must be aligned based on the SIZE 436 */ 437 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 438 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 439 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 440 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 441 /* 442 * for slave UCODE and ENV instored in master memory space, 443 * PHYS must be aligned based on the SIZE 444 */ 445 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 446 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 447 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 448 449 /* slave core release by master*/ 450 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 451 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 452 453 /* 454 * SRIO_PCIE_BOOT - SLAVE 455 */ 456 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 457 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 458 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 459 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 460 #endif 461 462 /* 463 * eSPI - Enhanced SPI 464 */ 465 #ifdef CONFIG_SPI_FLASH 466 #define CONFIG_SPI_FLASH_BAR 467 #define CONFIG_SF_DEFAULT_SPEED 10000000 468 #define CONFIG_SF_DEFAULT_MODE 0 469 #endif 470 471 /* 472 * General PCI 473 * Memory space is mapped 1-1, but I/O space must start from 0. 474 */ 475 #define CONFIG_PCIE1 /* PCIE controller 1 */ 476 #define CONFIG_PCIE2 /* PCIE controller 2 */ 477 #define CONFIG_PCIE3 /* PCIE controller 3 */ 478 #define CONFIG_PCIE4 /* PCIE controller 4 */ 479 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 480 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 481 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 482 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 483 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 484 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 485 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 486 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 487 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 488 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 489 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 490 491 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 492 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 493 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 494 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 495 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 496 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 497 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 498 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 499 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 500 501 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 502 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 503 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 504 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 505 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 506 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 507 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 508 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 509 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 510 511 /* controller 4, Base address 203000 */ 512 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 513 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 514 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 515 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 516 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 517 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 518 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 519 520 #ifdef CONFIG_PCI 521 #define CONFIG_PCI_INDIRECT_BRIDGE 522 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 523 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 524 #endif 525 526 /* Qman/Bman */ 527 #ifndef CONFIG_NOBQFMAN 528 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 529 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 530 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 531 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 532 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 533 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 534 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 535 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 536 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 537 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 538 CONFIG_SYS_BMAN_CENA_SIZE) 539 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 540 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 541 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 542 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 543 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 544 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 545 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 546 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 547 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 548 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 549 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 550 CONFIG_SYS_QMAN_CENA_SIZE) 551 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 552 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 553 554 #define CONFIG_SYS_DPAA_FMAN 555 #define CONFIG_SYS_DPAA_PME 556 #define CONFIG_SYS_PMAN 557 #define CONFIG_SYS_DPAA_DCE 558 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 559 #define CONFIG_SYS_INTERLAKEN 560 561 /* Default address of microcode for the Linux Fman driver */ 562 #if defined(CONFIG_SPIFLASH) 563 /* 564 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 565 * env, so we got 0x110000. 566 */ 567 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 568 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 569 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 570 #define CONFIG_CORTINA_FW_ADDR 0x120000 571 572 #elif defined(CONFIG_SDCARD) 573 /* 574 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 575 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 576 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 577 */ 578 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 579 #define CONFIG_SYS_CORTINA_FW_IN_MMC 580 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 581 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 582 583 #elif defined(CONFIG_NAND) 584 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 585 #define CONFIG_SYS_CORTINA_FW_IN_NAND 586 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 587 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 588 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 589 /* 590 * Slave has no ucode locally, it can fetch this from remote. When implementing 591 * in two corenet boards, slave's ucode could be stored in master's memory 592 * space, the address can be mapped from slave TLB->slave LAW-> 593 * slave SRIO or PCIE outbound window->master inbound window-> 594 * master LAW->the ucode address in master's memory space. 595 */ 596 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 597 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 598 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 599 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 600 #else 601 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 602 #define CONFIG_SYS_CORTINA_FW_IN_NOR 603 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 604 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 605 #endif 606 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 607 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 608 #endif /* CONFIG_NOBQFMAN */ 609 610 #ifdef CONFIG_SYS_DPAA_FMAN 611 #define CONFIG_FMAN_ENET 612 #define CONFIG_PHYLIB_10G 613 #define CONFIG_PHY_AQUANTIA 614 #define CONFIG_PHY_CORTINA 615 #define CONFIG_PHY_REALTEK 616 #define CONFIG_CORTINA_FW_LENGTH 0x40000 617 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 618 #define RGMII_PHY2_ADDR 0x02 619 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 620 #define CORTINA_PHY_ADDR2 0x0d 621 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 622 #define FM1_10GEC4_PHY_ADDR 0x01 623 #endif 624 625 #ifdef CONFIG_FMAN_ENET 626 #define CONFIG_MII /* MII PHY management */ 627 #define CONFIG_ETHPRIME "FM1@DTSEC3" 628 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 629 #endif 630 631 /* 632 * SATA 633 */ 634 #ifdef CONFIG_FSL_SATA_V2 635 #define CONFIG_LIBATA 636 #define CONFIG_FSL_SATA 637 #define CONFIG_SYS_SATA_MAX_DEVICE 2 638 #define CONFIG_SATA1 639 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 640 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 641 #define CONFIG_SATA2 642 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 643 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 644 #define CONFIG_LBA48 645 #endif 646 647 /* 648 * USB 649 */ 650 #ifdef CONFIG_USB_EHCI_HCD 651 #define CONFIG_USB_EHCI_FSL 652 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 653 #define CONFIG_HAS_FSL_DR_USB 654 #endif 655 656 /* 657 * SDHC 658 */ 659 #ifdef CONFIG_MMC 660 #define CONFIG_FSL_ESDHC 661 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 662 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 663 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 664 #endif 665 666 /* 667 * Dynamic MTD Partition support with mtdparts 668 */ 669 #ifdef CONFIG_MTD_NOR_FLASH 670 #define CONFIG_MTD_DEVICE 671 #define CONFIG_MTD_PARTITIONS 672 #define CONFIG_FLASH_CFI_MTD 673 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 674 "spi0=spife110000.1" 675 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 676 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 677 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 678 "1m(uboot),5m(kernel),128k(dtb),-(user)" 679 #endif 680 681 /* 682 * Environment 683 */ 684 685 /* 686 * Command line configuration. 687 */ 688 #define CONFIG_CMD_REGINFO 689 690 #ifdef CONFIG_PCI 691 #define CONFIG_CMD_PCI 692 #endif 693 694 /* 695 * Miscellaneous configurable options 696 */ 697 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 698 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 699 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 700 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 701 #ifdef CONFIG_CMD_KGDB 702 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 703 #else 704 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 705 #endif 706 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 707 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 708 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 709 710 /* 711 * For booting Linux, the board info and command line data 712 * have to be in the first 64 MB of memory, since this is 713 * the maximum mapped by the Linux kernel during initialization. 714 */ 715 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 716 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 717 718 #ifdef CONFIG_CMD_KGDB 719 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 720 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 721 #endif 722 723 /* 724 * Environment Configuration 725 */ 726 #define CONFIG_ROOTPATH "/opt/nfsroot" 727 #define CONFIG_BOOTFILE "uImage" 728 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 729 730 /* default location for tftp and bootm */ 731 #define CONFIG_LOADADDR 1000000 732 #define __USB_PHY_TYPE utmi 733 734 #define CONFIG_EXTRA_ENV_SETTINGS \ 735 "hwconfig=fsl_ddr:" \ 736 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 737 "bank_intlv=auto;" \ 738 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 739 "netdev=eth0\0" \ 740 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 741 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 742 "tftpflash=tftpboot $loadaddr $uboot && " \ 743 "protect off $ubootaddr +$filesize && " \ 744 "erase $ubootaddr +$filesize && " \ 745 "cp.b $loadaddr $ubootaddr $filesize && " \ 746 "protect on $ubootaddr +$filesize && " \ 747 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 748 "consoledev=ttyS0\0" \ 749 "ramdiskaddr=2000000\0" \ 750 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 751 "fdtaddr=1e00000\0" \ 752 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 753 "bdev=sda3\0" 754 755 /* 756 * For emulation this causes u-boot to jump to the start of the 757 * proof point app code automatically 758 */ 759 #define CONFIG_PROOF_POINTS \ 760 "setenv bootargs root=/dev/$bdev rw " \ 761 "console=$consoledev,$baudrate $othbootargs;" \ 762 "cpu 1 release 0x29000000 - - -;" \ 763 "cpu 2 release 0x29000000 - - -;" \ 764 "cpu 3 release 0x29000000 - - -;" \ 765 "cpu 4 release 0x29000000 - - -;" \ 766 "cpu 5 release 0x29000000 - - -;" \ 767 "cpu 6 release 0x29000000 - - -;" \ 768 "cpu 7 release 0x29000000 - - -;" \ 769 "go 0x29000000" 770 771 #define CONFIG_HVBOOT \ 772 "setenv bootargs config-addr=0x60000000; " \ 773 "bootm 0x01000000 - 0x00f00000" 774 775 #define CONFIG_ALU \ 776 "setenv bootargs root=/dev/$bdev rw " \ 777 "console=$consoledev,$baudrate $othbootargs;" \ 778 "cpu 1 release 0x01000000 - - -;" \ 779 "cpu 2 release 0x01000000 - - -;" \ 780 "cpu 3 release 0x01000000 - - -;" \ 781 "cpu 4 release 0x01000000 - - -;" \ 782 "cpu 5 release 0x01000000 - - -;" \ 783 "cpu 6 release 0x01000000 - - -;" \ 784 "cpu 7 release 0x01000000 - - -;" \ 785 "go 0x01000000" 786 787 #define CONFIG_LINUX \ 788 "setenv bootargs root=/dev/ram rw " \ 789 "console=$consoledev,$baudrate $othbootargs;" \ 790 "setenv ramdiskaddr 0x02000000;" \ 791 "setenv fdtaddr 0x00c00000;" \ 792 "setenv loadaddr 0x1000000;" \ 793 "bootm $loadaddr $ramdiskaddr $fdtaddr" 794 795 #define CONFIG_HDBOOT \ 796 "setenv bootargs root=/dev/$bdev rw " \ 797 "console=$consoledev,$baudrate $othbootargs;" \ 798 "tftp $loadaddr $bootfile;" \ 799 "tftp $fdtaddr $fdtfile;" \ 800 "bootm $loadaddr - $fdtaddr" 801 802 #define CONFIG_NFSBOOTCOMMAND \ 803 "setenv bootargs root=/dev/nfs rw " \ 804 "nfsroot=$serverip:$rootpath " \ 805 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 806 "console=$consoledev,$baudrate $othbootargs;" \ 807 "tftp $loadaddr $bootfile;" \ 808 "tftp $fdtaddr $fdtfile;" \ 809 "bootm $loadaddr - $fdtaddr" 810 811 #define CONFIG_RAMBOOTCOMMAND \ 812 "setenv bootargs root=/dev/ram rw " \ 813 "console=$consoledev,$baudrate $othbootargs;" \ 814 "tftp $ramdiskaddr $ramdiskfile;" \ 815 "tftp $loadaddr $bootfile;" \ 816 "tftp $fdtaddr $fdtfile;" \ 817 "bootm $loadaddr $ramdiskaddr $fdtaddr" 818 819 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 820 821 #include <asm/fsl_secure_boot.h> 822 823 #endif /* __T2080RDB_H */ 824