1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 16 #define CONFIG_MMC 17 #define CONFIG_USB_EHCI 18 #if defined(CONFIG_PPC_T2080) 19 #define CONFIG_T2080QDS 20 #define CONFIG_FSL_SATA_V2 21 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 22 #define CONFIG_SRIO1 /* SRIO port 1 */ 23 #define CONFIG_SRIO2 /* SRIO port 2 */ 24 #elif defined(CONFIG_PPC_T2081) 25 #define CONFIG_T2081QDS 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_BOOKE 30 #define CONFIG_E500 /* BOOKE e500 family */ 31 #define CONFIG_E500MC /* BOOKE e500mc family */ 32 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 33 #define CONFIG_MP /* support multiple processors */ 34 #define CONFIG_ENABLE_36BIT_PHYS 35 36 #ifdef CONFIG_PHYS_64BIT 37 #define CONFIG_ADDR_MAP 1 38 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 39 #endif 40 41 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 42 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 43 #define CONFIG_FSL_IFC /* Enable IFC Support */ 44 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 45 #define CONFIG_FSL_LAW /* Use common FSL init code */ 46 #define CONFIG_ENV_OVERWRITE 47 48 #ifdef CONFIG_RAMBOOT_PBL 49 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 50 #if defined(CONFIG_PPC_T2080) 51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg 52 #elif defined(CONFIG_PPC_T2081) 53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg 54 #endif 55 56 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 57 #define CONFIG_SPL_ENV_SUPPORT 58 #define CONFIG_SPL_SERIAL_SUPPORT 59 #define CONFIG_SPL_FLUSH_IMAGE 60 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 61 #define CONFIG_SPL_LIBGENERIC_SUPPORT 62 #define CONFIG_SPL_LIBCOMMON_SUPPORT 63 #define CONFIG_SPL_I2C_SUPPORT 64 #define CONFIG_FSL_LAW /* Use common FSL init code */ 65 #define CONFIG_SYS_TEXT_BASE 0x00201000 66 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 67 #define CONFIG_SPL_PAD_TO 0x40000 68 #define CONFIG_SPL_MAX_SIZE 0x28000 69 #define RESET_VECTOR_OFFSET 0x27FFC 70 #define BOOT_PAGE_OFFSET 0x27000 71 #ifdef CONFIG_SPL_BUILD 72 #define CONFIG_SPL_SKIP_RELOCATE 73 #define CONFIG_SPL_COMMON_INIT_DDR 74 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 75 #define CONFIG_SYS_NO_FLASH 76 #endif 77 78 #ifdef CONFIG_NAND 79 #define CONFIG_SPL_NAND_SUPPORT 80 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 81 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 82 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 83 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 84 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 85 #define CONFIG_SPL_NAND_BOOT 86 #endif 87 88 #ifdef CONFIG_SPIFLASH 89 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 90 #define CONFIG_SPL_SPI_SUPPORT 91 #define CONFIG_SPL_SPI_FLASH_SUPPORT 92 #define CONFIG_SPL_SPI_FLASH_MINIMAL 93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 94 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 95 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 96 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 97 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 98 #ifndef CONFIG_SPL_BUILD 99 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 100 #endif 101 #define CONFIG_SPL_SPI_BOOT 102 #endif 103 104 #ifdef CONFIG_SDCARD 105 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 106 #define CONFIG_SPL_MMC_SUPPORT 107 #define CONFIG_SPL_MMC_MINIMAL 108 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 109 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 110 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 111 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 112 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 113 #ifndef CONFIG_SPL_BUILD 114 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 115 #endif 116 #define CONFIG_SPL_MMC_BOOT 117 #endif 118 119 #endif /* CONFIG_RAMBOOT_PBL */ 120 121 #define CONFIG_SRIO_PCIE_BOOT_MASTER 122 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 123 /* Set 1M boot space */ 124 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 125 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 126 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 127 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 128 #define CONFIG_SYS_NO_FLASH 129 #endif 130 131 #ifndef CONFIG_SYS_TEXT_BASE 132 #define CONFIG_SYS_TEXT_BASE 0xeff40000 133 #endif 134 135 #ifndef CONFIG_RESET_VECTOR_ADDRESS 136 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 137 #endif 138 139 /* 140 * These can be toggled for performance analysis, otherwise use default. 141 */ 142 #define CONFIG_SYS_CACHE_STASHING 143 #define CONFIG_BTB /* toggle branch predition */ 144 #define CONFIG_DDR_ECC 145 #ifdef CONFIG_DDR_ECC 146 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 147 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 148 #endif 149 150 #ifndef CONFIG_SYS_NO_FLASH 151 #define CONFIG_FLASH_CFI_DRIVER 152 #define CONFIG_SYS_FLASH_CFI 153 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 154 #endif 155 156 #if defined(CONFIG_SPIFLASH) 157 #define CONFIG_SYS_EXTRA_ENV_RELOC 158 #define CONFIG_ENV_IS_IN_SPI_FLASH 159 #define CONFIG_ENV_SPI_BUS 0 160 #define CONFIG_ENV_SPI_CS 0 161 #define CONFIG_ENV_SPI_MAX_HZ 10000000 162 #define CONFIG_ENV_SPI_MODE 0 163 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 164 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 165 #define CONFIG_ENV_SECT_SIZE 0x10000 166 #elif defined(CONFIG_SDCARD) 167 #define CONFIG_SYS_EXTRA_ENV_RELOC 168 #define CONFIG_ENV_IS_IN_MMC 169 #define CONFIG_SYS_MMC_ENV_DEV 0 170 #define CONFIG_ENV_SIZE 0x2000 171 #define CONFIG_ENV_OFFSET (512 * 0x800) 172 #elif defined(CONFIG_NAND) 173 #define CONFIG_SYS_EXTRA_ENV_RELOC 174 #define CONFIG_ENV_IS_IN_NAND 175 #define CONFIG_ENV_SIZE 0x2000 176 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 177 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 178 #define CONFIG_ENV_IS_IN_REMOTE 179 #define CONFIG_ENV_ADDR 0xffe20000 180 #define CONFIG_ENV_SIZE 0x2000 181 #elif defined(CONFIG_ENV_IS_NOWHERE) 182 #define CONFIG_ENV_SIZE 0x2000 183 #else 184 #define CONFIG_ENV_IS_IN_FLASH 185 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 186 #define CONFIG_ENV_SIZE 0x2000 187 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 188 #endif 189 190 #ifndef __ASSEMBLY__ 191 unsigned long get_board_sys_clk(void); 192 unsigned long get_board_ddr_clk(void); 193 #endif 194 195 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 196 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 197 198 /* 199 * Config the L3 Cache as L3 SRAM 200 */ 201 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 202 #define CONFIG_SYS_L3_SIZE (512 << 10) 203 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 204 #ifdef CONFIG_RAMBOOT_PBL 205 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 206 #endif 207 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 208 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 209 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 210 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 211 212 #define CONFIG_SYS_DCSRBAR 0xf0000000 213 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 214 215 /* EEPROM */ 216 #define CONFIG_ID_EEPROM 217 #define CONFIG_SYS_I2C_EEPROM_NXID 218 #define CONFIG_SYS_EEPROM_BUS_NUM 0 219 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 220 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 221 222 /* 223 * DDR Setup 224 */ 225 #define CONFIG_VERY_BIG_RAM 226 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 227 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 228 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 229 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 230 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 231 #define CONFIG_DDR_SPD 232 #define CONFIG_SYS_FSL_DDR3 233 #define CONFIG_FSL_DDR_INTERACTIVE 234 #define CONFIG_SYS_SPD_BUS_NUM 0 235 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 236 #define SPD_EEPROM_ADDRESS1 0x51 237 #define SPD_EEPROM_ADDRESS2 0x52 238 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 239 #define CTRL_INTLV_PREFERED cacheline 240 241 /* 242 * IFC Definitions 243 */ 244 #define CONFIG_SYS_FLASH_BASE 0xe0000000 245 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 246 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 247 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 248 + 0x8000000) | \ 249 CSPR_PORT_SIZE_16 | \ 250 CSPR_MSEL_NOR | \ 251 CSPR_V) 252 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 253 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 254 CSPR_PORT_SIZE_16 | \ 255 CSPR_MSEL_NOR | \ 256 CSPR_V) 257 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 258 /* NOR Flash Timing Params */ 259 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 260 261 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 262 FTIM0_NOR_TEADC(0x5) | \ 263 FTIM0_NOR_TEAHC(0x5)) 264 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 265 FTIM1_NOR_TRAD_NOR(0x1A) |\ 266 FTIM1_NOR_TSEQRAD_NOR(0x13)) 267 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 268 FTIM2_NOR_TCH(0x4) | \ 269 FTIM2_NOR_TWPH(0x0E) | \ 270 FTIM2_NOR_TWP(0x1c)) 271 #define CONFIG_SYS_NOR_FTIM3 0x0 272 273 #define CONFIG_SYS_FLASH_QUIET_TEST 274 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 275 276 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 277 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 278 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 279 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 280 281 #define CONFIG_SYS_FLASH_EMPTY_INFO 282 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 283 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 284 285 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 286 #define QIXIS_BASE 0xffdf0000 287 #define QIXIS_LBMAP_SWITCH 6 288 #define QIXIS_LBMAP_MASK 0x0f 289 #define QIXIS_LBMAP_SHIFT 0 290 #define QIXIS_LBMAP_DFLTBANK 0x00 291 #define QIXIS_LBMAP_ALTBANK 0x04 292 #define QIXIS_LBMAP_NAND 0x09 293 #define QIXIS_LBMAP_SD 0x00 294 #define QIXIS_RCW_SRC_NAND 0x104 295 #define QIXIS_RCW_SRC_SD 0x040 296 #define QIXIS_RST_CTL_RESET 0x83 297 #define QIXIS_RST_FORCE_MEM 0x1 298 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 299 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 300 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 301 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 302 303 #define CONFIG_SYS_CSPR3_EXT (0xf) 304 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 305 | CSPR_PORT_SIZE_8 \ 306 | CSPR_MSEL_GPCM \ 307 | CSPR_V) 308 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 309 #define CONFIG_SYS_CSOR3 0x0 310 /* QIXIS Timing parameters for IFC CS3 */ 311 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 312 FTIM0_GPCM_TEADC(0x0e) | \ 313 FTIM0_GPCM_TEAHC(0x0e)) 314 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 315 FTIM1_GPCM_TRAD(0x3f)) 316 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 317 FTIM2_GPCM_TCH(0x8) | \ 318 FTIM2_GPCM_TWP(0x1f)) 319 #define CONFIG_SYS_CS3_FTIM3 0x0 320 321 /* NAND Flash on IFC */ 322 #define CONFIG_NAND_FSL_IFC 323 #define CONFIG_SYS_NAND_BASE 0xff800000 324 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 325 326 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 327 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 328 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 329 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 330 | CSPR_V) 331 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 332 333 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 334 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 335 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 336 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 337 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 338 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 339 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 340 341 #define CONFIG_SYS_NAND_ONFI_DETECTION 342 343 /* ONFI NAND Flash mode0 Timing Params */ 344 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 345 FTIM0_NAND_TWP(0x18) | \ 346 FTIM0_NAND_TWCHT(0x07) | \ 347 FTIM0_NAND_TWH(0x0a)) 348 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 349 FTIM1_NAND_TWBE(0x39) | \ 350 FTIM1_NAND_TRR(0x0e) | \ 351 FTIM1_NAND_TRP(0x18)) 352 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 353 FTIM2_NAND_TREH(0x0a) | \ 354 FTIM2_NAND_TWHRE(0x1e)) 355 #define CONFIG_SYS_NAND_FTIM3 0x0 356 357 #define CONFIG_SYS_NAND_DDR_LAW 11 358 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 359 #define CONFIG_SYS_MAX_NAND_DEVICE 1 360 #define CONFIG_CMD_NAND 361 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 362 363 #if defined(CONFIG_NAND) 364 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 365 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 366 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 367 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 368 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 369 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 370 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 371 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 372 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 373 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 374 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 375 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 376 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 377 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 378 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 379 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 380 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 381 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 382 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 383 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 384 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 385 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 386 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 387 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 388 #else 389 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 390 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 391 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 392 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 393 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 394 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 395 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 396 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 397 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 398 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 399 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 400 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 401 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 402 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 403 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 404 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 405 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 406 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 407 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 408 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 409 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 410 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 411 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 412 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 413 #endif 414 415 #if defined(CONFIG_RAMBOOT_PBL) 416 #define CONFIG_SYS_RAMBOOT 417 #endif 418 419 #ifdef CONFIG_SPL_BUILD 420 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 421 #else 422 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 423 #endif 424 425 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 426 #define CONFIG_MISC_INIT_R 427 #define CONFIG_HWCONFIG 428 429 /* define to use L1 as initial stack */ 430 #define CONFIG_L1_INIT_RAM 431 #define CONFIG_SYS_INIT_RAM_LOCK 432 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 433 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 435 /* The assembler doesn't like typecast */ 436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 437 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 438 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 439 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 440 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 441 GENERATED_GBL_DATA_SIZE) 442 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 443 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 444 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 445 446 /* 447 * Serial Port 448 */ 449 #define CONFIG_CONS_INDEX 1 450 #define CONFIG_SYS_NS16550_SERIAL 451 #define CONFIG_SYS_NS16550_REG_SIZE 1 452 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 453 #define CONFIG_SYS_BAUDRATE_TABLE \ 454 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 455 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 456 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 457 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 458 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 459 460 /* 461 * I2C 462 */ 463 #define CONFIG_SYS_I2C 464 #define CONFIG_SYS_I2C_FSL 465 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 466 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 467 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 468 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 469 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 470 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 471 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 472 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 473 #define CONFIG_SYS_FSL_I2C_SPEED 100000 474 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 475 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 476 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 477 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 478 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 479 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 480 #define I2C_MUX_CH_DEFAULT 0x8 481 482 #define I2C_MUX_CH_VOL_MONITOR 0xa 483 484 /* Voltage monitor on channel 2*/ 485 #define I2C_VOL_MONITOR_ADDR 0x40 486 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 487 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 488 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 489 490 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 491 #ifndef CONFIG_SPL_BUILD 492 #define CONFIG_VID 493 #endif 494 #define CONFIG_VOL_MONITOR_IR36021_SET 495 #define CONFIG_VOL_MONITOR_IR36021_READ 496 /* The lowest and highest voltage allowed for T208xQDS */ 497 #define VDD_MV_MIN 819 498 #define VDD_MV_MAX 1212 499 500 /* 501 * RapidIO 502 */ 503 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 504 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 505 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 506 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 507 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 508 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 509 /* 510 * for slave u-boot IMAGE instored in master memory space, 511 * PHYS must be aligned based on the SIZE 512 */ 513 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 514 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 515 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 516 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 517 /* 518 * for slave UCODE and ENV instored in master memory space, 519 * PHYS must be aligned based on the SIZE 520 */ 521 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 522 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 523 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 524 525 /* slave core release by master*/ 526 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 527 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 528 529 /* 530 * SRIO_PCIE_BOOT - SLAVE 531 */ 532 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 533 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 534 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 535 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 536 #endif 537 538 /* 539 * eSPI - Enhanced SPI 540 */ 541 #ifdef CONFIG_SPI_FLASH 542 #ifndef CONFIG_SPL_BUILD 543 #endif 544 545 #define CONFIG_SPI_FLASH_BAR 546 #define CONFIG_SF_DEFAULT_SPEED 10000000 547 #define CONFIG_SF_DEFAULT_MODE 0 548 #endif 549 550 /* 551 * General PCI 552 * Memory space is mapped 1-1, but I/O space must start from 0. 553 */ 554 #define CONFIG_PCI /* Enable PCI/PCIE */ 555 #define CONFIG_PCIE1 /* PCIE controller 1 */ 556 #define CONFIG_PCIE2 /* PCIE controller 2 */ 557 #define CONFIG_PCIE3 /* PCIE controller 3 */ 558 #define CONFIG_PCIE4 /* PCIE controller 4 */ 559 #define CONFIG_FSL_PCIE_RESET 560 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 561 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 562 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 563 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 564 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 565 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 566 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 567 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 568 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 569 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 570 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 571 572 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 573 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 574 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 575 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 576 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 577 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 578 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 579 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 580 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 581 582 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 583 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 584 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 585 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 586 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 587 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 588 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 589 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 590 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 591 592 /* controller 4, Base address 203000 */ 593 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 594 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 595 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 596 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 597 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 598 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 599 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 600 601 #ifdef CONFIG_PCI 602 #define CONFIG_PCI_INDIRECT_BRIDGE 603 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 604 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 605 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 606 #define CONFIG_DOS_PARTITION 607 #endif 608 609 /* Qman/Bman */ 610 #ifndef CONFIG_NOBQFMAN 611 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 612 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 613 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 614 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 615 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 616 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 617 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 618 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 619 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 620 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 621 CONFIG_SYS_BMAN_CENA_SIZE) 622 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 623 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 624 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 625 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 626 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 627 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 628 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 629 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 630 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 631 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 632 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 633 CONFIG_SYS_QMAN_CENA_SIZE) 634 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 635 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 636 637 #define CONFIG_SYS_DPAA_FMAN 638 #define CONFIG_SYS_DPAA_PME 639 #define CONFIG_SYS_PMAN 640 #define CONFIG_SYS_DPAA_DCE 641 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 642 #define CONFIG_SYS_INTERLAKEN 643 644 /* Default address of microcode for the Linux Fman driver */ 645 #if defined(CONFIG_SPIFLASH) 646 /* 647 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 648 * env, so we got 0x110000. 649 */ 650 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 651 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 652 #elif defined(CONFIG_SDCARD) 653 /* 654 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 655 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 656 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 657 */ 658 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 659 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 660 #elif defined(CONFIG_NAND) 661 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 662 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 663 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 664 /* 665 * Slave has no ucode locally, it can fetch this from remote. When implementing 666 * in two corenet boards, slave's ucode could be stored in master's memory 667 * space, the address can be mapped from slave TLB->slave LAW-> 668 * slave SRIO or PCIE outbound window->master inbound window-> 669 * master LAW->the ucode address in master's memory space. 670 */ 671 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 672 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 673 #else 674 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 675 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 676 #endif 677 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 678 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 679 #endif /* CONFIG_NOBQFMAN */ 680 681 #ifdef CONFIG_SYS_DPAA_FMAN 682 #define CONFIG_FMAN_ENET 683 #define CONFIG_PHYLIB_10G 684 #define CONFIG_PHY_VITESSE 685 #define CONFIG_PHY_REALTEK 686 #define CONFIG_PHY_TERANETICS 687 #define RGMII_PHY1_ADDR 0x1 688 #define RGMII_PHY2_ADDR 0x2 689 #define FM1_10GEC1_PHY_ADDR 0x3 690 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 691 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 692 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 693 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 694 #endif 695 696 #ifdef CONFIG_FMAN_ENET 697 #define CONFIG_MII /* MII PHY management */ 698 #define CONFIG_ETHPRIME "FM1@DTSEC3" 699 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 700 #endif 701 702 /* 703 * SATA 704 */ 705 #ifdef CONFIG_FSL_SATA_V2 706 #define CONFIG_LIBATA 707 #define CONFIG_FSL_SATA 708 #define CONFIG_SYS_SATA_MAX_DEVICE 2 709 #define CONFIG_SATA1 710 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 711 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 712 #define CONFIG_SATA2 713 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 714 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 715 #define CONFIG_LBA48 716 #define CONFIG_CMD_SATA 717 #define CONFIG_DOS_PARTITION 718 #endif 719 720 /* 721 * USB 722 */ 723 #ifdef CONFIG_USB_EHCI 724 #define CONFIG_USB_EHCI_FSL 725 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 726 #define CONFIG_HAS_FSL_DR_USB 727 #endif 728 729 /* 730 * SDHC 731 */ 732 #ifdef CONFIG_MMC 733 #define CONFIG_FSL_ESDHC 734 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 735 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 736 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 737 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 738 #define CONFIG_GENERIC_MMC 739 #define CONFIG_DOS_PARTITION 740 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 741 #endif 742 743 /* 744 * Dynamic MTD Partition support with mtdparts 745 */ 746 #ifndef CONFIG_SYS_NO_FLASH 747 #define CONFIG_MTD_DEVICE 748 #define CONFIG_MTD_PARTITIONS 749 #define CONFIG_CMD_MTDPARTS 750 #define CONFIG_FLASH_CFI_MTD 751 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 752 "spi0=spife110000.0" 753 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 754 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 755 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 756 "1m(uboot),5m(kernel),128k(dtb),-(user)" 757 #endif 758 759 /* 760 * Environment 761 */ 762 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 763 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 764 765 /* 766 * Command line configuration. 767 */ 768 #define CONFIG_CMD_ERRATA 769 #define CONFIG_CMD_IRQ 770 #define CONFIG_CMD_REGINFO 771 772 #ifdef CONFIG_PCI 773 #define CONFIG_CMD_PCI 774 #endif 775 776 /* Hash command with SHA acceleration supported in hardware */ 777 #ifdef CONFIG_FSL_CAAM 778 #define CONFIG_CMD_HASH 779 #define CONFIG_SHA_HW_ACCEL 780 #endif 781 782 /* 783 * Miscellaneous configurable options 784 */ 785 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 786 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 787 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 788 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 789 #ifdef CONFIG_CMD_KGDB 790 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 791 #else 792 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 793 #endif 794 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 795 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 796 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 797 798 /* 799 * For booting Linux, the board info and command line data 800 * have to be in the first 64 MB of memory, since this is 801 * the maximum mapped by the Linux kernel during initialization. 802 */ 803 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 804 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 805 806 #ifdef CONFIG_CMD_KGDB 807 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 808 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 809 #endif 810 811 /* 812 * Environment Configuration 813 */ 814 #define CONFIG_ROOTPATH "/opt/nfsroot" 815 #define CONFIG_BOOTFILE "uImage" 816 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 817 818 /* default location for tftp and bootm */ 819 #define CONFIG_LOADADDR 1000000 820 #define CONFIG_BAUDRATE 115200 821 #define __USB_PHY_TYPE utmi 822 823 #define CONFIG_EXTRA_ENV_SETTINGS \ 824 "hwconfig=fsl_ddr:" \ 825 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 826 "bank_intlv=auto;" \ 827 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 828 "netdev=eth0\0" \ 829 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 830 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 831 "tftpflash=tftpboot $loadaddr $uboot && " \ 832 "protect off $ubootaddr +$filesize && " \ 833 "erase $ubootaddr +$filesize && " \ 834 "cp.b $loadaddr $ubootaddr $filesize && " \ 835 "protect on $ubootaddr +$filesize && " \ 836 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 837 "consoledev=ttyS0\0" \ 838 "ramdiskaddr=2000000\0" \ 839 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 840 "fdtaddr=1e00000\0" \ 841 "fdtfile=t2080qds/t2080qds.dtb\0" \ 842 "bdev=sda3\0" 843 844 /* 845 * For emulation this causes u-boot to jump to the start of the 846 * proof point app code automatically 847 */ 848 #define CONFIG_PROOF_POINTS \ 849 "setenv bootargs root=/dev/$bdev rw " \ 850 "console=$consoledev,$baudrate $othbootargs;" \ 851 "cpu 1 release 0x29000000 - - -;" \ 852 "cpu 2 release 0x29000000 - - -;" \ 853 "cpu 3 release 0x29000000 - - -;" \ 854 "cpu 4 release 0x29000000 - - -;" \ 855 "cpu 5 release 0x29000000 - - -;" \ 856 "cpu 6 release 0x29000000 - - -;" \ 857 "cpu 7 release 0x29000000 - - -;" \ 858 "go 0x29000000" 859 860 #define CONFIG_HVBOOT \ 861 "setenv bootargs config-addr=0x60000000; " \ 862 "bootm 0x01000000 - 0x00f00000" 863 864 #define CONFIG_ALU \ 865 "setenv bootargs root=/dev/$bdev rw " \ 866 "console=$consoledev,$baudrate $othbootargs;" \ 867 "cpu 1 release 0x01000000 - - -;" \ 868 "cpu 2 release 0x01000000 - - -;" \ 869 "cpu 3 release 0x01000000 - - -;" \ 870 "cpu 4 release 0x01000000 - - -;" \ 871 "cpu 5 release 0x01000000 - - -;" \ 872 "cpu 6 release 0x01000000 - - -;" \ 873 "cpu 7 release 0x01000000 - - -;" \ 874 "go 0x01000000" 875 876 #define CONFIG_LINUX \ 877 "setenv bootargs root=/dev/ram rw " \ 878 "console=$consoledev,$baudrate $othbootargs;" \ 879 "setenv ramdiskaddr 0x02000000;" \ 880 "setenv fdtaddr 0x00c00000;" \ 881 "setenv loadaddr 0x1000000;" \ 882 "bootm $loadaddr $ramdiskaddr $fdtaddr" 883 884 #define CONFIG_HDBOOT \ 885 "setenv bootargs root=/dev/$bdev rw " \ 886 "console=$consoledev,$baudrate $othbootargs;" \ 887 "tftp $loadaddr $bootfile;" \ 888 "tftp $fdtaddr $fdtfile;" \ 889 "bootm $loadaddr - $fdtaddr" 890 891 #define CONFIG_NFSBOOTCOMMAND \ 892 "setenv bootargs root=/dev/nfs rw " \ 893 "nfsroot=$serverip:$rootpath " \ 894 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 895 "console=$consoledev,$baudrate $othbootargs;" \ 896 "tftp $loadaddr $bootfile;" \ 897 "tftp $fdtaddr $fdtfile;" \ 898 "bootm $loadaddr - $fdtaddr" 899 900 #define CONFIG_RAMBOOTCOMMAND \ 901 "setenv bootargs root=/dev/ram rw " \ 902 "console=$consoledev,$baudrate $othbootargs;" \ 903 "tftp $ramdiskaddr $ramdiskfile;" \ 904 "tftp $loadaddr $bootfile;" \ 905 "tftp $fdtaddr $fdtfile;" \ 906 "bootm $loadaddr $ramdiskaddr $fdtaddr" 907 908 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 909 910 #include <asm/fsl_secure_boot.h> 911 912 #endif /* __T208xQDS_H */ 913