1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 16 #define CONFIG_MMC 17 #define CONFIG_USB_EHCI 18 #if defined(CONFIG_PPC_T2080) 19 #define CONFIG_T2080QDS 20 #define CONFIG_FSL_SATA_V2 21 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 22 #define CONFIG_SRIO1 /* SRIO port 1 */ 23 #define CONFIG_SRIO2 /* SRIO port 2 */ 24 #elif defined(CONFIG_PPC_T2081) 25 #define CONFIG_T2081QDS 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_BOOKE 30 #define CONFIG_E500 /* BOOKE e500 family */ 31 #define CONFIG_E500MC /* BOOKE e500mc family */ 32 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 33 #define CONFIG_MP /* support multiple processors */ 34 #define CONFIG_ENABLE_36BIT_PHYS 35 36 #ifdef CONFIG_PHYS_64BIT 37 #define CONFIG_ADDR_MAP 1 38 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 39 #endif 40 41 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 42 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 43 #define CONFIG_FSL_IFC /* Enable IFC Support */ 44 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 45 #define CONFIG_FSL_LAW /* Use common FSL init code */ 46 #define CONFIG_ENV_OVERWRITE 47 48 #ifdef CONFIG_RAMBOOT_PBL 49 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 50 #if defined(CONFIG_PPC_T2080) 51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg 52 #elif defined(CONFIG_PPC_T2081) 53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg 54 #endif 55 56 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 57 #define CONFIG_SPL_SERIAL_SUPPORT 58 #define CONFIG_SPL_FLUSH_IMAGE 59 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 60 #define CONFIG_SPL_LIBGENERIC_SUPPORT 61 #define CONFIG_SPL_LIBCOMMON_SUPPORT 62 #define CONFIG_FSL_LAW /* Use common FSL init code */ 63 #define CONFIG_SYS_TEXT_BASE 0x00201000 64 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 65 #define CONFIG_SPL_PAD_TO 0x40000 66 #define CONFIG_SPL_MAX_SIZE 0x28000 67 #define RESET_VECTOR_OFFSET 0x27FFC 68 #define BOOT_PAGE_OFFSET 0x27000 69 #ifdef CONFIG_SPL_BUILD 70 #define CONFIG_SPL_SKIP_RELOCATE 71 #define CONFIG_SPL_COMMON_INIT_DDR 72 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 73 #define CONFIG_SYS_NO_FLASH 74 #endif 75 76 #ifdef CONFIG_NAND 77 #define CONFIG_SPL_NAND_SUPPORT 78 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 79 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 80 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 81 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 82 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 83 #define CONFIG_SPL_NAND_BOOT 84 #endif 85 86 #ifdef CONFIG_SPIFLASH 87 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 88 #define CONFIG_SPL_SPI_SUPPORT 89 #define CONFIG_SPL_SPI_FLASH_SUPPORT 90 #define CONFIG_SPL_SPI_FLASH_MINIMAL 91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 94 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 95 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 96 #ifndef CONFIG_SPL_BUILD 97 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 98 #endif 99 #define CONFIG_SPL_SPI_BOOT 100 #endif 101 102 #ifdef CONFIG_SDCARD 103 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 104 #define CONFIG_SPL_MMC_SUPPORT 105 #define CONFIG_SPL_MMC_MINIMAL 106 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 107 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 108 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 109 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 110 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 111 #ifndef CONFIG_SPL_BUILD 112 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 113 #endif 114 #define CONFIG_SPL_MMC_BOOT 115 #endif 116 117 #endif /* CONFIG_RAMBOOT_PBL */ 118 119 #define CONFIG_SRIO_PCIE_BOOT_MASTER 120 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 121 /* Set 1M boot space */ 122 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 123 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 124 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 125 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 126 #define CONFIG_SYS_NO_FLASH 127 #endif 128 129 #ifndef CONFIG_SYS_TEXT_BASE 130 #define CONFIG_SYS_TEXT_BASE 0xeff40000 131 #endif 132 133 #ifndef CONFIG_RESET_VECTOR_ADDRESS 134 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 135 #endif 136 137 /* 138 * These can be toggled for performance analysis, otherwise use default. 139 */ 140 #define CONFIG_SYS_CACHE_STASHING 141 #define CONFIG_BTB /* toggle branch predition */ 142 #define CONFIG_DDR_ECC 143 #ifdef CONFIG_DDR_ECC 144 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 145 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 146 #endif 147 148 #ifndef CONFIG_SYS_NO_FLASH 149 #define CONFIG_FLASH_CFI_DRIVER 150 #define CONFIG_SYS_FLASH_CFI 151 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 152 #endif 153 154 #if defined(CONFIG_SPIFLASH) 155 #define CONFIG_SYS_EXTRA_ENV_RELOC 156 #define CONFIG_ENV_IS_IN_SPI_FLASH 157 #define CONFIG_ENV_SPI_BUS 0 158 #define CONFIG_ENV_SPI_CS 0 159 #define CONFIG_ENV_SPI_MAX_HZ 10000000 160 #define CONFIG_ENV_SPI_MODE 0 161 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 162 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 163 #define CONFIG_ENV_SECT_SIZE 0x10000 164 #elif defined(CONFIG_SDCARD) 165 #define CONFIG_SYS_EXTRA_ENV_RELOC 166 #define CONFIG_ENV_IS_IN_MMC 167 #define CONFIG_SYS_MMC_ENV_DEV 0 168 #define CONFIG_ENV_SIZE 0x2000 169 #define CONFIG_ENV_OFFSET (512 * 0x800) 170 #elif defined(CONFIG_NAND) 171 #define CONFIG_SYS_EXTRA_ENV_RELOC 172 #define CONFIG_ENV_IS_IN_NAND 173 #define CONFIG_ENV_SIZE 0x2000 174 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 175 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 176 #define CONFIG_ENV_IS_IN_REMOTE 177 #define CONFIG_ENV_ADDR 0xffe20000 178 #define CONFIG_ENV_SIZE 0x2000 179 #elif defined(CONFIG_ENV_IS_NOWHERE) 180 #define CONFIG_ENV_SIZE 0x2000 181 #else 182 #define CONFIG_ENV_IS_IN_FLASH 183 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 184 #define CONFIG_ENV_SIZE 0x2000 185 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 186 #endif 187 188 #ifndef __ASSEMBLY__ 189 unsigned long get_board_sys_clk(void); 190 unsigned long get_board_ddr_clk(void); 191 #endif 192 193 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 194 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 195 196 /* 197 * Config the L3 Cache as L3 SRAM 198 */ 199 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 200 #define CONFIG_SYS_L3_SIZE (512 << 10) 201 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 202 #ifdef CONFIG_RAMBOOT_PBL 203 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 204 #endif 205 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 206 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 207 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 208 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 209 210 #define CONFIG_SYS_DCSRBAR 0xf0000000 211 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 212 213 /* EEPROM */ 214 #define CONFIG_ID_EEPROM 215 #define CONFIG_SYS_I2C_EEPROM_NXID 216 #define CONFIG_SYS_EEPROM_BUS_NUM 0 217 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 218 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 219 220 /* 221 * DDR Setup 222 */ 223 #define CONFIG_VERY_BIG_RAM 224 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 225 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 226 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 227 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 228 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 229 #define CONFIG_DDR_SPD 230 #define CONFIG_SYS_FSL_DDR3 231 #define CONFIG_FSL_DDR_INTERACTIVE 232 #define CONFIG_SYS_SPD_BUS_NUM 0 233 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 234 #define SPD_EEPROM_ADDRESS1 0x51 235 #define SPD_EEPROM_ADDRESS2 0x52 236 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 237 #define CTRL_INTLV_PREFERED cacheline 238 239 /* 240 * IFC Definitions 241 */ 242 #define CONFIG_SYS_FLASH_BASE 0xe0000000 243 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 244 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 245 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 246 + 0x8000000) | \ 247 CSPR_PORT_SIZE_16 | \ 248 CSPR_MSEL_NOR | \ 249 CSPR_V) 250 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 251 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 252 CSPR_PORT_SIZE_16 | \ 253 CSPR_MSEL_NOR | \ 254 CSPR_V) 255 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 256 /* NOR Flash Timing Params */ 257 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 258 259 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 260 FTIM0_NOR_TEADC(0x5) | \ 261 FTIM0_NOR_TEAHC(0x5)) 262 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 263 FTIM1_NOR_TRAD_NOR(0x1A) |\ 264 FTIM1_NOR_TSEQRAD_NOR(0x13)) 265 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 266 FTIM2_NOR_TCH(0x4) | \ 267 FTIM2_NOR_TWPH(0x0E) | \ 268 FTIM2_NOR_TWP(0x1c)) 269 #define CONFIG_SYS_NOR_FTIM3 0x0 270 271 #define CONFIG_SYS_FLASH_QUIET_TEST 272 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 273 274 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 275 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 276 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 277 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 278 279 #define CONFIG_SYS_FLASH_EMPTY_INFO 280 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 281 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 282 283 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 284 #define QIXIS_BASE 0xffdf0000 285 #define QIXIS_LBMAP_SWITCH 6 286 #define QIXIS_LBMAP_MASK 0x0f 287 #define QIXIS_LBMAP_SHIFT 0 288 #define QIXIS_LBMAP_DFLTBANK 0x00 289 #define QIXIS_LBMAP_ALTBANK 0x04 290 #define QIXIS_LBMAP_NAND 0x09 291 #define QIXIS_LBMAP_SD 0x00 292 #define QIXIS_RCW_SRC_NAND 0x104 293 #define QIXIS_RCW_SRC_SD 0x040 294 #define QIXIS_RST_CTL_RESET 0x83 295 #define QIXIS_RST_FORCE_MEM 0x1 296 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 297 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 298 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 299 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 300 301 #define CONFIG_SYS_CSPR3_EXT (0xf) 302 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 303 | CSPR_PORT_SIZE_8 \ 304 | CSPR_MSEL_GPCM \ 305 | CSPR_V) 306 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 307 #define CONFIG_SYS_CSOR3 0x0 308 /* QIXIS Timing parameters for IFC CS3 */ 309 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 310 FTIM0_GPCM_TEADC(0x0e) | \ 311 FTIM0_GPCM_TEAHC(0x0e)) 312 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 313 FTIM1_GPCM_TRAD(0x3f)) 314 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 315 FTIM2_GPCM_TCH(0x8) | \ 316 FTIM2_GPCM_TWP(0x1f)) 317 #define CONFIG_SYS_CS3_FTIM3 0x0 318 319 /* NAND Flash on IFC */ 320 #define CONFIG_NAND_FSL_IFC 321 #define CONFIG_SYS_NAND_BASE 0xff800000 322 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 323 324 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 325 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 326 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 327 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 328 | CSPR_V) 329 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 330 331 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 332 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 333 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 334 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 335 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 336 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 337 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 338 339 #define CONFIG_SYS_NAND_ONFI_DETECTION 340 341 /* ONFI NAND Flash mode0 Timing Params */ 342 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 343 FTIM0_NAND_TWP(0x18) | \ 344 FTIM0_NAND_TWCHT(0x07) | \ 345 FTIM0_NAND_TWH(0x0a)) 346 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 347 FTIM1_NAND_TWBE(0x39) | \ 348 FTIM1_NAND_TRR(0x0e) | \ 349 FTIM1_NAND_TRP(0x18)) 350 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 351 FTIM2_NAND_TREH(0x0a) | \ 352 FTIM2_NAND_TWHRE(0x1e)) 353 #define CONFIG_SYS_NAND_FTIM3 0x0 354 355 #define CONFIG_SYS_NAND_DDR_LAW 11 356 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 357 #define CONFIG_SYS_MAX_NAND_DEVICE 1 358 #define CONFIG_CMD_NAND 359 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 360 361 #if defined(CONFIG_NAND) 362 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 363 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 364 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 365 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 366 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 367 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 368 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 369 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 370 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 371 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 372 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 373 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 374 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 375 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 376 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 377 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 378 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 379 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 380 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 381 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 382 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 383 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 384 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 385 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 386 #else 387 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 388 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 389 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 390 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 391 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 392 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 393 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 394 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 395 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 396 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 397 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 398 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 399 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 400 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 401 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 402 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 403 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 404 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 405 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 406 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 407 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 408 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 409 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 410 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 411 #endif 412 413 #if defined(CONFIG_RAMBOOT_PBL) 414 #define CONFIG_SYS_RAMBOOT 415 #endif 416 417 #ifdef CONFIG_SPL_BUILD 418 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 419 #else 420 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 421 #endif 422 423 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 424 #define CONFIG_MISC_INIT_R 425 #define CONFIG_HWCONFIG 426 427 /* define to use L1 as initial stack */ 428 #define CONFIG_L1_INIT_RAM 429 #define CONFIG_SYS_INIT_RAM_LOCK 430 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 431 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 432 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 433 /* The assembler doesn't like typecast */ 434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 435 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 436 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 437 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 438 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 439 GENERATED_GBL_DATA_SIZE) 440 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 441 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 442 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 443 444 /* 445 * Serial Port 446 */ 447 #define CONFIG_CONS_INDEX 1 448 #define CONFIG_SYS_NS16550_SERIAL 449 #define CONFIG_SYS_NS16550_REG_SIZE 1 450 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 451 #define CONFIG_SYS_BAUDRATE_TABLE \ 452 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 453 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 454 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 455 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 456 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 457 458 /* 459 * I2C 460 */ 461 #define CONFIG_SYS_I2C 462 #define CONFIG_SYS_I2C_FSL 463 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 464 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 465 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 466 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 467 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 468 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 469 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 470 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 471 #define CONFIG_SYS_FSL_I2C_SPEED 100000 472 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 473 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 474 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 475 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 476 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 477 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 478 #define I2C_MUX_CH_DEFAULT 0x8 479 480 #define I2C_MUX_CH_VOL_MONITOR 0xa 481 482 /* Voltage monitor on channel 2*/ 483 #define I2C_VOL_MONITOR_ADDR 0x40 484 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 485 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 486 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 487 488 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 489 #ifndef CONFIG_SPL_BUILD 490 #define CONFIG_VID 491 #endif 492 #define CONFIG_VOL_MONITOR_IR36021_SET 493 #define CONFIG_VOL_MONITOR_IR36021_READ 494 /* The lowest and highest voltage allowed for T208xQDS */ 495 #define VDD_MV_MIN 819 496 #define VDD_MV_MAX 1212 497 498 /* 499 * RapidIO 500 */ 501 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 502 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 503 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 504 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 505 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 506 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 507 /* 508 * for slave u-boot IMAGE instored in master memory space, 509 * PHYS must be aligned based on the SIZE 510 */ 511 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 512 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 513 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 514 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 515 /* 516 * for slave UCODE and ENV instored in master memory space, 517 * PHYS must be aligned based on the SIZE 518 */ 519 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 520 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 521 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 522 523 /* slave core release by master*/ 524 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 525 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 526 527 /* 528 * SRIO_PCIE_BOOT - SLAVE 529 */ 530 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 531 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 532 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 533 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 534 #endif 535 536 /* 537 * eSPI - Enhanced SPI 538 */ 539 #ifdef CONFIG_SPI_FLASH 540 #ifndef CONFIG_SPL_BUILD 541 #endif 542 543 #define CONFIG_SPI_FLASH_BAR 544 #define CONFIG_SF_DEFAULT_SPEED 10000000 545 #define CONFIG_SF_DEFAULT_MODE 0 546 #endif 547 548 /* 549 * General PCI 550 * Memory space is mapped 1-1, but I/O space must start from 0. 551 */ 552 #define CONFIG_PCI /* Enable PCI/PCIE */ 553 #define CONFIG_PCIE1 /* PCIE controller 1 */ 554 #define CONFIG_PCIE2 /* PCIE controller 2 */ 555 #define CONFIG_PCIE3 /* PCIE controller 3 */ 556 #define CONFIG_PCIE4 /* PCIE controller 4 */ 557 #define CONFIG_FSL_PCIE_RESET 558 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 559 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 560 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 561 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 562 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 563 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 564 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 565 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 566 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 567 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 568 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 569 570 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 571 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 572 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 573 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 574 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 575 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 576 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 577 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 578 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 579 580 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 581 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 582 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 583 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 584 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 585 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 586 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 587 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 588 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 589 590 /* controller 4, Base address 203000 */ 591 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 592 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 593 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 594 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 595 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 596 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 597 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 598 599 #ifdef CONFIG_PCI 600 #define CONFIG_PCI_INDIRECT_BRIDGE 601 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 602 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 603 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 604 #define CONFIG_DOS_PARTITION 605 #endif 606 607 /* Qman/Bman */ 608 #ifndef CONFIG_NOBQFMAN 609 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 610 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 611 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 612 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 613 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 614 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 615 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 616 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 617 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 618 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 619 CONFIG_SYS_BMAN_CENA_SIZE) 620 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 621 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 622 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 623 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 624 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 625 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 626 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 627 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 628 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 629 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 630 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 631 CONFIG_SYS_QMAN_CENA_SIZE) 632 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 633 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 634 635 #define CONFIG_SYS_DPAA_FMAN 636 #define CONFIG_SYS_DPAA_PME 637 #define CONFIG_SYS_PMAN 638 #define CONFIG_SYS_DPAA_DCE 639 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 640 #define CONFIG_SYS_INTERLAKEN 641 642 /* Default address of microcode for the Linux Fman driver */ 643 #if defined(CONFIG_SPIFLASH) 644 /* 645 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 646 * env, so we got 0x110000. 647 */ 648 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 649 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 650 #elif defined(CONFIG_SDCARD) 651 /* 652 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 653 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 654 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 655 */ 656 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 657 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 658 #elif defined(CONFIG_NAND) 659 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 660 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 661 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 662 /* 663 * Slave has no ucode locally, it can fetch this from remote. When implementing 664 * in two corenet boards, slave's ucode could be stored in master's memory 665 * space, the address can be mapped from slave TLB->slave LAW-> 666 * slave SRIO or PCIE outbound window->master inbound window-> 667 * master LAW->the ucode address in master's memory space. 668 */ 669 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 670 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 671 #else 672 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 673 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 674 #endif 675 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 676 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 677 #endif /* CONFIG_NOBQFMAN */ 678 679 #ifdef CONFIG_SYS_DPAA_FMAN 680 #define CONFIG_FMAN_ENET 681 #define CONFIG_PHYLIB_10G 682 #define CONFIG_PHY_VITESSE 683 #define CONFIG_PHY_REALTEK 684 #define CONFIG_PHY_TERANETICS 685 #define RGMII_PHY1_ADDR 0x1 686 #define RGMII_PHY2_ADDR 0x2 687 #define FM1_10GEC1_PHY_ADDR 0x3 688 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 689 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 690 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 691 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 692 #endif 693 694 #ifdef CONFIG_FMAN_ENET 695 #define CONFIG_MII /* MII PHY management */ 696 #define CONFIG_ETHPRIME "FM1@DTSEC3" 697 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 698 #endif 699 700 /* 701 * SATA 702 */ 703 #ifdef CONFIG_FSL_SATA_V2 704 #define CONFIG_LIBATA 705 #define CONFIG_FSL_SATA 706 #define CONFIG_SYS_SATA_MAX_DEVICE 2 707 #define CONFIG_SATA1 708 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 709 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 710 #define CONFIG_SATA2 711 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 712 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 713 #define CONFIG_LBA48 714 #define CONFIG_CMD_SATA 715 #define CONFIG_DOS_PARTITION 716 #endif 717 718 /* 719 * USB 720 */ 721 #ifdef CONFIG_USB_EHCI 722 #define CONFIG_USB_EHCI_FSL 723 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 724 #define CONFIG_HAS_FSL_DR_USB 725 #endif 726 727 /* 728 * SDHC 729 */ 730 #ifdef CONFIG_MMC 731 #define CONFIG_FSL_ESDHC 732 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 733 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 734 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 735 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 736 #define CONFIG_GENERIC_MMC 737 #define CONFIG_DOS_PARTITION 738 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 739 #endif 740 741 /* 742 * Dynamic MTD Partition support with mtdparts 743 */ 744 #ifndef CONFIG_SYS_NO_FLASH 745 #define CONFIG_MTD_DEVICE 746 #define CONFIG_MTD_PARTITIONS 747 #define CONFIG_CMD_MTDPARTS 748 #define CONFIG_FLASH_CFI_MTD 749 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 750 "spi0=spife110000.0" 751 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 752 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 753 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 754 "1m(uboot),5m(kernel),128k(dtb),-(user)" 755 #endif 756 757 /* 758 * Environment 759 */ 760 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 761 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 762 763 /* 764 * Command line configuration. 765 */ 766 #define CONFIG_CMD_ERRATA 767 #define CONFIG_CMD_IRQ 768 #define CONFIG_CMD_REGINFO 769 770 #ifdef CONFIG_PCI 771 #define CONFIG_CMD_PCI 772 #endif 773 774 /* Hash command with SHA acceleration supported in hardware */ 775 #ifdef CONFIG_FSL_CAAM 776 #define CONFIG_CMD_HASH 777 #define CONFIG_SHA_HW_ACCEL 778 #endif 779 780 /* 781 * Miscellaneous configurable options 782 */ 783 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 784 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 785 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 786 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 787 #ifdef CONFIG_CMD_KGDB 788 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 789 #else 790 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 791 #endif 792 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 793 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 794 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 795 796 /* 797 * For booting Linux, the board info and command line data 798 * have to be in the first 64 MB of memory, since this is 799 * the maximum mapped by the Linux kernel during initialization. 800 */ 801 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 802 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 803 804 #ifdef CONFIG_CMD_KGDB 805 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 806 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 807 #endif 808 809 /* 810 * Environment Configuration 811 */ 812 #define CONFIG_ROOTPATH "/opt/nfsroot" 813 #define CONFIG_BOOTFILE "uImage" 814 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 815 816 /* default location for tftp and bootm */ 817 #define CONFIG_LOADADDR 1000000 818 #define CONFIG_BAUDRATE 115200 819 #define __USB_PHY_TYPE utmi 820 821 #define CONFIG_EXTRA_ENV_SETTINGS \ 822 "hwconfig=fsl_ddr:" \ 823 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 824 "bank_intlv=auto;" \ 825 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 826 "netdev=eth0\0" \ 827 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 828 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 829 "tftpflash=tftpboot $loadaddr $uboot && " \ 830 "protect off $ubootaddr +$filesize && " \ 831 "erase $ubootaddr +$filesize && " \ 832 "cp.b $loadaddr $ubootaddr $filesize && " \ 833 "protect on $ubootaddr +$filesize && " \ 834 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 835 "consoledev=ttyS0\0" \ 836 "ramdiskaddr=2000000\0" \ 837 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 838 "fdtaddr=1e00000\0" \ 839 "fdtfile=t2080qds/t2080qds.dtb\0" \ 840 "bdev=sda3\0" 841 842 /* 843 * For emulation this causes u-boot to jump to the start of the 844 * proof point app code automatically 845 */ 846 #define CONFIG_PROOF_POINTS \ 847 "setenv bootargs root=/dev/$bdev rw " \ 848 "console=$consoledev,$baudrate $othbootargs;" \ 849 "cpu 1 release 0x29000000 - - -;" \ 850 "cpu 2 release 0x29000000 - - -;" \ 851 "cpu 3 release 0x29000000 - - -;" \ 852 "cpu 4 release 0x29000000 - - -;" \ 853 "cpu 5 release 0x29000000 - - -;" \ 854 "cpu 6 release 0x29000000 - - -;" \ 855 "cpu 7 release 0x29000000 - - -;" \ 856 "go 0x29000000" 857 858 #define CONFIG_HVBOOT \ 859 "setenv bootargs config-addr=0x60000000; " \ 860 "bootm 0x01000000 - 0x00f00000" 861 862 #define CONFIG_ALU \ 863 "setenv bootargs root=/dev/$bdev rw " \ 864 "console=$consoledev,$baudrate $othbootargs;" \ 865 "cpu 1 release 0x01000000 - - -;" \ 866 "cpu 2 release 0x01000000 - - -;" \ 867 "cpu 3 release 0x01000000 - - -;" \ 868 "cpu 4 release 0x01000000 - - -;" \ 869 "cpu 5 release 0x01000000 - - -;" \ 870 "cpu 6 release 0x01000000 - - -;" \ 871 "cpu 7 release 0x01000000 - - -;" \ 872 "go 0x01000000" 873 874 #define CONFIG_LINUX \ 875 "setenv bootargs root=/dev/ram rw " \ 876 "console=$consoledev,$baudrate $othbootargs;" \ 877 "setenv ramdiskaddr 0x02000000;" \ 878 "setenv fdtaddr 0x00c00000;" \ 879 "setenv loadaddr 0x1000000;" \ 880 "bootm $loadaddr $ramdiskaddr $fdtaddr" 881 882 #define CONFIG_HDBOOT \ 883 "setenv bootargs root=/dev/$bdev rw " \ 884 "console=$consoledev,$baudrate $othbootargs;" \ 885 "tftp $loadaddr $bootfile;" \ 886 "tftp $fdtaddr $fdtfile;" \ 887 "bootm $loadaddr - $fdtaddr" 888 889 #define CONFIG_NFSBOOTCOMMAND \ 890 "setenv bootargs root=/dev/nfs rw " \ 891 "nfsroot=$serverip:$rootpath " \ 892 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 893 "console=$consoledev,$baudrate $othbootargs;" \ 894 "tftp $loadaddr $bootfile;" \ 895 "tftp $fdtaddr $fdtfile;" \ 896 "bootm $loadaddr - $fdtaddr" 897 898 #define CONFIG_RAMBOOTCOMMAND \ 899 "setenv bootargs root=/dev/ram rw " \ 900 "console=$consoledev,$baudrate $othbootargs;" \ 901 "tftp $ramdiskaddr $ramdiskfile;" \ 902 "tftp $loadaddr $bootfile;" \ 903 "tftp $fdtaddr $fdtfile;" \ 904 "bootm $loadaddr $ramdiskaddr $fdtaddr" 905 906 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 907 908 #include <asm/fsl_secure_boot.h> 909 910 #endif /* __T208xQDS_H */ 911