1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 16 #define CONFIG_MMC 17 #define CONFIG_USB_EHCI 18 #if defined(CONFIG_PPC_T2080) 19 #define CONFIG_T2080QDS 20 #define CONFIG_FSL_SATA_V2 21 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 22 #define CONFIG_SRIO1 /* SRIO port 1 */ 23 #define CONFIG_SRIO2 /* SRIO port 2 */ 24 #elif defined(CONFIG_PPC_T2081) 25 #define CONFIG_T2081QDS 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_BOOKE 30 #define CONFIG_E500 /* BOOKE e500 family */ 31 #define CONFIG_E500MC /* BOOKE e500mc family */ 32 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 33 #define CONFIG_MP /* support multiple processors */ 34 #define CONFIG_ENABLE_36BIT_PHYS 35 36 #ifdef CONFIG_PHYS_64BIT 37 #define CONFIG_ADDR_MAP 1 38 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 39 #endif 40 41 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 42 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 43 #define CONFIG_FSL_IFC /* Enable IFC Support */ 44 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 45 #define CONFIG_FSL_LAW /* Use common FSL init code */ 46 #define CONFIG_ENV_OVERWRITE 47 48 #ifdef CONFIG_RAMBOOT_PBL 49 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 50 #if defined(CONFIG_PPC_T2080) 51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg 52 #elif defined(CONFIG_PPC_T2081) 53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg 54 #endif 55 56 #define CONFIG_SPL_SERIAL_SUPPORT 57 #define CONFIG_SPL_FLUSH_IMAGE 58 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 59 #define CONFIG_FSL_LAW /* Use common FSL init code */ 60 #define CONFIG_SYS_TEXT_BASE 0x00201000 61 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 62 #define CONFIG_SPL_PAD_TO 0x40000 63 #define CONFIG_SPL_MAX_SIZE 0x28000 64 #define RESET_VECTOR_OFFSET 0x27FFC 65 #define BOOT_PAGE_OFFSET 0x27000 66 #ifdef CONFIG_SPL_BUILD 67 #define CONFIG_SPL_SKIP_RELOCATE 68 #define CONFIG_SPL_COMMON_INIT_DDR 69 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 70 #define CONFIG_SYS_NO_FLASH 71 #endif 72 73 #ifdef CONFIG_NAND 74 #define CONFIG_SPL_NAND_SUPPORT 75 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 76 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 77 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 78 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 79 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 80 #define CONFIG_SPL_NAND_BOOT 81 #endif 82 83 #ifdef CONFIG_SPIFLASH 84 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 85 #define CONFIG_SPL_SPI_SUPPORT 86 #define CONFIG_SPL_SPI_FLASH_SUPPORT 87 #define CONFIG_SPL_SPI_FLASH_MINIMAL 88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 89 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 90 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 92 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 93 #ifndef CONFIG_SPL_BUILD 94 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 95 #endif 96 #define CONFIG_SPL_SPI_BOOT 97 #endif 98 99 #ifdef CONFIG_SDCARD 100 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 101 #define CONFIG_SPL_MMC_MINIMAL 102 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 103 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 104 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 105 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 106 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 107 #ifndef CONFIG_SPL_BUILD 108 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 109 #endif 110 #define CONFIG_SPL_MMC_BOOT 111 #endif 112 113 #endif /* CONFIG_RAMBOOT_PBL */ 114 115 #define CONFIG_SRIO_PCIE_BOOT_MASTER 116 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 117 /* Set 1M boot space */ 118 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 119 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 120 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 121 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 122 #define CONFIG_SYS_NO_FLASH 123 #endif 124 125 #ifndef CONFIG_SYS_TEXT_BASE 126 #define CONFIG_SYS_TEXT_BASE 0xeff40000 127 #endif 128 129 #ifndef CONFIG_RESET_VECTOR_ADDRESS 130 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 131 #endif 132 133 /* 134 * These can be toggled for performance analysis, otherwise use default. 135 */ 136 #define CONFIG_SYS_CACHE_STASHING 137 #define CONFIG_BTB /* toggle branch predition */ 138 #define CONFIG_DDR_ECC 139 #ifdef CONFIG_DDR_ECC 140 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 141 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 142 #endif 143 144 #ifndef CONFIG_SYS_NO_FLASH 145 #define CONFIG_FLASH_CFI_DRIVER 146 #define CONFIG_SYS_FLASH_CFI 147 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 148 #endif 149 150 #if defined(CONFIG_SPIFLASH) 151 #define CONFIG_SYS_EXTRA_ENV_RELOC 152 #define CONFIG_ENV_IS_IN_SPI_FLASH 153 #define CONFIG_ENV_SPI_BUS 0 154 #define CONFIG_ENV_SPI_CS 0 155 #define CONFIG_ENV_SPI_MAX_HZ 10000000 156 #define CONFIG_ENV_SPI_MODE 0 157 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 158 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 159 #define CONFIG_ENV_SECT_SIZE 0x10000 160 #elif defined(CONFIG_SDCARD) 161 #define CONFIG_SYS_EXTRA_ENV_RELOC 162 #define CONFIG_ENV_IS_IN_MMC 163 #define CONFIG_SYS_MMC_ENV_DEV 0 164 #define CONFIG_ENV_SIZE 0x2000 165 #define CONFIG_ENV_OFFSET (512 * 0x800) 166 #elif defined(CONFIG_NAND) 167 #define CONFIG_SYS_EXTRA_ENV_RELOC 168 #define CONFIG_ENV_IS_IN_NAND 169 #define CONFIG_ENV_SIZE 0x2000 170 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 171 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 172 #define CONFIG_ENV_IS_IN_REMOTE 173 #define CONFIG_ENV_ADDR 0xffe20000 174 #define CONFIG_ENV_SIZE 0x2000 175 #elif defined(CONFIG_ENV_IS_NOWHERE) 176 #define CONFIG_ENV_SIZE 0x2000 177 #else 178 #define CONFIG_ENV_IS_IN_FLASH 179 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 180 #define CONFIG_ENV_SIZE 0x2000 181 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 182 #endif 183 184 #ifndef __ASSEMBLY__ 185 unsigned long get_board_sys_clk(void); 186 unsigned long get_board_ddr_clk(void); 187 #endif 188 189 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 190 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 191 192 /* 193 * Config the L3 Cache as L3 SRAM 194 */ 195 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 196 #define CONFIG_SYS_L3_SIZE (512 << 10) 197 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 198 #ifdef CONFIG_RAMBOOT_PBL 199 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 200 #endif 201 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 202 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 203 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 204 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 205 206 #define CONFIG_SYS_DCSRBAR 0xf0000000 207 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 208 209 /* EEPROM */ 210 #define CONFIG_ID_EEPROM 211 #define CONFIG_SYS_I2C_EEPROM_NXID 212 #define CONFIG_SYS_EEPROM_BUS_NUM 0 213 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 214 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 215 216 /* 217 * DDR Setup 218 */ 219 #define CONFIG_VERY_BIG_RAM 220 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 221 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 222 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 223 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 224 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 225 #define CONFIG_DDR_SPD 226 #define CONFIG_SYS_FSL_DDR3 227 #define CONFIG_FSL_DDR_INTERACTIVE 228 #define CONFIG_SYS_SPD_BUS_NUM 0 229 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 230 #define SPD_EEPROM_ADDRESS1 0x51 231 #define SPD_EEPROM_ADDRESS2 0x52 232 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 233 #define CTRL_INTLV_PREFERED cacheline 234 235 /* 236 * IFC Definitions 237 */ 238 #define CONFIG_SYS_FLASH_BASE 0xe0000000 239 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 240 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 241 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 242 + 0x8000000) | \ 243 CSPR_PORT_SIZE_16 | \ 244 CSPR_MSEL_NOR | \ 245 CSPR_V) 246 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 247 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 248 CSPR_PORT_SIZE_16 | \ 249 CSPR_MSEL_NOR | \ 250 CSPR_V) 251 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 252 /* NOR Flash Timing Params */ 253 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 254 255 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 256 FTIM0_NOR_TEADC(0x5) | \ 257 FTIM0_NOR_TEAHC(0x5)) 258 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 259 FTIM1_NOR_TRAD_NOR(0x1A) |\ 260 FTIM1_NOR_TSEQRAD_NOR(0x13)) 261 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 262 FTIM2_NOR_TCH(0x4) | \ 263 FTIM2_NOR_TWPH(0x0E) | \ 264 FTIM2_NOR_TWP(0x1c)) 265 #define CONFIG_SYS_NOR_FTIM3 0x0 266 267 #define CONFIG_SYS_FLASH_QUIET_TEST 268 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 269 270 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 271 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 272 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 273 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 274 275 #define CONFIG_SYS_FLASH_EMPTY_INFO 276 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 277 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 278 279 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 280 #define QIXIS_BASE 0xffdf0000 281 #define QIXIS_LBMAP_SWITCH 6 282 #define QIXIS_LBMAP_MASK 0x0f 283 #define QIXIS_LBMAP_SHIFT 0 284 #define QIXIS_LBMAP_DFLTBANK 0x00 285 #define QIXIS_LBMAP_ALTBANK 0x04 286 #define QIXIS_LBMAP_NAND 0x09 287 #define QIXIS_LBMAP_SD 0x00 288 #define QIXIS_RCW_SRC_NAND 0x104 289 #define QIXIS_RCW_SRC_SD 0x040 290 #define QIXIS_RST_CTL_RESET 0x83 291 #define QIXIS_RST_FORCE_MEM 0x1 292 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 293 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 294 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 295 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 296 297 #define CONFIG_SYS_CSPR3_EXT (0xf) 298 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 299 | CSPR_PORT_SIZE_8 \ 300 | CSPR_MSEL_GPCM \ 301 | CSPR_V) 302 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 303 #define CONFIG_SYS_CSOR3 0x0 304 /* QIXIS Timing parameters for IFC CS3 */ 305 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 306 FTIM0_GPCM_TEADC(0x0e) | \ 307 FTIM0_GPCM_TEAHC(0x0e)) 308 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 309 FTIM1_GPCM_TRAD(0x3f)) 310 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 311 FTIM2_GPCM_TCH(0x8) | \ 312 FTIM2_GPCM_TWP(0x1f)) 313 #define CONFIG_SYS_CS3_FTIM3 0x0 314 315 /* NAND Flash on IFC */ 316 #define CONFIG_NAND_FSL_IFC 317 #define CONFIG_SYS_NAND_BASE 0xff800000 318 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 319 320 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 321 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 322 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 323 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 324 | CSPR_V) 325 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 326 327 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 328 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 329 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 330 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 331 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 332 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 333 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 334 335 #define CONFIG_SYS_NAND_ONFI_DETECTION 336 337 /* ONFI NAND Flash mode0 Timing Params */ 338 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 339 FTIM0_NAND_TWP(0x18) | \ 340 FTIM0_NAND_TWCHT(0x07) | \ 341 FTIM0_NAND_TWH(0x0a)) 342 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 343 FTIM1_NAND_TWBE(0x39) | \ 344 FTIM1_NAND_TRR(0x0e) | \ 345 FTIM1_NAND_TRP(0x18)) 346 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 347 FTIM2_NAND_TREH(0x0a) | \ 348 FTIM2_NAND_TWHRE(0x1e)) 349 #define CONFIG_SYS_NAND_FTIM3 0x0 350 351 #define CONFIG_SYS_NAND_DDR_LAW 11 352 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 353 #define CONFIG_SYS_MAX_NAND_DEVICE 1 354 #define CONFIG_CMD_NAND 355 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 356 357 #if defined(CONFIG_NAND) 358 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 359 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 360 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 361 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 362 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 363 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 364 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 365 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 366 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 367 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 368 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 369 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 370 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 371 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 372 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 373 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 374 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 375 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 376 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 377 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 378 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 379 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 380 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 381 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 382 #else 383 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 384 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 385 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 386 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 387 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 388 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 389 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 390 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 391 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 392 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 393 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 394 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 395 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 396 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 397 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 398 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 399 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 400 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 401 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 402 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 403 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 404 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 405 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 406 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 407 #endif 408 409 #if defined(CONFIG_RAMBOOT_PBL) 410 #define CONFIG_SYS_RAMBOOT 411 #endif 412 413 #ifdef CONFIG_SPL_BUILD 414 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 415 #else 416 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 417 #endif 418 419 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 420 #define CONFIG_MISC_INIT_R 421 #define CONFIG_HWCONFIG 422 423 /* define to use L1 as initial stack */ 424 #define CONFIG_L1_INIT_RAM 425 #define CONFIG_SYS_INIT_RAM_LOCK 426 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 427 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 428 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 429 /* The assembler doesn't like typecast */ 430 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 431 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 432 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 433 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 434 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 435 GENERATED_GBL_DATA_SIZE) 436 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 437 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 438 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 439 440 /* 441 * Serial Port 442 */ 443 #define CONFIG_CONS_INDEX 1 444 #define CONFIG_SYS_NS16550_SERIAL 445 #define CONFIG_SYS_NS16550_REG_SIZE 1 446 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 447 #define CONFIG_SYS_BAUDRATE_TABLE \ 448 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 449 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 450 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 451 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 452 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 453 454 /* 455 * I2C 456 */ 457 #define CONFIG_SYS_I2C 458 #define CONFIG_SYS_I2C_FSL 459 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 460 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 461 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 462 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 463 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 464 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 465 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 466 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 467 #define CONFIG_SYS_FSL_I2C_SPEED 100000 468 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 469 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 470 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 471 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 472 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 473 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 474 #define I2C_MUX_CH_DEFAULT 0x8 475 476 #define I2C_MUX_CH_VOL_MONITOR 0xa 477 478 /* Voltage monitor on channel 2*/ 479 #define I2C_VOL_MONITOR_ADDR 0x40 480 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 481 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 482 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 483 484 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 485 #ifndef CONFIG_SPL_BUILD 486 #define CONFIG_VID 487 #endif 488 #define CONFIG_VOL_MONITOR_IR36021_SET 489 #define CONFIG_VOL_MONITOR_IR36021_READ 490 /* The lowest and highest voltage allowed for T208xQDS */ 491 #define VDD_MV_MIN 819 492 #define VDD_MV_MAX 1212 493 494 /* 495 * RapidIO 496 */ 497 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 498 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 499 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 500 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 501 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 502 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 503 /* 504 * for slave u-boot IMAGE instored in master memory space, 505 * PHYS must be aligned based on the SIZE 506 */ 507 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 508 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 509 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 510 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 511 /* 512 * for slave UCODE and ENV instored in master memory space, 513 * PHYS must be aligned based on the SIZE 514 */ 515 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 516 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 517 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 518 519 /* slave core release by master*/ 520 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 521 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 522 523 /* 524 * SRIO_PCIE_BOOT - SLAVE 525 */ 526 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 527 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 528 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 529 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 530 #endif 531 532 /* 533 * eSPI - Enhanced SPI 534 */ 535 #ifdef CONFIG_SPI_FLASH 536 #ifndef CONFIG_SPL_BUILD 537 #endif 538 539 #define CONFIG_SPI_FLASH_BAR 540 #define CONFIG_SF_DEFAULT_SPEED 10000000 541 #define CONFIG_SF_DEFAULT_MODE 0 542 #endif 543 544 /* 545 * General PCI 546 * Memory space is mapped 1-1, but I/O space must start from 0. 547 */ 548 #define CONFIG_PCI /* Enable PCI/PCIE */ 549 #define CONFIG_PCIE1 /* PCIE controller 1 */ 550 #define CONFIG_PCIE2 /* PCIE controller 2 */ 551 #define CONFIG_PCIE3 /* PCIE controller 3 */ 552 #define CONFIG_PCIE4 /* PCIE controller 4 */ 553 #define CONFIG_FSL_PCIE_RESET 554 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 555 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 556 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 557 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 558 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 559 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 560 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 561 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 562 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 563 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 564 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 565 566 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 567 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 568 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 569 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 570 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 571 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 572 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 573 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 574 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 575 576 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 577 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 578 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 579 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 580 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 581 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 582 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 583 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 584 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 585 586 /* controller 4, Base address 203000 */ 587 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 588 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 589 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 590 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 591 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 592 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 593 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 594 595 #ifdef CONFIG_PCI 596 #define CONFIG_PCI_INDIRECT_BRIDGE 597 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 598 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 599 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 600 #define CONFIG_DOS_PARTITION 601 #endif 602 603 /* Qman/Bman */ 604 #ifndef CONFIG_NOBQFMAN 605 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 606 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 607 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 608 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 609 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 610 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 611 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 612 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 613 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 614 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 615 CONFIG_SYS_BMAN_CENA_SIZE) 616 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 617 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 618 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 619 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 620 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 621 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 622 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 623 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 624 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 625 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 626 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 627 CONFIG_SYS_QMAN_CENA_SIZE) 628 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 629 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 630 631 #define CONFIG_SYS_DPAA_FMAN 632 #define CONFIG_SYS_DPAA_PME 633 #define CONFIG_SYS_PMAN 634 #define CONFIG_SYS_DPAA_DCE 635 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 636 #define CONFIG_SYS_INTERLAKEN 637 638 /* Default address of microcode for the Linux Fman driver */ 639 #if defined(CONFIG_SPIFLASH) 640 /* 641 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 642 * env, so we got 0x110000. 643 */ 644 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 645 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 646 #elif defined(CONFIG_SDCARD) 647 /* 648 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 649 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 650 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 651 */ 652 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 653 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 654 #elif defined(CONFIG_NAND) 655 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 656 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 657 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 658 /* 659 * Slave has no ucode locally, it can fetch this from remote. When implementing 660 * in two corenet boards, slave's ucode could be stored in master's memory 661 * space, the address can be mapped from slave TLB->slave LAW-> 662 * slave SRIO or PCIE outbound window->master inbound window-> 663 * master LAW->the ucode address in master's memory space. 664 */ 665 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 666 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 667 #else 668 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 669 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 670 #endif 671 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 672 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 673 #endif /* CONFIG_NOBQFMAN */ 674 675 #ifdef CONFIG_SYS_DPAA_FMAN 676 #define CONFIG_FMAN_ENET 677 #define CONFIG_PHYLIB_10G 678 #define CONFIG_PHY_VITESSE 679 #define CONFIG_PHY_REALTEK 680 #define CONFIG_PHY_TERANETICS 681 #define RGMII_PHY1_ADDR 0x1 682 #define RGMII_PHY2_ADDR 0x2 683 #define FM1_10GEC1_PHY_ADDR 0x3 684 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 685 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 686 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 687 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 688 #endif 689 690 #ifdef CONFIG_FMAN_ENET 691 #define CONFIG_MII /* MII PHY management */ 692 #define CONFIG_ETHPRIME "FM1@DTSEC3" 693 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 694 #endif 695 696 /* 697 * SATA 698 */ 699 #ifdef CONFIG_FSL_SATA_V2 700 #define CONFIG_LIBATA 701 #define CONFIG_FSL_SATA 702 #define CONFIG_SYS_SATA_MAX_DEVICE 2 703 #define CONFIG_SATA1 704 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 705 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 706 #define CONFIG_SATA2 707 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 708 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 709 #define CONFIG_LBA48 710 #define CONFIG_CMD_SATA 711 #define CONFIG_DOS_PARTITION 712 #endif 713 714 /* 715 * USB 716 */ 717 #ifdef CONFIG_USB_EHCI 718 #define CONFIG_USB_EHCI_FSL 719 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 720 #define CONFIG_HAS_FSL_DR_USB 721 #endif 722 723 /* 724 * SDHC 725 */ 726 #ifdef CONFIG_MMC 727 #define CONFIG_FSL_ESDHC 728 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 729 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 730 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 731 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 732 #define CONFIG_GENERIC_MMC 733 #define CONFIG_DOS_PARTITION 734 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 735 #endif 736 737 /* 738 * Dynamic MTD Partition support with mtdparts 739 */ 740 #ifndef CONFIG_SYS_NO_FLASH 741 #define CONFIG_MTD_DEVICE 742 #define CONFIG_MTD_PARTITIONS 743 #define CONFIG_CMD_MTDPARTS 744 #define CONFIG_FLASH_CFI_MTD 745 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 746 "spi0=spife110000.0" 747 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 748 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 749 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 750 "1m(uboot),5m(kernel),128k(dtb),-(user)" 751 #endif 752 753 /* 754 * Environment 755 */ 756 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 757 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 758 759 /* 760 * Command line configuration. 761 */ 762 #define CONFIG_CMD_ERRATA 763 #define CONFIG_CMD_IRQ 764 #define CONFIG_CMD_REGINFO 765 766 #ifdef CONFIG_PCI 767 #define CONFIG_CMD_PCI 768 #endif 769 770 /* Hash command with SHA acceleration supported in hardware */ 771 #ifdef CONFIG_FSL_CAAM 772 #define CONFIG_CMD_HASH 773 #define CONFIG_SHA_HW_ACCEL 774 #endif 775 776 /* 777 * Miscellaneous configurable options 778 */ 779 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 780 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 781 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 782 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 783 #ifdef CONFIG_CMD_KGDB 784 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 785 #else 786 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 787 #endif 788 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 789 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 790 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 791 792 /* 793 * For booting Linux, the board info and command line data 794 * have to be in the first 64 MB of memory, since this is 795 * the maximum mapped by the Linux kernel during initialization. 796 */ 797 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 798 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 799 800 #ifdef CONFIG_CMD_KGDB 801 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 802 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 803 #endif 804 805 /* 806 * Environment Configuration 807 */ 808 #define CONFIG_ROOTPATH "/opt/nfsroot" 809 #define CONFIG_BOOTFILE "uImage" 810 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 811 812 /* default location for tftp and bootm */ 813 #define CONFIG_LOADADDR 1000000 814 #define CONFIG_BAUDRATE 115200 815 #define __USB_PHY_TYPE utmi 816 817 #define CONFIG_EXTRA_ENV_SETTINGS \ 818 "hwconfig=fsl_ddr:" \ 819 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 820 "bank_intlv=auto;" \ 821 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 822 "netdev=eth0\0" \ 823 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 824 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 825 "tftpflash=tftpboot $loadaddr $uboot && " \ 826 "protect off $ubootaddr +$filesize && " \ 827 "erase $ubootaddr +$filesize && " \ 828 "cp.b $loadaddr $ubootaddr $filesize && " \ 829 "protect on $ubootaddr +$filesize && " \ 830 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 831 "consoledev=ttyS0\0" \ 832 "ramdiskaddr=2000000\0" \ 833 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 834 "fdtaddr=1e00000\0" \ 835 "fdtfile=t2080qds/t2080qds.dtb\0" \ 836 "bdev=sda3\0" 837 838 /* 839 * For emulation this causes u-boot to jump to the start of the 840 * proof point app code automatically 841 */ 842 #define CONFIG_PROOF_POINTS \ 843 "setenv bootargs root=/dev/$bdev rw " \ 844 "console=$consoledev,$baudrate $othbootargs;" \ 845 "cpu 1 release 0x29000000 - - -;" \ 846 "cpu 2 release 0x29000000 - - -;" \ 847 "cpu 3 release 0x29000000 - - -;" \ 848 "cpu 4 release 0x29000000 - - -;" \ 849 "cpu 5 release 0x29000000 - - -;" \ 850 "cpu 6 release 0x29000000 - - -;" \ 851 "cpu 7 release 0x29000000 - - -;" \ 852 "go 0x29000000" 853 854 #define CONFIG_HVBOOT \ 855 "setenv bootargs config-addr=0x60000000; " \ 856 "bootm 0x01000000 - 0x00f00000" 857 858 #define CONFIG_ALU \ 859 "setenv bootargs root=/dev/$bdev rw " \ 860 "console=$consoledev,$baudrate $othbootargs;" \ 861 "cpu 1 release 0x01000000 - - -;" \ 862 "cpu 2 release 0x01000000 - - -;" \ 863 "cpu 3 release 0x01000000 - - -;" \ 864 "cpu 4 release 0x01000000 - - -;" \ 865 "cpu 5 release 0x01000000 - - -;" \ 866 "cpu 6 release 0x01000000 - - -;" \ 867 "cpu 7 release 0x01000000 - - -;" \ 868 "go 0x01000000" 869 870 #define CONFIG_LINUX \ 871 "setenv bootargs root=/dev/ram rw " \ 872 "console=$consoledev,$baudrate $othbootargs;" \ 873 "setenv ramdiskaddr 0x02000000;" \ 874 "setenv fdtaddr 0x00c00000;" \ 875 "setenv loadaddr 0x1000000;" \ 876 "bootm $loadaddr $ramdiskaddr $fdtaddr" 877 878 #define CONFIG_HDBOOT \ 879 "setenv bootargs root=/dev/$bdev rw " \ 880 "console=$consoledev,$baudrate $othbootargs;" \ 881 "tftp $loadaddr $bootfile;" \ 882 "tftp $fdtaddr $fdtfile;" \ 883 "bootm $loadaddr - $fdtaddr" 884 885 #define CONFIG_NFSBOOTCOMMAND \ 886 "setenv bootargs root=/dev/nfs rw " \ 887 "nfsroot=$serverip:$rootpath " \ 888 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 889 "console=$consoledev,$baudrate $othbootargs;" \ 890 "tftp $loadaddr $bootfile;" \ 891 "tftp $fdtaddr $fdtfile;" \ 892 "bootm $loadaddr - $fdtaddr" 893 894 #define CONFIG_RAMBOOTCOMMAND \ 895 "setenv bootargs root=/dev/ram rw " \ 896 "console=$consoledev,$baudrate $othbootargs;" \ 897 "tftp $ramdiskaddr $ramdiskfile;" \ 898 "tftp $loadaddr $bootfile;" \ 899 "tftp $fdtaddr $fdtfile;" \ 900 "bootm $loadaddr $ramdiskaddr $fdtaddr" 901 902 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 903 904 #include <asm/fsl_secure_boot.h> 905 906 #endif /* __T208xQDS_H */ 907