1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 15 #define CONFIG_MMC 16 #define CONFIG_SPI_FLASH 17 #define CONFIG_USB_EHCI 18 #if defined(CONFIG_PPC_T2080) 19 #define CONFIG_T2080QDS 20 #define CONFIG_FSL_SATA_V2 21 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 22 #define CONFIG_SRIO1 /* SRIO port 1 */ 23 #define CONFIG_SRIO2 /* SRIO port 2 */ 24 #elif defined(CONFIG_PPC_T2081) 25 #define CONFIG_T2081QDS 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_PHYS_64BIT 30 #define CONFIG_BOOKE 31 #define CONFIG_E500 /* BOOKE e500 family */ 32 #define CONFIG_E500MC /* BOOKE e500mc family */ 33 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 34 #define CONFIG_MP /* support multiple processors */ 35 #define CONFIG_ENABLE_36BIT_PHYS 36 37 #ifdef CONFIG_PHYS_64BIT 38 #define CONFIG_ADDR_MAP 1 39 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 40 #endif 41 42 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 43 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 44 #define CONFIG_FSL_IFC /* Enable IFC Support */ 45 #define CONFIG_FSL_LAW /* Use common FSL init code */ 46 #define CONFIG_ENV_OVERWRITE 47 48 #ifdef CONFIG_RAMBOOT_PBL 49 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 50 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 51 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 52 #if defined(CONFIG_PPC_T2080) 53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg 54 #elif defined(CONFIG_PPC_T2081) 55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg 56 #endif 57 #endif 58 59 #define CONFIG_SRIO_PCIE_BOOT_MASTER 60 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 61 /* Set 1M boot space */ 62 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 63 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 64 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 65 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 66 #define CONFIG_SYS_NO_FLASH 67 #endif 68 69 #ifndef CONFIG_SYS_TEXT_BASE 70 #define CONFIG_SYS_TEXT_BASE 0xeff40000 71 #endif 72 73 #ifndef CONFIG_RESET_VECTOR_ADDRESS 74 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 75 #endif 76 77 /* 78 * These can be toggled for performance analysis, otherwise use default. 79 */ 80 #define CONFIG_SYS_CACHE_STASHING 81 #define CONFIG_BTB /* toggle branch predition */ 82 #define CONFIG_DDR_ECC 83 #ifdef CONFIG_DDR_ECC 84 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 85 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 86 #endif 87 88 #ifdef CONFIG_SYS_NO_FLASH 89 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 90 #define CONFIG_ENV_IS_NOWHERE 91 #endif 92 #else 93 #define CONFIG_FLASH_CFI_DRIVER 94 #define CONFIG_SYS_FLASH_CFI 95 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 96 #endif 97 98 #if defined(CONFIG_SPIFLASH) 99 #define CONFIG_SYS_EXTRA_ENV_RELOC 100 #define CONFIG_ENV_IS_IN_SPI_FLASH 101 #define CONFIG_ENV_SPI_BUS 0 102 #define CONFIG_ENV_SPI_CS 0 103 #define CONFIG_ENV_SPI_MAX_HZ 10000000 104 #define CONFIG_ENV_SPI_MODE 0 105 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 106 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 107 #define CONFIG_ENV_SECT_SIZE 0x10000 108 #elif defined(CONFIG_SDCARD) 109 #define CONFIG_SYS_EXTRA_ENV_RELOC 110 #define CONFIG_ENV_IS_IN_MMC 111 #define CONFIG_SYS_MMC_ENV_DEV 0 112 #define CONFIG_ENV_SIZE 0x2000 113 #define CONFIG_ENV_OFFSET (512 * 1658) 114 #elif defined(CONFIG_NAND) 115 #define CONFIG_SYS_EXTRA_ENV_RELOC 116 #define CONFIG_ENV_IS_IN_NAND 117 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 118 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 119 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 120 #define CONFIG_ENV_IS_IN_REMOTE 121 #define CONFIG_ENV_ADDR 0xffe20000 122 #define CONFIG_ENV_SIZE 0x2000 123 #elif defined(CONFIG_ENV_IS_NOWHERE) 124 #define CONFIG_ENV_SIZE 0x2000 125 #else 126 #define CONFIG_ENV_IS_IN_FLASH 127 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 128 #define CONFIG_ENV_SIZE 0x2000 129 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 130 #endif 131 132 #ifndef __ASSEMBLY__ 133 unsigned long get_board_sys_clk(void); 134 unsigned long get_board_ddr_clk(void); 135 #endif 136 137 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 138 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 139 140 /* 141 * Config the L3 Cache as L3 SRAM 142 */ 143 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 144 145 #define CONFIG_SYS_DCSRBAR 0xf0000000 146 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 147 148 /* EEPROM */ 149 #define CONFIG_ID_EEPROM 150 #define CONFIG_SYS_I2C_EEPROM_NXID 151 #define CONFIG_SYS_EEPROM_BUS_NUM 0 152 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 153 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 154 155 /* 156 * DDR Setup 157 */ 158 #define CONFIG_VERY_BIG_RAM 159 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 160 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 161 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 162 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 163 #define CONFIG_DDR_SPD 164 #define CONFIG_SYS_FSL_DDR3 165 #undef CONFIG_FSL_DDR_INTERACTIVE 166 #define CONFIG_SYS_SPD_BUS_NUM 0 167 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 168 #define SPD_EEPROM_ADDRESS1 0x51 169 #define SPD_EEPROM_ADDRESS2 0x52 170 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 171 #define CTRL_INTLV_PREFERED cacheline 172 173 /* 174 * IFC Definitions 175 */ 176 #define CONFIG_SYS_FLASH_BASE 0xe0000000 177 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 178 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 179 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 180 + 0x8000000) | \ 181 CSPR_PORT_SIZE_16 | \ 182 CSPR_MSEL_NOR | \ 183 CSPR_V) 184 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 185 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 186 CSPR_PORT_SIZE_16 | \ 187 CSPR_MSEL_NOR | \ 188 CSPR_V) 189 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 190 /* NOR Flash Timing Params */ 191 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 192 193 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 194 FTIM0_NOR_TEADC(0x5) | \ 195 FTIM0_NOR_TEAHC(0x5)) 196 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 197 FTIM1_NOR_TRAD_NOR(0x1A) |\ 198 FTIM1_NOR_TSEQRAD_NOR(0x13)) 199 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 200 FTIM2_NOR_TCH(0x4) | \ 201 FTIM2_NOR_TWPH(0x0E) | \ 202 FTIM2_NOR_TWP(0x1c)) 203 #define CONFIG_SYS_NOR_FTIM3 0x0 204 205 #define CONFIG_SYS_FLASH_QUIET_TEST 206 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 207 208 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 209 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 210 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 211 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 212 213 #define CONFIG_SYS_FLASH_EMPTY_INFO 214 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 215 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 216 217 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 218 #define QIXIS_BASE 0xffdf0000 219 #define QIXIS_LBMAP_SWITCH 6 220 #define QIXIS_LBMAP_MASK 0x0f 221 #define QIXIS_LBMAP_SHIFT 0 222 #define QIXIS_LBMAP_DFLTBANK 0x00 223 #define QIXIS_LBMAP_ALTBANK 0x04 224 #define QIXIS_RST_CTL_RESET 0x83 225 #define QIXIS_RST_FORCE_MEM 0x1 226 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 227 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 228 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 229 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 230 231 #define CONFIG_SYS_CSPR3_EXT (0xf) 232 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 233 | CSPR_PORT_SIZE_8 \ 234 | CSPR_MSEL_GPCM \ 235 | CSPR_V) 236 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 237 #define CONFIG_SYS_CSOR3 0x0 238 /* QIXIS Timing parameters for IFC CS3 */ 239 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 240 FTIM0_GPCM_TEADC(0x0e) | \ 241 FTIM0_GPCM_TEAHC(0x0e)) 242 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 243 FTIM1_GPCM_TRAD(0x3f)) 244 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 245 FTIM2_GPCM_TCH(0x8) | \ 246 FTIM2_GPCM_TWP(0x1f)) 247 #define CONFIG_SYS_CS3_FTIM3 0x0 248 249 /* NAND Flash on IFC */ 250 #define CONFIG_NAND_FSL_IFC 251 #define CONFIG_SYS_NAND_BASE 0xff800000 252 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 253 254 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 255 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 256 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 257 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 258 | CSPR_V) 259 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 260 261 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 262 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 263 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 264 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 265 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 266 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 267 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 268 269 #define CONFIG_SYS_NAND_ONFI_DETECTION 270 271 /* ONFI NAND Flash mode0 Timing Params */ 272 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 273 FTIM0_NAND_TWP(0x18) | \ 274 FTIM0_NAND_TWCHT(0x07) | \ 275 FTIM0_NAND_TWH(0x0a)) 276 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 277 FTIM1_NAND_TWBE(0x39) | \ 278 FTIM1_NAND_TRR(0x0e) | \ 279 FTIM1_NAND_TRP(0x18)) 280 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 281 FTIM2_NAND_TREH(0x0a) | \ 282 FTIM2_NAND_TWHRE(0x1e)) 283 #define CONFIG_SYS_NAND_FTIM3 0x0 284 285 #define CONFIG_SYS_NAND_DDR_LAW 11 286 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 287 #define CONFIG_SYS_MAX_NAND_DEVICE 1 288 #define CONFIG_MTD_NAND_VERIFY_WRITE 289 #define CONFIG_CMD_NAND 290 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 291 292 #if defined(CONFIG_NAND) 293 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 294 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 295 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 296 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 297 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 298 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 299 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 300 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 301 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 302 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 303 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 304 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 305 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 306 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 307 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 308 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 309 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 310 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 311 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 312 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 313 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 314 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 315 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 316 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 317 #else 318 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 319 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 320 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 321 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 322 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 323 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 324 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 325 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 326 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 327 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 328 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 329 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 330 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 331 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 332 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 333 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 334 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 335 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 336 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 337 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 338 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 339 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 340 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 341 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 342 #endif 343 344 #if defined(CONFIG_RAMBOOT_PBL) 345 #define CONFIG_SYS_RAMBOOT 346 #endif 347 348 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 349 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 350 #define CONFIG_MISC_INIT_R 351 #define CONFIG_HWCONFIG 352 353 /* define to use L1 as initial stack */ 354 #define CONFIG_L1_INIT_RAM 355 #define CONFIG_SYS_INIT_RAM_LOCK 356 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 357 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 358 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 359 /* The assembler doesn't like typecast */ 360 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 361 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 362 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 363 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 364 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 365 GENERATED_GBL_DATA_SIZE) 366 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 367 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 368 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 369 370 /* 371 * Serial Port 372 */ 373 #define CONFIG_CONS_INDEX 1 374 #define CONFIG_SYS_NS16550 375 #define CONFIG_SYS_NS16550_SERIAL 376 #define CONFIG_SYS_NS16550_REG_SIZE 1 377 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 378 #define CONFIG_SYS_BAUDRATE_TABLE \ 379 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 380 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 381 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 382 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 383 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 384 385 /* Use the HUSH parser */ 386 #define CONFIG_SYS_HUSH_PARSER 387 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 388 389 /* pass open firmware flat tree */ 390 #define CONFIG_OF_LIBFDT 391 #define CONFIG_OF_BOARD_SETUP 392 #define CONFIG_OF_STDOUT_VIA_ALIAS 393 394 /* new uImage format support */ 395 #define CONFIG_FIT 396 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 397 398 /* 399 * I2C 400 */ 401 #define CONFIG_SYS_I2C 402 #define CONFIG_SYS_I2C_FSL 403 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 404 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 405 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 406 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 407 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 408 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 409 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 410 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 411 #define CONFIG_SYS_FSL_I2C_SPEED 100000 412 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 413 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 414 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 415 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 416 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 417 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 418 #define I2C_MUX_CH_DEFAULT 0x8 419 420 421 /* 422 * RapidIO 423 */ 424 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 425 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 426 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 427 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 428 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 429 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 430 /* 431 * for slave u-boot IMAGE instored in master memory space, 432 * PHYS must be aligned based on the SIZE 433 */ 434 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 435 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 436 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 437 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 438 /* 439 * for slave UCODE and ENV instored in master memory space, 440 * PHYS must be aligned based on the SIZE 441 */ 442 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 443 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 444 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 445 446 /* slave core release by master*/ 447 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 448 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 449 450 /* 451 * SRIO_PCIE_BOOT - SLAVE 452 */ 453 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 454 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 455 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 456 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 457 #endif 458 459 /* 460 * eSPI - Enhanced SPI 461 */ 462 #ifdef CONFIG_SPI_FLASH 463 #define CONFIG_FSL_ESPI 464 #define CONFIG_SPI_FLASH_SST 465 #define CONFIG_SPI_FLASH_STMICRO 466 #if defined(CONFIG_T2080QDS) 467 #define CONFIG_SPI_FLASH_SPANSION 468 #elif defined(CONFIG_T2081QDS) 469 #define CONFIG_SPI_FLASH_EON 470 #endif 471 472 #define CONFIG_CMD_SF 473 #define CONFIG_SF_DEFAULT_SPEED 10000000 474 #define CONFIG_SF_DEFAULT_MODE 0 475 #endif 476 477 /* 478 * General PCI 479 * Memory space is mapped 1-1, but I/O space must start from 0. 480 */ 481 #define CONFIG_PCI /* Enable PCI/PCIE */ 482 #define CONFIG_PCIE1 /* PCIE controler 1 */ 483 #define CONFIG_PCIE2 /* PCIE controler 2 */ 484 #define CONFIG_PCIE3 /* PCIE controler 3 */ 485 #define CONFIG_PCIE4 /* PCIE controler 4 */ 486 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 487 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 488 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 489 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 490 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 491 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 492 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 493 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 494 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 495 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 496 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 497 498 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 499 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 500 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 501 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 502 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 503 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 504 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 505 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 506 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 507 508 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 509 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 510 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 511 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 512 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 513 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 514 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 515 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 516 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 517 518 /* controller 4, Base address 203000 */ 519 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 520 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 521 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 522 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 523 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 524 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 525 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 526 527 #ifdef CONFIG_PCI 528 #define CONFIG_PCI_INDIRECT_BRIDGE 529 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 530 #define CONFIG_NET_MULTI 531 #define CONFIG_E1000 532 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 533 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 534 #define CONFIG_DOS_PARTITION 535 #endif 536 537 /* Qman/Bman */ 538 #ifndef CONFIG_NOBQFMAN 539 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 540 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 541 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 542 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 543 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 544 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 545 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 546 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 547 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 548 549 #define CONFIG_SYS_DPAA_FMAN 550 #define CONFIG_SYS_DPAA_PME 551 #define CONFIG_SYS_PMAN 552 #define CONFIG_SYS_DPAA_DCE 553 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 554 #define CONFIG_SYS_INTERLAKEN 555 556 /* Default address of microcode for the Linux Fman driver */ 557 #if defined(CONFIG_SPIFLASH) 558 /* 559 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 560 * env, so we got 0x110000. 561 */ 562 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 563 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 564 #elif defined(CONFIG_SDCARD) 565 /* 566 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 567 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 568 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 569 */ 570 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 571 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 572 #elif defined(CONFIG_NAND) 573 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 574 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 575 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 576 /* 577 * Slave has no ucode locally, it can fetch this from remote. When implementing 578 * in two corenet boards, slave's ucode could be stored in master's memory 579 * space, the address can be mapped from slave TLB->slave LAW-> 580 * slave SRIO or PCIE outbound window->master inbound window-> 581 * master LAW->the ucode address in master's memory space. 582 */ 583 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 584 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 585 #else 586 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 587 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 588 #endif 589 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 590 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 591 #endif /* CONFIG_NOBQFMAN */ 592 593 #ifdef CONFIG_SYS_DPAA_FMAN 594 #define CONFIG_FMAN_ENET 595 #define CONFIG_PHYLIB_10G 596 #define CONFIG_PHY_VITESSE 597 #define CONFIG_PHY_REALTEK 598 #define CONFIG_PHY_TERANETICS 599 #define RGMII_PHY1_ADDR 0x1 600 #define RGMII_PHY2_ADDR 0x2 601 #define FM1_10GEC1_PHY_ADDR 0x3 602 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 603 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 604 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 605 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 606 #endif 607 608 #ifdef CONFIG_FMAN_ENET 609 #define CONFIG_MII /* MII PHY management */ 610 #define CONFIG_ETHPRIME "FM1@DTSEC3" 611 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 612 #endif 613 614 /* 615 * SATA 616 */ 617 #ifdef CONFIG_FSL_SATA_V2 618 #define CONFIG_LIBATA 619 #define CONFIG_FSL_SATA 620 #define CONFIG_SYS_SATA_MAX_DEVICE 2 621 #define CONFIG_SATA1 622 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 623 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 624 #define CONFIG_SATA2 625 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 626 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 627 #define CONFIG_LBA48 628 #define CONFIG_CMD_SATA 629 #define CONFIG_DOS_PARTITION 630 #define CONFIG_CMD_EXT2 631 #endif 632 633 /* 634 * USB 635 */ 636 #ifdef CONFIG_USB_EHCI 637 #define CONFIG_CMD_USB 638 #define CONFIG_USB_STORAGE 639 #define CONFIG_USB_EHCI_FSL 640 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 641 #define CONFIG_CMD_EXT2 642 #define CONFIG_HAS_FSL_DR_USB 643 #endif 644 645 /* 646 * SDHC 647 */ 648 #ifdef CONFIG_MMC 649 #define CONFIG_CMD_MMC 650 #define CONFIG_FSL_ESDHC 651 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 652 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 653 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 654 #define CONFIG_GENERIC_MMC 655 #define CONFIG_CMD_EXT2 656 #define CONFIG_CMD_FAT 657 #define CONFIG_DOS_PARTITION 658 #endif 659 660 661 /* 662 * Dynamic MTD Partition support with mtdparts 663 */ 664 #ifndef CONFIG_SYS_NO_FLASH 665 #define CONFIG_MTD_DEVICE 666 #define CONFIG_MTD_PARTITIONS 667 #define CONFIG_CMD_MTDPARTS 668 #define CONFIG_FLASH_CFI_MTD 669 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 670 "spi0=spife110000.0" 671 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 672 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 673 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 674 "1m(uboot),5m(kernel),128k(dtb),-(user)" 675 #endif 676 677 /* 678 * Environment 679 */ 680 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 681 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 682 683 /* 684 * Command line configuration. 685 */ 686 #include <config_cmd_default.h> 687 688 #define CONFIG_CMD_DHCP 689 #define CONFIG_CMD_ELF 690 #define CONFIG_CMD_ERRATA 691 #define CONFIG_CMD_GREPENV 692 #define CONFIG_CMD_IRQ 693 #define CONFIG_CMD_I2C 694 #define CONFIG_CMD_MII 695 #define CONFIG_CMD_PING 696 #define CONFIG_CMD_SETEXPR 697 #define CONFIG_CMD_REGINFO 698 #define CONFIG_CMD_BDI 699 700 #ifdef CONFIG_PCI 701 #define CONFIG_CMD_PCI 702 #define CONFIG_CMD_NET 703 #endif 704 705 /* 706 * Miscellaneous configurable options 707 */ 708 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 709 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 710 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 711 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 712 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 713 #ifdef CONFIG_CMD_KGDB 714 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 715 #else 716 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 717 #endif 718 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 719 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 720 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 721 722 /* 723 * For booting Linux, the board info and command line data 724 * have to be in the first 64 MB of memory, since this is 725 * the maximum mapped by the Linux kernel during initialization. 726 */ 727 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 728 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 729 730 #ifdef CONFIG_CMD_KGDB 731 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 732 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 733 #endif 734 735 /* 736 * Environment Configuration 737 */ 738 #define CONFIG_ROOTPATH "/opt/nfsroot" 739 #define CONFIG_BOOTFILE "uImage" 740 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 741 742 /* default location for tftp and bootm */ 743 #define CONFIG_LOADADDR 1000000 744 #define CONFIG_BAUDRATE 115200 745 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 746 #define __USB_PHY_TYPE utmi 747 748 #define CONFIG_EXTRA_ENV_SETTINGS \ 749 "hwconfig=fsl_ddr:" \ 750 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 751 "bank_intlv=auto;" \ 752 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 753 "netdev=eth0\0" \ 754 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 755 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 756 "tftpflash=tftpboot $loadaddr $uboot && " \ 757 "protect off $ubootaddr +$filesize && " \ 758 "erase $ubootaddr +$filesize && " \ 759 "cp.b $loadaddr $ubootaddr $filesize && " \ 760 "protect on $ubootaddr +$filesize && " \ 761 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 762 "consoledev=ttyS0\0" \ 763 "ramdiskaddr=2000000\0" \ 764 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 765 "fdtaddr=c00000\0" \ 766 "fdtfile=t2080qds/t2080qds.dtb\0" \ 767 "bdev=sda3\0" \ 768 "c=ffe\0" 769 770 /* 771 * For emulation this causes u-boot to jump to the start of the 772 * proof point app code automatically 773 */ 774 #define CONFIG_PROOF_POINTS \ 775 "setenv bootargs root=/dev/$bdev rw " \ 776 "console=$consoledev,$baudrate $othbootargs;" \ 777 "cpu 1 release 0x29000000 - - -;" \ 778 "cpu 2 release 0x29000000 - - -;" \ 779 "cpu 3 release 0x29000000 - - -;" \ 780 "cpu 4 release 0x29000000 - - -;" \ 781 "cpu 5 release 0x29000000 - - -;" \ 782 "cpu 6 release 0x29000000 - - -;" \ 783 "cpu 7 release 0x29000000 - - -;" \ 784 "go 0x29000000" 785 786 #define CONFIG_HVBOOT \ 787 "setenv bootargs config-addr=0x60000000; " \ 788 "bootm 0x01000000 - 0x00f00000" 789 790 #define CONFIG_ALU \ 791 "setenv bootargs root=/dev/$bdev rw " \ 792 "console=$consoledev,$baudrate $othbootargs;" \ 793 "cpu 1 release 0x01000000 - - -;" \ 794 "cpu 2 release 0x01000000 - - -;" \ 795 "cpu 3 release 0x01000000 - - -;" \ 796 "cpu 4 release 0x01000000 - - -;" \ 797 "cpu 5 release 0x01000000 - - -;" \ 798 "cpu 6 release 0x01000000 - - -;" \ 799 "cpu 7 release 0x01000000 - - -;" \ 800 "go 0x01000000" 801 802 #define CONFIG_LINUX \ 803 "setenv bootargs root=/dev/ram rw " \ 804 "console=$consoledev,$baudrate $othbootargs;" \ 805 "setenv ramdiskaddr 0x02000000;" \ 806 "setenv fdtaddr 0x00c00000;" \ 807 "setenv loadaddr 0x1000000;" \ 808 "bootm $loadaddr $ramdiskaddr $fdtaddr" 809 810 #define CONFIG_HDBOOT \ 811 "setenv bootargs root=/dev/$bdev rw " \ 812 "console=$consoledev,$baudrate $othbootargs;" \ 813 "tftp $loadaddr $bootfile;" \ 814 "tftp $fdtaddr $fdtfile;" \ 815 "bootm $loadaddr - $fdtaddr" 816 817 #define CONFIG_NFSBOOTCOMMAND \ 818 "setenv bootargs root=/dev/nfs rw " \ 819 "nfsroot=$serverip:$rootpath " \ 820 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 821 "console=$consoledev,$baudrate $othbootargs;" \ 822 "tftp $loadaddr $bootfile;" \ 823 "tftp $fdtaddr $fdtfile;" \ 824 "bootm $loadaddr - $fdtaddr" 825 826 #define CONFIG_RAMBOOTCOMMAND \ 827 "setenv bootargs root=/dev/ram rw " \ 828 "console=$consoledev,$baudrate $othbootargs;" \ 829 "tftp $ramdiskaddr $ramdiskfile;" \ 830 "tftp $loadaddr $bootfile;" \ 831 "tftp $fdtaddr $fdtfile;" \ 832 "bootm $loadaddr $ramdiskaddr $fdtaddr" 833 834 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 835 836 #ifdef CONFIG_SECURE_BOOT 837 #include <asm/fsl_secure_boot.h> 838 #undef CONFIG_CMD_USB 839 #endif 840 841 #endif /* __T208xQDS_H */ 842