1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #include <asm/config_mpc85xx.h> 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 17 #ifndef CONFIG_SECURE_BOOT 18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 19 #else 20 #define CONFIG_SYS_FSL_PBL_PBI \ 21 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 22 #endif 23 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x30001000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #ifdef CONFIG_SPL_BUILD 31 #define CONFIG_SPL_SKIP_RELOCATE 32 #define CONFIG_SPL_COMMON_INIT_DDR 33 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 34 #define CONFIG_SYS_NO_FLASH 35 #endif 36 #define RESET_VECTOR_OFFSET 0x27FFC 37 #define BOOT_PAGE_OFFSET 0x27000 38 39 #ifdef CONFIG_NAND 40 #ifdef CONFIG_SECURE_BOOT 41 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 42 /* 43 * HDR would be appended at end of image and copied to DDR along 44 * with U-Boot image. 45 */ 46 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 47 CONFIG_U_BOOT_HDR_SIZE) 48 #else 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 50 #endif 51 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 52 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 55 #ifdef CONFIG_TARGET_T1040RDB 56 #define CONFIG_SYS_FSL_PBL_RCW \ 57 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 58 #endif 59 #ifdef CONFIG_TARGET_T1042RDB_PI 60 #define CONFIG_SYS_FSL_PBL_RCW \ 61 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 62 #endif 63 #ifdef CONFIG_TARGET_T1042RDB 64 #define CONFIG_SYS_FSL_PBL_RCW \ 65 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 66 #endif 67 #ifdef CONFIG_TARGET_T1040D4RDB 68 #define CONFIG_SYS_FSL_PBL_RCW \ 69 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 70 #endif 71 #ifdef CONFIG_TARGET_T1042D4RDB 72 #define CONFIG_SYS_FSL_PBL_RCW \ 73 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 74 #endif 75 #define CONFIG_SPL_NAND_BOOT 76 #endif 77 78 #ifdef CONFIG_SPIFLASH 79 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 80 #define CONFIG_SPL_SPI_FLASH_MINIMAL 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 86 #ifndef CONFIG_SPL_BUILD 87 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 88 #endif 89 #ifdef CONFIG_TARGET_T1040RDB 90 #define CONFIG_SYS_FSL_PBL_RCW \ 91 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 92 #endif 93 #ifdef CONFIG_TARGET_T1042RDB_PI 94 #define CONFIG_SYS_FSL_PBL_RCW \ 95 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 96 #endif 97 #ifdef CONFIG_TARGET_T1042RDB 98 #define CONFIG_SYS_FSL_PBL_RCW \ 99 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 100 #endif 101 #ifdef CONFIG_TARGET_T1040D4RDB 102 #define CONFIG_SYS_FSL_PBL_RCW \ 103 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 104 #endif 105 #ifdef CONFIG_TARGET_T1042D4RDB 106 #define CONFIG_SYS_FSL_PBL_RCW \ 107 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 108 #endif 109 #define CONFIG_SPL_SPI_BOOT 110 #endif 111 112 #ifdef CONFIG_SDCARD 113 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 114 #define CONFIG_SPL_MMC_MINIMAL 115 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 116 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 117 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 118 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 119 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 120 #ifndef CONFIG_SPL_BUILD 121 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 122 #endif 123 #ifdef CONFIG_TARGET_T1040RDB 124 #define CONFIG_SYS_FSL_PBL_RCW \ 125 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 126 #endif 127 #ifdef CONFIG_TARGET_T1042RDB_PI 128 #define CONFIG_SYS_FSL_PBL_RCW \ 129 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 130 #endif 131 #ifdef CONFIG_TARGET_T1042RDB 132 #define CONFIG_SYS_FSL_PBL_RCW \ 133 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 134 #endif 135 #ifdef CONFIG_TARGET_T1040D4RDB 136 #define CONFIG_SYS_FSL_PBL_RCW \ 137 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 138 #endif 139 #ifdef CONFIG_TARGET_T1042D4RDB 140 #define CONFIG_SYS_FSL_PBL_RCW \ 141 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 142 #endif 143 #define CONFIG_SPL_MMC_BOOT 144 #endif 145 146 #endif 147 148 /* High Level Configuration Options */ 149 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 150 #define CONFIG_MP /* support multiple processors */ 151 152 /* support deep sleep */ 153 #define CONFIG_DEEP_SLEEP 154 155 #ifndef CONFIG_SYS_TEXT_BASE 156 #define CONFIG_SYS_TEXT_BASE 0xeff40000 157 #endif 158 159 #ifndef CONFIG_RESET_VECTOR_ADDRESS 160 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 161 #endif 162 163 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 164 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 165 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 166 #define CONFIG_PCI_INDIRECT_BRIDGE 167 #define CONFIG_PCIE1 /* PCIE controller 1 */ 168 #define CONFIG_PCIE2 /* PCIE controller 2 */ 169 #define CONFIG_PCIE3 /* PCIE controller 3 */ 170 #define CONFIG_PCIE4 /* PCIE controller 4 */ 171 172 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 173 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 174 175 #define CONFIG_ENV_OVERWRITE 176 177 #ifndef CONFIG_SYS_NO_FLASH 178 #define CONFIG_FLASH_CFI_DRIVER 179 #define CONFIG_SYS_FLASH_CFI 180 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 181 #endif 182 183 #if defined(CONFIG_SPIFLASH) 184 #define CONFIG_SYS_EXTRA_ENV_RELOC 185 #define CONFIG_ENV_IS_IN_SPI_FLASH 186 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 187 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 188 #define CONFIG_ENV_SECT_SIZE 0x10000 189 #elif defined(CONFIG_SDCARD) 190 #define CONFIG_SYS_EXTRA_ENV_RELOC 191 #define CONFIG_ENV_IS_IN_MMC 192 #define CONFIG_SYS_MMC_ENV_DEV 0 193 #define CONFIG_ENV_SIZE 0x2000 194 #define CONFIG_ENV_OFFSET (512 * 0x800) 195 #elif defined(CONFIG_NAND) 196 #ifdef CONFIG_SECURE_BOOT 197 #define CONFIG_RAMBOOT_NAND 198 #define CONFIG_BOOTSCRIPT_COPY_RAM 199 #endif 200 #define CONFIG_SYS_EXTRA_ENV_RELOC 201 #define CONFIG_ENV_IS_IN_NAND 202 #define CONFIG_ENV_SIZE 0x2000 203 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 204 #else 205 #define CONFIG_ENV_IS_IN_FLASH 206 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 207 #define CONFIG_ENV_SIZE 0x2000 208 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 209 #endif 210 211 #define CONFIG_SYS_CLK_FREQ 100000000 212 #define CONFIG_DDR_CLK_FREQ 66666666 213 214 /* 215 * These can be toggled for performance analysis, otherwise use default. 216 */ 217 #define CONFIG_SYS_CACHE_STASHING 218 #define CONFIG_BACKSIDE_L2_CACHE 219 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 220 #define CONFIG_BTB /* toggle branch predition */ 221 #define CONFIG_DDR_ECC 222 #ifdef CONFIG_DDR_ECC 223 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 224 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 225 #endif 226 227 #define CONFIG_ENABLE_36BIT_PHYS 228 229 #define CONFIG_ADDR_MAP 230 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 231 232 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 233 #define CONFIG_SYS_MEMTEST_END 0x00400000 234 #define CONFIG_SYS_ALT_MEMTEST 235 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 236 237 /* 238 * Config the L3 Cache as L3 SRAM 239 */ 240 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 241 /* 242 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 243 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 244 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 245 */ 246 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 247 #define CONFIG_SYS_L3_SIZE 256 << 10 248 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 249 #ifdef CONFIG_RAMBOOT_PBL 250 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 251 #endif 252 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 253 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 254 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 255 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 256 257 #define CONFIG_SYS_DCSRBAR 0xf0000000 258 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 259 260 /* 261 * DDR Setup 262 */ 263 #define CONFIG_VERY_BIG_RAM 264 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 265 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 266 267 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 268 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 269 270 #define CONFIG_DDR_SPD 271 272 #define CONFIG_SYS_SPD_BUS_NUM 0 273 #define SPD_EEPROM_ADDRESS 0x51 274 275 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 276 277 /* 278 * IFC Definitions 279 */ 280 #define CONFIG_SYS_FLASH_BASE 0xe8000000 281 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 282 283 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 284 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 285 CSPR_PORT_SIZE_16 | \ 286 CSPR_MSEL_NOR | \ 287 CSPR_V) 288 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 289 290 /* 291 * TDM Definition 292 */ 293 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 294 295 /* NOR Flash Timing Params */ 296 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 297 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 298 FTIM0_NOR_TEADC(0x5) | \ 299 FTIM0_NOR_TEAHC(0x5)) 300 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 301 FTIM1_NOR_TRAD_NOR(0x1A) |\ 302 FTIM1_NOR_TSEQRAD_NOR(0x13)) 303 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 304 FTIM2_NOR_TCH(0x4) | \ 305 FTIM2_NOR_TWPH(0x0E) | \ 306 FTIM2_NOR_TWP(0x1c)) 307 #define CONFIG_SYS_NOR_FTIM3 0x0 308 309 #define CONFIG_SYS_FLASH_QUIET_TEST 310 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 311 312 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 313 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 314 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 315 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 316 317 #define CONFIG_SYS_FLASH_EMPTY_INFO 318 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 319 320 /* CPLD on IFC */ 321 #define CPLD_LBMAP_MASK 0x3F 322 #define CPLD_BANK_SEL_MASK 0x07 323 #define CPLD_BANK_OVERRIDE 0x40 324 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 325 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 326 #define CPLD_LBMAP_RESET 0xFF 327 #define CPLD_LBMAP_SHIFT 0x03 328 329 #if defined(CONFIG_TARGET_T1042RDB_PI) 330 #define CPLD_DIU_SEL_DFP 0x80 331 #elif defined(CONFIG_TARGET_T1042D4RDB) 332 #define CPLD_DIU_SEL_DFP 0xc0 333 #endif 334 335 #if defined(CONFIG_TARGET_T1040D4RDB) 336 #define CPLD_INT_MASK_ALL 0xFF 337 #define CPLD_INT_MASK_THERM 0x80 338 #define CPLD_INT_MASK_DVI_DFP 0x40 339 #define CPLD_INT_MASK_QSGMII1 0x20 340 #define CPLD_INT_MASK_QSGMII2 0x10 341 #define CPLD_INT_MASK_SGMI1 0x08 342 #define CPLD_INT_MASK_SGMI2 0x04 343 #define CPLD_INT_MASK_TDMR1 0x02 344 #define CPLD_INT_MASK_TDMR2 0x01 345 #endif 346 347 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 348 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 349 #define CONFIG_SYS_CSPR2_EXT (0xf) 350 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 351 | CSPR_PORT_SIZE_8 \ 352 | CSPR_MSEL_GPCM \ 353 | CSPR_V) 354 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 355 #define CONFIG_SYS_CSOR2 0x0 356 /* CPLD Timing parameters for IFC CS2 */ 357 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 358 FTIM0_GPCM_TEADC(0x0e) | \ 359 FTIM0_GPCM_TEAHC(0x0e)) 360 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 361 FTIM1_GPCM_TRAD(0x1f)) 362 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 363 FTIM2_GPCM_TCH(0x8) | \ 364 FTIM2_GPCM_TWP(0x1f)) 365 #define CONFIG_SYS_CS2_FTIM3 0x0 366 367 /* NAND Flash on IFC */ 368 #define CONFIG_NAND_FSL_IFC 369 #define CONFIG_SYS_NAND_BASE 0xff800000 370 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 371 372 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 373 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 374 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 375 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 376 | CSPR_V) 377 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 378 379 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 380 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 381 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 382 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 383 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 384 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 385 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 386 387 #define CONFIG_SYS_NAND_ONFI_DETECTION 388 389 /* ONFI NAND Flash mode0 Timing Params */ 390 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 391 FTIM0_NAND_TWP(0x18) | \ 392 FTIM0_NAND_TWCHT(0x07) | \ 393 FTIM0_NAND_TWH(0x0a)) 394 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 395 FTIM1_NAND_TWBE(0x39) | \ 396 FTIM1_NAND_TRR(0x0e) | \ 397 FTIM1_NAND_TRP(0x18)) 398 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 399 FTIM2_NAND_TREH(0x0a) | \ 400 FTIM2_NAND_TWHRE(0x1e)) 401 #define CONFIG_SYS_NAND_FTIM3 0x0 402 403 #define CONFIG_SYS_NAND_DDR_LAW 11 404 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 405 #define CONFIG_SYS_MAX_NAND_DEVICE 1 406 #define CONFIG_CMD_NAND 407 408 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 409 410 #if defined(CONFIG_NAND) 411 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 412 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 413 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 414 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 415 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 416 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 417 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 418 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 419 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 420 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 421 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 422 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 423 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 424 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 425 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 426 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 427 #else 428 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 429 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 430 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 431 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 432 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 433 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 434 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 435 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 436 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 437 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 438 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 439 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 440 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 441 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 442 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 443 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 444 #endif 445 446 #ifdef CONFIG_SPL_BUILD 447 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 448 #else 449 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 450 #endif 451 452 #if defined(CONFIG_RAMBOOT_PBL) 453 #define CONFIG_SYS_RAMBOOT 454 #endif 455 456 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 457 #if defined(CONFIG_NAND) 458 #define CONFIG_A008044_WORKAROUND 459 #endif 460 #endif 461 462 #define CONFIG_BOARD_EARLY_INIT_R 463 #define CONFIG_MISC_INIT_R 464 465 #define CONFIG_HWCONFIG 466 467 /* define to use L1 as initial stack */ 468 #define CONFIG_L1_INIT_RAM 469 #define CONFIG_SYS_INIT_RAM_LOCK 470 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 473 /* The assembler doesn't like typecast */ 474 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 475 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 476 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 477 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 478 479 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 480 GENERATED_GBL_DATA_SIZE) 481 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 482 483 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 484 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 485 486 /* Serial Port - controlled on board with jumper J8 487 * open - index 2 488 * shorted - index 1 489 */ 490 #define CONFIG_CONS_INDEX 1 491 #define CONFIG_SYS_NS16550_SERIAL 492 #define CONFIG_SYS_NS16550_REG_SIZE 1 493 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 494 495 #define CONFIG_SYS_BAUDRATE_TABLE \ 496 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 497 498 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 499 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 500 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 501 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 502 503 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) 504 /* Video */ 505 #define CONFIG_FSL_DIU_FB 506 507 #ifdef CONFIG_FSL_DIU_FB 508 #define CONFIG_FSL_DIU_CH7301 509 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 510 #define CONFIG_CMD_BMP 511 #define CONFIG_VIDEO_LOGO 512 #define CONFIG_VIDEO_BMP_LOGO 513 #endif 514 #endif 515 516 /* I2C */ 517 #define CONFIG_SYS_I2C 518 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 519 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 520 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 521 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 522 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 523 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 524 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 525 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 526 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 527 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 528 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 529 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 530 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 531 532 /* I2C bus multiplexer */ 533 #define I2C_MUX_PCA_ADDR 0x70 534 #define I2C_MUX_CH_DEFAULT 0x8 535 536 #if defined(CONFIG_TARGET_T1042RDB_PI) || \ 537 defined(CONFIG_TARGET_T1040D4RDB) || \ 538 defined(CONFIG_TARGET_T1042D4RDB) 539 /* LDI/DVI Encoder for display */ 540 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 541 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 542 543 /* 544 * RTC configuration 545 */ 546 #define RTC 547 #define CONFIG_RTC_DS1337 1 548 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 549 550 /*DVI encoder*/ 551 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 552 #endif 553 554 /* 555 * eSPI - Enhanced SPI 556 */ 557 #define CONFIG_SPI_FLASH_BAR 558 #define CONFIG_SF_DEFAULT_SPEED 10000000 559 #define CONFIG_SF_DEFAULT_MODE 0 560 #define CONFIG_ENV_SPI_BUS 0 561 #define CONFIG_ENV_SPI_CS 0 562 #define CONFIG_ENV_SPI_MAX_HZ 10000000 563 #define CONFIG_ENV_SPI_MODE 0 564 565 /* 566 * General PCI 567 * Memory space is mapped 1-1, but I/O space must start from 0. 568 */ 569 570 #ifdef CONFIG_PCI 571 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 572 #ifdef CONFIG_PCIE1 573 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 574 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 575 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 576 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 577 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 578 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 579 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 580 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 581 #endif 582 583 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 584 #ifdef CONFIG_PCIE2 585 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 586 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 587 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 588 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 589 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 590 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 591 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 592 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 593 #endif 594 595 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 596 #ifdef CONFIG_PCIE3 597 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 598 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 599 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 600 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 601 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 602 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 603 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 604 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 605 #endif 606 607 /* controller 4, Base address 203000 */ 608 #ifdef CONFIG_PCIE4 609 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 610 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 611 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 612 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 613 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 614 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 615 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 616 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 617 #endif 618 619 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 620 #define CONFIG_DOS_PARTITION 621 #endif /* CONFIG_PCI */ 622 623 /* SATA */ 624 #define CONFIG_FSL_SATA_V2 625 #ifdef CONFIG_FSL_SATA_V2 626 #define CONFIG_LIBATA 627 #define CONFIG_FSL_SATA 628 629 #define CONFIG_SYS_SATA_MAX_DEVICE 1 630 #define CONFIG_SATA1 631 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 632 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 633 634 #define CONFIG_LBA48 635 #define CONFIG_CMD_SATA 636 #define CONFIG_DOS_PARTITION 637 #endif 638 639 /* 640 * USB 641 */ 642 #define CONFIG_HAS_FSL_DR_USB 643 644 #ifdef CONFIG_HAS_FSL_DR_USB 645 #define CONFIG_USB_EHCI 646 647 #ifdef CONFIG_USB_EHCI 648 #define CONFIG_USB_EHCI_FSL 649 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 650 #endif 651 #endif 652 653 #ifdef CONFIG_MMC 654 #define CONFIG_FSL_ESDHC 655 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 656 #define CONFIG_GENERIC_MMC 657 #define CONFIG_DOS_PARTITION 658 #endif 659 660 /* Qman/Bman */ 661 #ifndef CONFIG_NOBQFMAN 662 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 663 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 664 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 665 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 666 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 667 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 668 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 669 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 670 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 671 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 672 CONFIG_SYS_BMAN_CENA_SIZE) 673 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 674 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 675 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 676 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 677 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 678 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 679 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 680 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 681 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 682 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 683 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 684 CONFIG_SYS_QMAN_CENA_SIZE) 685 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 686 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 687 688 #define CONFIG_SYS_DPAA_FMAN 689 #define CONFIG_SYS_DPAA_PME 690 691 #define CONFIG_QE 692 #define CONFIG_U_QE 693 694 /* Default address of microcode for the Linux Fman driver */ 695 #if defined(CONFIG_SPIFLASH) 696 /* 697 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 698 * env, so we got 0x110000. 699 */ 700 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 701 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 702 #elif defined(CONFIG_SDCARD) 703 /* 704 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 705 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 706 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 707 */ 708 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 709 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 710 #elif defined(CONFIG_NAND) 711 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 712 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 713 #else 714 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 715 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 716 #endif 717 718 #if defined(CONFIG_SPIFLASH) 719 #define CONFIG_SYS_QE_FW_ADDR 0x130000 720 #elif defined(CONFIG_SDCARD) 721 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 722 #elif defined(CONFIG_NAND) 723 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 724 #else 725 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 726 #endif 727 728 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 729 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 730 #endif /* CONFIG_NOBQFMAN */ 731 732 #ifdef CONFIG_SYS_DPAA_FMAN 733 #define CONFIG_FMAN_ENET 734 #define CONFIG_PHY_VITESSE 735 #define CONFIG_PHY_REALTEK 736 #endif 737 738 #ifdef CONFIG_FMAN_ENET 739 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) 740 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 741 #elif defined(CONFIG_TARGET_T1040D4RDB) 742 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 743 #elif defined(CONFIG_TARGET_T1042D4RDB) 744 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 745 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 746 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 747 #endif 748 749 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 750 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 751 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 752 #else 753 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 754 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 755 #endif 756 757 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 758 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) 759 #define CONFIG_VSC9953 760 #define CONFIG_CMD_ETHSW 761 #ifdef CONFIG_TARGET_T1040RDB 762 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 763 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 764 #else 765 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 766 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 767 #endif 768 #endif 769 770 #define CONFIG_MII /* MII PHY management */ 771 #define CONFIG_ETHPRIME "FM1@DTSEC4" 772 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 773 #endif 774 775 /* 776 * Environment 777 */ 778 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 779 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 780 781 /* 782 * Command line configuration. 783 */ 784 #ifdef CONFIG_TARGET_T1042RDB_PI 785 #define CONFIG_CMD_DATE 786 #endif 787 #define CONFIG_CMD_ERRATA 788 #define CONFIG_CMD_IRQ 789 #define CONFIG_CMD_REGINFO 790 791 #ifdef CONFIG_PCI 792 #define CONFIG_CMD_PCI 793 #endif 794 795 /* Hash command with SHA acceleration supported in hardware */ 796 #ifdef CONFIG_FSL_CAAM 797 #define CONFIG_CMD_HASH 798 #define CONFIG_SHA_HW_ACCEL 799 #endif 800 801 /* 802 * Miscellaneous configurable options 803 */ 804 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 805 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 806 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 807 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 808 #ifdef CONFIG_CMD_KGDB 809 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 810 #else 811 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 812 #endif 813 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 814 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 815 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 816 817 /* 818 * For booting Linux, the board info and command line data 819 * have to be in the first 64 MB of memory, since this is 820 * the maximum mapped by the Linux kernel during initialization. 821 */ 822 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 823 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 824 825 #ifdef CONFIG_CMD_KGDB 826 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 827 #endif 828 829 /* 830 * Dynamic MTD Partition support with mtdparts 831 */ 832 #ifndef CONFIG_SYS_NO_FLASH 833 #define CONFIG_MTD_DEVICE 834 #define CONFIG_MTD_PARTITIONS 835 #define CONFIG_CMD_MTDPARTS 836 #define CONFIG_FLASH_CFI_MTD 837 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 838 "spi0=spife110000.0" 839 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 840 "128k(dtb),96m(fs),-(user);"\ 841 "fff800000.flash:2m(uboot),9m(kernel),"\ 842 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 843 "2m(uboot),9m(kernel),128k(dtb),-(user)" 844 #endif 845 846 /* 847 * Environment Configuration 848 */ 849 #define CONFIG_ROOTPATH "/opt/nfsroot" 850 #define CONFIG_BOOTFILE "uImage" 851 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 852 853 /* default location for tftp and bootm */ 854 #define CONFIG_LOADADDR 1000000 855 856 857 #define CONFIG_BAUDRATE 115200 858 859 #define __USB_PHY_TYPE utmi 860 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 861 862 #ifdef CONFIG_TARGET_T1040RDB 863 #define FDTFILE "t1040rdb/t1040rdb.dtb" 864 #elif defined(CONFIG_TARGET_T1042RDB_PI) 865 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 866 #elif defined(CONFIG_TARGET_T1042RDB) 867 #define FDTFILE "t1042rdb/t1042rdb.dtb" 868 #elif defined(CONFIG_TARGET_T1040D4RDB) 869 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 870 #elif defined(CONFIG_TARGET_T1042D4RDB) 871 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 872 #endif 873 874 #ifdef CONFIG_FSL_DIU_FB 875 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 876 #else 877 #define DIU_ENVIRONMENT 878 #endif 879 880 #define CONFIG_EXTRA_ENV_SETTINGS \ 881 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 882 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 883 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 884 "netdev=eth0\0" \ 885 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 886 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 887 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 888 "tftpflash=tftpboot $loadaddr $uboot && " \ 889 "protect off $ubootaddr +$filesize && " \ 890 "erase $ubootaddr +$filesize && " \ 891 "cp.b $loadaddr $ubootaddr $filesize && " \ 892 "protect on $ubootaddr +$filesize && " \ 893 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 894 "consoledev=ttyS0\0" \ 895 "ramdiskaddr=2000000\0" \ 896 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 897 "fdtaddr=1e00000\0" \ 898 "fdtfile=" __stringify(FDTFILE) "\0" \ 899 "bdev=sda3\0" 900 901 #define CONFIG_LINUX \ 902 "setenv bootargs root=/dev/ram rw " \ 903 "console=$consoledev,$baudrate $othbootargs;" \ 904 "setenv ramdiskaddr 0x02000000;" \ 905 "setenv fdtaddr 0x00c00000;" \ 906 "setenv loadaddr 0x1000000;" \ 907 "bootm $loadaddr $ramdiskaddr $fdtaddr" 908 909 #define CONFIG_HDBOOT \ 910 "setenv bootargs root=/dev/$bdev rw " \ 911 "console=$consoledev,$baudrate $othbootargs;" \ 912 "tftp $loadaddr $bootfile;" \ 913 "tftp $fdtaddr $fdtfile;" \ 914 "bootm $loadaddr - $fdtaddr" 915 916 #define CONFIG_NFSBOOTCOMMAND \ 917 "setenv bootargs root=/dev/nfs rw " \ 918 "nfsroot=$serverip:$rootpath " \ 919 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 920 "console=$consoledev,$baudrate $othbootargs;" \ 921 "tftp $loadaddr $bootfile;" \ 922 "tftp $fdtaddr $fdtfile;" \ 923 "bootm $loadaddr - $fdtaddr" 924 925 #define CONFIG_RAMBOOTCOMMAND \ 926 "setenv bootargs root=/dev/ram rw " \ 927 "console=$consoledev,$baudrate $othbootargs;" \ 928 "tftp $ramdiskaddr $ramdiskfile;" \ 929 "tftp $loadaddr $bootfile;" \ 930 "tftp $fdtaddr $fdtfile;" \ 931 "bootm $loadaddr $ramdiskaddr $fdtaddr" 932 933 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 934 935 #include <asm/fsl_secure_boot.h> 936 937 #endif /* __CONFIG_H */ 938