1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_E500 /* BOOKE e500 family */ 17 #include <asm/config_mpc85xx.h> 18 19 #ifdef CONFIG_RAMBOOT_PBL 20 21 #ifndef CONFIG_SECURE_BOOT 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 23 #else 24 #define CONFIG_SYS_FSL_PBL_PBI \ 25 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 26 #endif 27 28 #ifdef CONFIG_T1040RDB 29 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg 30 #endif 31 #ifdef CONFIG_T1042RDB_PI 32 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg 33 #endif 34 #ifdef CONFIG_T1042RDB 35 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg 36 #endif 37 #ifdef CONFIG_T1040D4RDB 38 #define CONFIG_SYS_FSL_PBL_RCW \ 39 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg 40 #endif 41 #ifdef CONFIG_T1042D4RDB 42 #define CONFIG_SYS_FSL_PBL_RCW \ 43 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg 44 #endif 45 46 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 47 #define CONFIG_SPL_ENV_SUPPORT 48 #define CONFIG_SPL_SERIAL_SUPPORT 49 #define CONFIG_SPL_FLUSH_IMAGE 50 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 51 #define CONFIG_SPL_LIBGENERIC_SUPPORT 52 #define CONFIG_SPL_LIBCOMMON_SUPPORT 53 #define CONFIG_SPL_I2C_SUPPORT 54 #define CONFIG_FSL_LAW /* Use common FSL init code */ 55 #define CONFIG_SYS_TEXT_BASE 0x30001000 56 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 57 #define CONFIG_SPL_PAD_TO 0x40000 58 #define CONFIG_SPL_MAX_SIZE 0x28000 59 #ifdef CONFIG_SPL_BUILD 60 #define CONFIG_SPL_SKIP_RELOCATE 61 #define CONFIG_SPL_COMMON_INIT_DDR 62 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 63 #define CONFIG_SYS_NO_FLASH 64 #endif 65 #define RESET_VECTOR_OFFSET 0x27FFC 66 #define BOOT_PAGE_OFFSET 0x27000 67 68 #ifdef CONFIG_NAND 69 #define CONFIG_SPL_NAND_SUPPORT 70 #ifdef CONFIG_SECURE_BOOT 71 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 72 /* 73 * HDR would be appended at end of image and copied to DDR along 74 * with U-Boot image. 75 */ 76 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 77 CONFIG_U_BOOT_HDR_SIZE) 78 #else 79 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 80 #endif 81 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 82 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 83 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 84 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 85 #define CONFIG_SPL_NAND_BOOT 86 #endif 87 88 #ifdef CONFIG_SPIFLASH 89 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 90 #define CONFIG_SPL_SPI_SUPPORT 91 #define CONFIG_SPL_SPI_FLASH_SUPPORT 92 #define CONFIG_SPL_SPI_FLASH_MINIMAL 93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 94 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 95 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 96 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 97 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 98 #ifndef CONFIG_SPL_BUILD 99 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 100 #endif 101 #define CONFIG_SPL_SPI_BOOT 102 #endif 103 104 #ifdef CONFIG_SDCARD 105 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 106 #define CONFIG_SPL_MMC_SUPPORT 107 #define CONFIG_SPL_MMC_MINIMAL 108 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 109 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 110 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 111 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 112 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 113 #ifndef CONFIG_SPL_BUILD 114 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 115 #endif 116 #define CONFIG_SPL_MMC_BOOT 117 #endif 118 119 #endif 120 121 /* High Level Configuration Options */ 122 #define CONFIG_BOOKE 123 #define CONFIG_E500MC /* BOOKE e500mc family */ 124 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 125 #define CONFIG_MP /* support multiple processors */ 126 127 /* support deep sleep */ 128 #define CONFIG_DEEP_SLEEP 129 #if defined(CONFIG_DEEP_SLEEP) 130 #define CONFIG_BOARD_EARLY_INIT_F 131 #define CONFIG_SILENT_CONSOLE 132 #endif 133 134 #ifndef CONFIG_SYS_TEXT_BASE 135 #define CONFIG_SYS_TEXT_BASE 0xeff40000 136 #endif 137 138 #ifndef CONFIG_RESET_VECTOR_ADDRESS 139 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 140 #endif 141 142 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 143 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 144 #define CONFIG_FSL_IFC /* Enable IFC Support */ 145 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 146 #define CONFIG_PCI /* Enable PCI/PCIE */ 147 #define CONFIG_PCI_INDIRECT_BRIDGE 148 #define CONFIG_PCIE1 /* PCIE controller 1 */ 149 #define CONFIG_PCIE2 /* PCIE controller 2 */ 150 #define CONFIG_PCIE3 /* PCIE controller 3 */ 151 #define CONFIG_PCIE4 /* PCIE controller 4 */ 152 153 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 154 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 155 156 #define CONFIG_FSL_LAW /* Use common FSL init code */ 157 158 #define CONFIG_ENV_OVERWRITE 159 160 #ifndef CONFIG_SYS_NO_FLASH 161 #define CONFIG_FLASH_CFI_DRIVER 162 #define CONFIG_SYS_FLASH_CFI 163 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 164 #endif 165 166 #if defined(CONFIG_SPIFLASH) 167 #define CONFIG_SYS_EXTRA_ENV_RELOC 168 #define CONFIG_ENV_IS_IN_SPI_FLASH 169 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 170 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 171 #define CONFIG_ENV_SECT_SIZE 0x10000 172 #elif defined(CONFIG_SDCARD) 173 #define CONFIG_SYS_EXTRA_ENV_RELOC 174 #define CONFIG_ENV_IS_IN_MMC 175 #define CONFIG_SYS_MMC_ENV_DEV 0 176 #define CONFIG_ENV_SIZE 0x2000 177 #define CONFIG_ENV_OFFSET (512 * 0x800) 178 #elif defined(CONFIG_NAND) 179 #ifdef CONFIG_SECURE_BOOT 180 #define CONFIG_RAMBOOT_NAND 181 #define CONFIG_BOOTSCRIPT_COPY_RAM 182 #endif 183 #define CONFIG_SYS_EXTRA_ENV_RELOC 184 #define CONFIG_ENV_IS_IN_NAND 185 #define CONFIG_ENV_SIZE 0x2000 186 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 187 #else 188 #define CONFIG_ENV_IS_IN_FLASH 189 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 190 #define CONFIG_ENV_SIZE 0x2000 191 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 192 #endif 193 194 #define CONFIG_SYS_CLK_FREQ 100000000 195 #define CONFIG_DDR_CLK_FREQ 66666666 196 197 /* 198 * These can be toggled for performance analysis, otherwise use default. 199 */ 200 #define CONFIG_SYS_CACHE_STASHING 201 #define CONFIG_BACKSIDE_L2_CACHE 202 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 203 #define CONFIG_BTB /* toggle branch predition */ 204 #define CONFIG_DDR_ECC 205 #ifdef CONFIG_DDR_ECC 206 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 207 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 208 #endif 209 210 #define CONFIG_ENABLE_36BIT_PHYS 211 212 #define CONFIG_ADDR_MAP 213 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 214 215 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 216 #define CONFIG_SYS_MEMTEST_END 0x00400000 217 #define CONFIG_SYS_ALT_MEMTEST 218 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 219 220 /* 221 * Config the L3 Cache as L3 SRAM 222 */ 223 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 224 /* 225 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 226 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 227 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 228 */ 229 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 230 #define CONFIG_SYS_L3_SIZE 256 << 10 231 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 232 #ifdef CONFIG_RAMBOOT_PBL 233 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 234 #endif 235 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 236 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 237 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 238 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 239 240 #define CONFIG_SYS_DCSRBAR 0xf0000000 241 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 242 243 /* 244 * DDR Setup 245 */ 246 #define CONFIG_VERY_BIG_RAM 247 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 248 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 249 250 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 251 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 252 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 253 254 #define CONFIG_DDR_SPD 255 #ifndef CONFIG_SYS_FSL_DDR4 256 #define CONFIG_SYS_FSL_DDR3 257 #endif 258 259 #define CONFIG_SYS_SPD_BUS_NUM 0 260 #define SPD_EEPROM_ADDRESS 0x51 261 262 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 263 264 /* 265 * IFC Definitions 266 */ 267 #define CONFIG_SYS_FLASH_BASE 0xe8000000 268 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 269 270 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 271 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 272 CSPR_PORT_SIZE_16 | \ 273 CSPR_MSEL_NOR | \ 274 CSPR_V) 275 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 276 277 /* 278 * TDM Definition 279 */ 280 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 281 282 /* NOR Flash Timing Params */ 283 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 284 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 285 FTIM0_NOR_TEADC(0x5) | \ 286 FTIM0_NOR_TEAHC(0x5)) 287 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 288 FTIM1_NOR_TRAD_NOR(0x1A) |\ 289 FTIM1_NOR_TSEQRAD_NOR(0x13)) 290 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 291 FTIM2_NOR_TCH(0x4) | \ 292 FTIM2_NOR_TWPH(0x0E) | \ 293 FTIM2_NOR_TWP(0x1c)) 294 #define CONFIG_SYS_NOR_FTIM3 0x0 295 296 #define CONFIG_SYS_FLASH_QUIET_TEST 297 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 298 299 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 300 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 301 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 302 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 303 304 #define CONFIG_SYS_FLASH_EMPTY_INFO 305 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 306 307 /* CPLD on IFC */ 308 #define CPLD_LBMAP_MASK 0x3F 309 #define CPLD_BANK_SEL_MASK 0x07 310 #define CPLD_BANK_OVERRIDE 0x40 311 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 312 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 313 #define CPLD_LBMAP_RESET 0xFF 314 #define CPLD_LBMAP_SHIFT 0x03 315 316 #if defined(CONFIG_T1042RDB_PI) 317 #define CPLD_DIU_SEL_DFP 0x80 318 #elif defined(CONFIG_T1042D4RDB) 319 #define CPLD_DIU_SEL_DFP 0xc0 320 #endif 321 322 #if defined(CONFIG_T1040D4RDB) 323 #define CPLD_INT_MASK_ALL 0xFF 324 #define CPLD_INT_MASK_THERM 0x80 325 #define CPLD_INT_MASK_DVI_DFP 0x40 326 #define CPLD_INT_MASK_QSGMII1 0x20 327 #define CPLD_INT_MASK_QSGMII2 0x10 328 #define CPLD_INT_MASK_SGMI1 0x08 329 #define CPLD_INT_MASK_SGMI2 0x04 330 #define CPLD_INT_MASK_TDMR1 0x02 331 #define CPLD_INT_MASK_TDMR2 0x01 332 #endif 333 334 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 335 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 336 #define CONFIG_SYS_CSPR2_EXT (0xf) 337 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 338 | CSPR_PORT_SIZE_8 \ 339 | CSPR_MSEL_GPCM \ 340 | CSPR_V) 341 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 342 #define CONFIG_SYS_CSOR2 0x0 343 /* CPLD Timing parameters for IFC CS2 */ 344 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 345 FTIM0_GPCM_TEADC(0x0e) | \ 346 FTIM0_GPCM_TEAHC(0x0e)) 347 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 348 FTIM1_GPCM_TRAD(0x1f)) 349 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 350 FTIM2_GPCM_TCH(0x8) | \ 351 FTIM2_GPCM_TWP(0x1f)) 352 #define CONFIG_SYS_CS2_FTIM3 0x0 353 354 /* NAND Flash on IFC */ 355 #define CONFIG_NAND_FSL_IFC 356 #define CONFIG_SYS_NAND_BASE 0xff800000 357 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 358 359 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 360 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 361 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 362 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 363 | CSPR_V) 364 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 365 366 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 367 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 368 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 369 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 370 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 371 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 372 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 373 374 #define CONFIG_SYS_NAND_ONFI_DETECTION 375 376 /* ONFI NAND Flash mode0 Timing Params */ 377 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 378 FTIM0_NAND_TWP(0x18) | \ 379 FTIM0_NAND_TWCHT(0x07) | \ 380 FTIM0_NAND_TWH(0x0a)) 381 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 382 FTIM1_NAND_TWBE(0x39) | \ 383 FTIM1_NAND_TRR(0x0e) | \ 384 FTIM1_NAND_TRP(0x18)) 385 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 386 FTIM2_NAND_TREH(0x0a) | \ 387 FTIM2_NAND_TWHRE(0x1e)) 388 #define CONFIG_SYS_NAND_FTIM3 0x0 389 390 #define CONFIG_SYS_NAND_DDR_LAW 11 391 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 392 #define CONFIG_SYS_MAX_NAND_DEVICE 1 393 #define CONFIG_CMD_NAND 394 395 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 396 397 #if defined(CONFIG_NAND) 398 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 399 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 400 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 401 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 402 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 403 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 404 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 405 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 406 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 407 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 408 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 409 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 410 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 411 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 412 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 413 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 414 #else 415 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 416 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 417 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 418 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 419 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 420 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 421 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 422 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 423 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 424 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 425 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 426 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 427 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 428 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 429 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 430 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 431 #endif 432 433 #ifdef CONFIG_SPL_BUILD 434 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 435 #else 436 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 437 #endif 438 439 #if defined(CONFIG_RAMBOOT_PBL) 440 #define CONFIG_SYS_RAMBOOT 441 #endif 442 443 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 444 #if defined(CONFIG_NAND) 445 #define CONFIG_A008044_WORKAROUND 446 #endif 447 #endif 448 449 #define CONFIG_BOARD_EARLY_INIT_R 450 #define CONFIG_MISC_INIT_R 451 452 #define CONFIG_HWCONFIG 453 454 /* define to use L1 as initial stack */ 455 #define CONFIG_L1_INIT_RAM 456 #define CONFIG_SYS_INIT_RAM_LOCK 457 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 458 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 459 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 460 /* The assembler doesn't like typecast */ 461 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 462 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 463 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 464 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 465 466 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 467 GENERATED_GBL_DATA_SIZE) 468 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 469 470 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 471 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 472 473 /* Serial Port - controlled on board with jumper J8 474 * open - index 2 475 * shorted - index 1 476 */ 477 #define CONFIG_CONS_INDEX 1 478 #define CONFIG_SYS_NS16550_SERIAL 479 #define CONFIG_SYS_NS16550_REG_SIZE 1 480 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 481 482 #define CONFIG_SYS_BAUDRATE_TABLE \ 483 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 484 485 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 486 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 487 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 488 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 489 #ifndef CONFIG_SPL_BUILD 490 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 491 #endif 492 493 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB) 494 /* Video */ 495 #define CONFIG_FSL_DIU_FB 496 497 #ifdef CONFIG_FSL_DIU_FB 498 #define CONFIG_FSL_DIU_CH7301 499 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 500 #define CONFIG_VIDEO 501 #define CONFIG_CMD_BMP 502 #define CONFIG_CFB_CONSOLE 503 #define CONFIG_CFB_CONSOLE_ANSI 504 #define CONFIG_VIDEO_SW_CURSOR 505 #define CONFIG_VGA_AS_SINGLE_DEVICE 506 #define CONFIG_VIDEO_LOGO 507 #define CONFIG_VIDEO_BMP_LOGO 508 #endif 509 #endif 510 511 /* I2C */ 512 #define CONFIG_SYS_I2C 513 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 514 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 515 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 516 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 517 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 518 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 519 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 520 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 521 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 522 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 523 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 524 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 525 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 526 527 /* I2C bus multiplexer */ 528 #define I2C_MUX_PCA_ADDR 0x70 529 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 530 #define I2C_MUX_CH_DEFAULT 0x8 531 #endif 532 533 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) 534 /* LDI/DVI Encoder for display */ 535 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 536 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 537 538 /* 539 * RTC configuration 540 */ 541 #define RTC 542 #define CONFIG_RTC_DS1337 1 543 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 544 545 /*DVI encoder*/ 546 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 547 #endif 548 549 /* 550 * eSPI - Enhanced SPI 551 */ 552 #define CONFIG_SPI_FLASH_BAR 553 #define CONFIG_SF_DEFAULT_SPEED 10000000 554 #define CONFIG_SF_DEFAULT_MODE 0 555 #define CONFIG_ENV_SPI_BUS 0 556 #define CONFIG_ENV_SPI_CS 0 557 #define CONFIG_ENV_SPI_MAX_HZ 10000000 558 #define CONFIG_ENV_SPI_MODE 0 559 560 /* 561 * General PCI 562 * Memory space is mapped 1-1, but I/O space must start from 0. 563 */ 564 565 #ifdef CONFIG_PCI 566 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 567 #ifdef CONFIG_PCIE1 568 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 569 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 570 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 571 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 572 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 573 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 574 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 575 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 576 #endif 577 578 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 579 #ifdef CONFIG_PCIE2 580 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 581 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 582 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 583 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 584 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 585 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 586 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 587 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 588 #endif 589 590 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 591 #ifdef CONFIG_PCIE3 592 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 593 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 594 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 595 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 596 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 597 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 598 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 599 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 600 #endif 601 602 /* controller 4, Base address 203000 */ 603 #ifdef CONFIG_PCIE4 604 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 605 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 606 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 607 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 608 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 609 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 610 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 611 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 612 #endif 613 614 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 615 616 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 617 #define CONFIG_DOS_PARTITION 618 #endif /* CONFIG_PCI */ 619 620 /* SATA */ 621 #define CONFIG_FSL_SATA_V2 622 #ifdef CONFIG_FSL_SATA_V2 623 #define CONFIG_LIBATA 624 #define CONFIG_FSL_SATA 625 626 #define CONFIG_SYS_SATA_MAX_DEVICE 1 627 #define CONFIG_SATA1 628 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 629 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 630 631 #define CONFIG_LBA48 632 #define CONFIG_CMD_SATA 633 #define CONFIG_DOS_PARTITION 634 #endif 635 636 /* 637 * USB 638 */ 639 #define CONFIG_HAS_FSL_DR_USB 640 641 #ifdef CONFIG_HAS_FSL_DR_USB 642 #define CONFIG_USB_EHCI 643 644 #ifdef CONFIG_USB_EHCI 645 #define CONFIG_USB_EHCI_FSL 646 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 647 #endif 648 #endif 649 650 #define CONFIG_MMC 651 652 #ifdef CONFIG_MMC 653 #define CONFIG_FSL_ESDHC 654 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 655 #define CONFIG_GENERIC_MMC 656 #define CONFIG_DOS_PARTITION 657 #endif 658 659 /* Qman/Bman */ 660 #ifndef CONFIG_NOBQFMAN 661 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 662 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 663 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 664 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 665 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 666 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 667 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 668 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 669 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 670 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 671 CONFIG_SYS_BMAN_CENA_SIZE) 672 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 673 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 674 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 675 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 676 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 677 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 678 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 679 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 680 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 681 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 682 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 683 CONFIG_SYS_QMAN_CENA_SIZE) 684 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 685 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 686 687 #define CONFIG_SYS_DPAA_FMAN 688 #define CONFIG_SYS_DPAA_PME 689 690 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 691 #define CONFIG_QE 692 #define CONFIG_U_QE 693 #endif 694 695 /* Default address of microcode for the Linux Fman driver */ 696 #if defined(CONFIG_SPIFLASH) 697 /* 698 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 699 * env, so we got 0x110000. 700 */ 701 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 702 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 703 #elif defined(CONFIG_SDCARD) 704 /* 705 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 706 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 707 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 708 */ 709 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 710 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 711 #elif defined(CONFIG_NAND) 712 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 713 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 714 #else 715 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 716 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 717 #endif 718 719 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 720 #if defined(CONFIG_SPIFLASH) 721 #define CONFIG_SYS_QE_FW_ADDR 0x130000 722 #elif defined(CONFIG_SDCARD) 723 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 724 #elif defined(CONFIG_NAND) 725 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 726 #else 727 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 728 #endif 729 #endif 730 731 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 732 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 733 #endif /* CONFIG_NOBQFMAN */ 734 735 #ifdef CONFIG_SYS_DPAA_FMAN 736 #define CONFIG_FMAN_ENET 737 #define CONFIG_PHY_VITESSE 738 #define CONFIG_PHY_REALTEK 739 #endif 740 741 #ifdef CONFIG_FMAN_ENET 742 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 743 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 744 #elif defined(CONFIG_T1040D4RDB) 745 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 746 #elif defined(CONFIG_T1042D4RDB) 747 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 748 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 749 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 750 #endif 751 752 #ifdef CONFIG_T104XD4RDB 753 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 754 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 755 #else 756 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 757 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 758 #endif 759 760 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 761 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) 762 #define CONFIG_VSC9953 763 #define CONFIG_CMD_ETHSW 764 #ifdef CONFIG_T1040RDB 765 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 766 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 767 #else 768 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 769 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 770 #endif 771 #endif 772 773 #define CONFIG_MII /* MII PHY management */ 774 #define CONFIG_ETHPRIME "FM1@DTSEC4" 775 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 776 #endif 777 778 /* 779 * Environment 780 */ 781 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 782 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 783 784 /* 785 * Command line configuration. 786 */ 787 #ifdef CONFIG_T1042RDB_PI 788 #define CONFIG_CMD_DATE 789 #endif 790 #define CONFIG_CMD_ERRATA 791 #define CONFIG_CMD_IRQ 792 #define CONFIG_CMD_REGINFO 793 794 #ifdef CONFIG_PCI 795 #define CONFIG_CMD_PCI 796 #endif 797 798 /* Hash command with SHA acceleration supported in hardware */ 799 #ifdef CONFIG_FSL_CAAM 800 #define CONFIG_CMD_HASH 801 #define CONFIG_SHA_HW_ACCEL 802 #endif 803 804 /* 805 * Miscellaneous configurable options 806 */ 807 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 808 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 809 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 810 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 811 #ifdef CONFIG_CMD_KGDB 812 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 813 #else 814 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 815 #endif 816 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 817 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 818 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 819 820 /* 821 * For booting Linux, the board info and command line data 822 * have to be in the first 64 MB of memory, since this is 823 * the maximum mapped by the Linux kernel during initialization. 824 */ 825 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 826 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 827 828 #ifdef CONFIG_CMD_KGDB 829 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 830 #endif 831 832 /* 833 * Dynamic MTD Partition support with mtdparts 834 */ 835 #ifndef CONFIG_SYS_NO_FLASH 836 #define CONFIG_MTD_DEVICE 837 #define CONFIG_MTD_PARTITIONS 838 #define CONFIG_CMD_MTDPARTS 839 #define CONFIG_FLASH_CFI_MTD 840 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 841 "spi0=spife110000.0" 842 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 843 "128k(dtb),96m(fs),-(user);"\ 844 "fff800000.flash:2m(uboot),9m(kernel),"\ 845 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 846 "2m(uboot),9m(kernel),128k(dtb),-(user)" 847 #endif 848 849 /* 850 * Environment Configuration 851 */ 852 #define CONFIG_ROOTPATH "/opt/nfsroot" 853 #define CONFIG_BOOTFILE "uImage" 854 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 855 856 /* default location for tftp and bootm */ 857 #define CONFIG_LOADADDR 1000000 858 859 860 #define CONFIG_BAUDRATE 115200 861 862 #define __USB_PHY_TYPE utmi 863 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 864 865 #ifdef CONFIG_T1040RDB 866 #define FDTFILE "t1040rdb/t1040rdb.dtb" 867 #elif defined(CONFIG_T1042RDB_PI) 868 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 869 #elif defined(CONFIG_T1042RDB) 870 #define FDTFILE "t1042rdb/t1042rdb.dtb" 871 #elif defined(CONFIG_T1040D4RDB) 872 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 873 #elif defined(CONFIG_T1042D4RDB) 874 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 875 #endif 876 877 #ifdef CONFIG_FSL_DIU_FB 878 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 879 #else 880 #define DIU_ENVIRONMENT 881 #endif 882 883 #define CONFIG_EXTRA_ENV_SETTINGS \ 884 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 885 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 886 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 887 "netdev=eth0\0" \ 888 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 889 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 890 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 891 "tftpflash=tftpboot $loadaddr $uboot && " \ 892 "protect off $ubootaddr +$filesize && " \ 893 "erase $ubootaddr +$filesize && " \ 894 "cp.b $loadaddr $ubootaddr $filesize && " \ 895 "protect on $ubootaddr +$filesize && " \ 896 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 897 "consoledev=ttyS0\0" \ 898 "ramdiskaddr=2000000\0" \ 899 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 900 "fdtaddr=1e00000\0" \ 901 "fdtfile=" __stringify(FDTFILE) "\0" \ 902 "bdev=sda3\0" 903 904 #define CONFIG_LINUX \ 905 "setenv bootargs root=/dev/ram rw " \ 906 "console=$consoledev,$baudrate $othbootargs;" \ 907 "setenv ramdiskaddr 0x02000000;" \ 908 "setenv fdtaddr 0x00c00000;" \ 909 "setenv loadaddr 0x1000000;" \ 910 "bootm $loadaddr $ramdiskaddr $fdtaddr" 911 912 #define CONFIG_HDBOOT \ 913 "setenv bootargs root=/dev/$bdev rw " \ 914 "console=$consoledev,$baudrate $othbootargs;" \ 915 "tftp $loadaddr $bootfile;" \ 916 "tftp $fdtaddr $fdtfile;" \ 917 "bootm $loadaddr - $fdtaddr" 918 919 #define CONFIG_NFSBOOTCOMMAND \ 920 "setenv bootargs root=/dev/nfs rw " \ 921 "nfsroot=$serverip:$rootpath " \ 922 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 923 "console=$consoledev,$baudrate $othbootargs;" \ 924 "tftp $loadaddr $bootfile;" \ 925 "tftp $fdtaddr $fdtfile;" \ 926 "bootm $loadaddr - $fdtaddr" 927 928 #define CONFIG_RAMBOOTCOMMAND \ 929 "setenv bootargs root=/dev/ram rw " \ 930 "console=$consoledev,$baudrate $othbootargs;" \ 931 "tftp $ramdiskaddr $ramdiskfile;" \ 932 "tftp $loadaddr $bootfile;" \ 933 "tftp $fdtaddr $fdtfile;" \ 934 "bootm $loadaddr $ramdiskaddr $fdtaddr" 935 936 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 937 938 #include <asm/fsl_secure_boot.h> 939 940 #endif /* __CONFIG_H */ 941