1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 15 #define CONFIG_E500 /* BOOKE e500 family */ 16 #include <asm/config_mpc85xx.h> 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 20 #ifndef CONFIG_SECURE_BOOT 21 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 22 #else 23 #define CONFIG_SYS_FSL_PBL_PBI \ 24 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 25 #endif 26 27 #define CONFIG_SPL_FLUSH_IMAGE 28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 29 #define CONFIG_FSL_LAW /* Use common FSL init code */ 30 #define CONFIG_SYS_TEXT_BASE 0x30001000 31 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 32 #define CONFIG_SPL_PAD_TO 0x40000 33 #define CONFIG_SPL_MAX_SIZE 0x28000 34 #ifdef CONFIG_SPL_BUILD 35 #define CONFIG_SPL_SKIP_RELOCATE 36 #define CONFIG_SPL_COMMON_INIT_DDR 37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 38 #define CONFIG_SYS_NO_FLASH 39 #endif 40 #define RESET_VECTOR_OFFSET 0x27FFC 41 #define BOOT_PAGE_OFFSET 0x27000 42 43 #ifdef CONFIG_NAND 44 #ifdef CONFIG_SECURE_BOOT 45 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 46 /* 47 * HDR would be appended at end of image and copied to DDR along 48 * with U-Boot image. 49 */ 50 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 51 CONFIG_U_BOOT_HDR_SIZE) 52 #else 53 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 54 #endif 55 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 56 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 57 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 58 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 59 #ifdef CONFIG_T1040RDB 60 #define CONFIG_SYS_FSL_PBL_RCW \ 61 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 62 #endif 63 #ifdef CONFIG_T1042RDB_PI 64 #define CONFIG_SYS_FSL_PBL_RCW \ 65 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 66 #endif 67 #ifdef CONFIG_T1042RDB 68 #define CONFIG_SYS_FSL_PBL_RCW \ 69 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 70 #endif 71 #ifdef CONFIG_T1040D4RDB 72 #define CONFIG_SYS_FSL_PBL_RCW \ 73 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 74 #endif 75 #ifdef CONFIG_T1042D4RDB 76 #define CONFIG_SYS_FSL_PBL_RCW \ 77 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 78 #endif 79 #define CONFIG_SPL_NAND_BOOT 80 #endif 81 82 #ifdef CONFIG_SPIFLASH 83 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 84 #define CONFIG_SPL_SPI_FLASH_MINIMAL 85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 89 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 90 #ifndef CONFIG_SPL_BUILD 91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 92 #endif 93 #ifdef CONFIG_T1040RDB 94 #define CONFIG_SYS_FSL_PBL_RCW \ 95 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 96 #endif 97 #ifdef CONFIG_T1042RDB_PI 98 #define CONFIG_SYS_FSL_PBL_RCW \ 99 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 100 #endif 101 #ifdef CONFIG_T1042RDB 102 #define CONFIG_SYS_FSL_PBL_RCW \ 103 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 104 #endif 105 #ifdef CONFIG_T1040D4RDB 106 #define CONFIG_SYS_FSL_PBL_RCW \ 107 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 108 #endif 109 #ifdef CONFIG_T1042D4RDB 110 #define CONFIG_SYS_FSL_PBL_RCW \ 111 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 112 #endif 113 #define CONFIG_SPL_SPI_BOOT 114 #endif 115 116 #ifdef CONFIG_SDCARD 117 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 118 #define CONFIG_SPL_MMC_MINIMAL 119 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 120 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 121 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 122 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 123 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 124 #ifndef CONFIG_SPL_BUILD 125 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 126 #endif 127 #ifdef CONFIG_T1040RDB 128 #define CONFIG_SYS_FSL_PBL_RCW \ 129 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 130 #endif 131 #ifdef CONFIG_T1042RDB_PI 132 #define CONFIG_SYS_FSL_PBL_RCW \ 133 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 134 #endif 135 #ifdef CONFIG_T1042RDB 136 #define CONFIG_SYS_FSL_PBL_RCW \ 137 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 138 #endif 139 #ifdef CONFIG_T1040D4RDB 140 #define CONFIG_SYS_FSL_PBL_RCW \ 141 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 142 #endif 143 #ifdef CONFIG_T1042D4RDB 144 #define CONFIG_SYS_FSL_PBL_RCW \ 145 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 146 #endif 147 #define CONFIG_SPL_MMC_BOOT 148 #endif 149 150 #endif 151 152 /* High Level Configuration Options */ 153 #define CONFIG_BOOKE 154 #define CONFIG_E500MC /* BOOKE e500mc family */ 155 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 156 #define CONFIG_MP /* support multiple processors */ 157 158 /* support deep sleep */ 159 #define CONFIG_DEEP_SLEEP 160 #if defined(CONFIG_DEEP_SLEEP) 161 #define CONFIG_BOARD_EARLY_INIT_F 162 #endif 163 164 #ifndef CONFIG_SYS_TEXT_BASE 165 #define CONFIG_SYS_TEXT_BASE 0xeff40000 166 #endif 167 168 #ifndef CONFIG_RESET_VECTOR_ADDRESS 169 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 170 #endif 171 172 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 173 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 174 #define CONFIG_FSL_IFC /* Enable IFC Support */ 175 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 176 #define CONFIG_PCI_INDIRECT_BRIDGE 177 #define CONFIG_PCIE1 /* PCIE controller 1 */ 178 #define CONFIG_PCIE2 /* PCIE controller 2 */ 179 #define CONFIG_PCIE3 /* PCIE controller 3 */ 180 #define CONFIG_PCIE4 /* PCIE controller 4 */ 181 182 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 183 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 184 185 #define CONFIG_FSL_LAW /* Use common FSL init code */ 186 187 #define CONFIG_ENV_OVERWRITE 188 189 #ifndef CONFIG_SYS_NO_FLASH 190 #define CONFIG_FLASH_CFI_DRIVER 191 #define CONFIG_SYS_FLASH_CFI 192 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 193 #endif 194 195 #if defined(CONFIG_SPIFLASH) 196 #define CONFIG_SYS_EXTRA_ENV_RELOC 197 #define CONFIG_ENV_IS_IN_SPI_FLASH 198 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 199 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 200 #define CONFIG_ENV_SECT_SIZE 0x10000 201 #elif defined(CONFIG_SDCARD) 202 #define CONFIG_SYS_EXTRA_ENV_RELOC 203 #define CONFIG_ENV_IS_IN_MMC 204 #define CONFIG_SYS_MMC_ENV_DEV 0 205 #define CONFIG_ENV_SIZE 0x2000 206 #define CONFIG_ENV_OFFSET (512 * 0x800) 207 #elif defined(CONFIG_NAND) 208 #ifdef CONFIG_SECURE_BOOT 209 #define CONFIG_RAMBOOT_NAND 210 #define CONFIG_BOOTSCRIPT_COPY_RAM 211 #endif 212 #define CONFIG_SYS_EXTRA_ENV_RELOC 213 #define CONFIG_ENV_IS_IN_NAND 214 #define CONFIG_ENV_SIZE 0x2000 215 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 216 #else 217 #define CONFIG_ENV_IS_IN_FLASH 218 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 219 #define CONFIG_ENV_SIZE 0x2000 220 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 221 #endif 222 223 #define CONFIG_SYS_CLK_FREQ 100000000 224 #define CONFIG_DDR_CLK_FREQ 66666666 225 226 /* 227 * These can be toggled for performance analysis, otherwise use default. 228 */ 229 #define CONFIG_SYS_CACHE_STASHING 230 #define CONFIG_BACKSIDE_L2_CACHE 231 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 232 #define CONFIG_BTB /* toggle branch predition */ 233 #define CONFIG_DDR_ECC 234 #ifdef CONFIG_DDR_ECC 235 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 236 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 237 #endif 238 239 #define CONFIG_ENABLE_36BIT_PHYS 240 241 #define CONFIG_ADDR_MAP 242 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 243 244 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 245 #define CONFIG_SYS_MEMTEST_END 0x00400000 246 #define CONFIG_SYS_ALT_MEMTEST 247 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 248 249 /* 250 * Config the L3 Cache as L3 SRAM 251 */ 252 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 253 /* 254 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 255 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 256 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 257 */ 258 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 259 #define CONFIG_SYS_L3_SIZE 256 << 10 260 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 261 #ifdef CONFIG_RAMBOOT_PBL 262 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 263 #endif 264 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 265 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 266 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 267 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 268 269 #define CONFIG_SYS_DCSRBAR 0xf0000000 270 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 271 272 /* 273 * DDR Setup 274 */ 275 #define CONFIG_VERY_BIG_RAM 276 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 277 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 278 279 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 280 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 281 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 282 283 #define CONFIG_DDR_SPD 284 #ifndef CONFIG_SYS_FSL_DDR4 285 #define CONFIG_SYS_FSL_DDR3 286 #endif 287 288 #define CONFIG_SYS_SPD_BUS_NUM 0 289 #define SPD_EEPROM_ADDRESS 0x51 290 291 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 292 293 /* 294 * IFC Definitions 295 */ 296 #define CONFIG_SYS_FLASH_BASE 0xe8000000 297 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 298 299 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 300 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 301 CSPR_PORT_SIZE_16 | \ 302 CSPR_MSEL_NOR | \ 303 CSPR_V) 304 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 305 306 /* 307 * TDM Definition 308 */ 309 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 310 311 /* NOR Flash Timing Params */ 312 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 313 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 314 FTIM0_NOR_TEADC(0x5) | \ 315 FTIM0_NOR_TEAHC(0x5)) 316 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 317 FTIM1_NOR_TRAD_NOR(0x1A) |\ 318 FTIM1_NOR_TSEQRAD_NOR(0x13)) 319 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 320 FTIM2_NOR_TCH(0x4) | \ 321 FTIM2_NOR_TWPH(0x0E) | \ 322 FTIM2_NOR_TWP(0x1c)) 323 #define CONFIG_SYS_NOR_FTIM3 0x0 324 325 #define CONFIG_SYS_FLASH_QUIET_TEST 326 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 327 328 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 329 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 330 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 331 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 332 333 #define CONFIG_SYS_FLASH_EMPTY_INFO 334 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 335 336 /* CPLD on IFC */ 337 #define CPLD_LBMAP_MASK 0x3F 338 #define CPLD_BANK_SEL_MASK 0x07 339 #define CPLD_BANK_OVERRIDE 0x40 340 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 341 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 342 #define CPLD_LBMAP_RESET 0xFF 343 #define CPLD_LBMAP_SHIFT 0x03 344 345 #if defined(CONFIG_T1042RDB_PI) 346 #define CPLD_DIU_SEL_DFP 0x80 347 #elif defined(CONFIG_T1042D4RDB) 348 #define CPLD_DIU_SEL_DFP 0xc0 349 #endif 350 351 #if defined(CONFIG_T1040D4RDB) 352 #define CPLD_INT_MASK_ALL 0xFF 353 #define CPLD_INT_MASK_THERM 0x80 354 #define CPLD_INT_MASK_DVI_DFP 0x40 355 #define CPLD_INT_MASK_QSGMII1 0x20 356 #define CPLD_INT_MASK_QSGMII2 0x10 357 #define CPLD_INT_MASK_SGMI1 0x08 358 #define CPLD_INT_MASK_SGMI2 0x04 359 #define CPLD_INT_MASK_TDMR1 0x02 360 #define CPLD_INT_MASK_TDMR2 0x01 361 #endif 362 363 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 364 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 365 #define CONFIG_SYS_CSPR2_EXT (0xf) 366 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 367 | CSPR_PORT_SIZE_8 \ 368 | CSPR_MSEL_GPCM \ 369 | CSPR_V) 370 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 371 #define CONFIG_SYS_CSOR2 0x0 372 /* CPLD Timing parameters for IFC CS2 */ 373 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 374 FTIM0_GPCM_TEADC(0x0e) | \ 375 FTIM0_GPCM_TEAHC(0x0e)) 376 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 377 FTIM1_GPCM_TRAD(0x1f)) 378 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 379 FTIM2_GPCM_TCH(0x8) | \ 380 FTIM2_GPCM_TWP(0x1f)) 381 #define CONFIG_SYS_CS2_FTIM3 0x0 382 383 /* NAND Flash on IFC */ 384 #define CONFIG_NAND_FSL_IFC 385 #define CONFIG_SYS_NAND_BASE 0xff800000 386 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 387 388 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 389 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 390 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 391 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 392 | CSPR_V) 393 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 394 395 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 396 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 397 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 398 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 399 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 400 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 401 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 402 403 #define CONFIG_SYS_NAND_ONFI_DETECTION 404 405 /* ONFI NAND Flash mode0 Timing Params */ 406 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 407 FTIM0_NAND_TWP(0x18) | \ 408 FTIM0_NAND_TWCHT(0x07) | \ 409 FTIM0_NAND_TWH(0x0a)) 410 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 411 FTIM1_NAND_TWBE(0x39) | \ 412 FTIM1_NAND_TRR(0x0e) | \ 413 FTIM1_NAND_TRP(0x18)) 414 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 415 FTIM2_NAND_TREH(0x0a) | \ 416 FTIM2_NAND_TWHRE(0x1e)) 417 #define CONFIG_SYS_NAND_FTIM3 0x0 418 419 #define CONFIG_SYS_NAND_DDR_LAW 11 420 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 421 #define CONFIG_SYS_MAX_NAND_DEVICE 1 422 #define CONFIG_CMD_NAND 423 424 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 425 426 #if defined(CONFIG_NAND) 427 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 428 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 429 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 430 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 431 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 432 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 433 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 434 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 435 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 436 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 437 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 438 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 439 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 440 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 441 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 442 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 443 #else 444 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 445 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 446 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 447 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 448 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 449 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 450 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 451 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 452 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 453 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 454 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 455 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 456 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 457 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 458 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 459 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 460 #endif 461 462 #ifdef CONFIG_SPL_BUILD 463 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 464 #else 465 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 466 #endif 467 468 #if defined(CONFIG_RAMBOOT_PBL) 469 #define CONFIG_SYS_RAMBOOT 470 #endif 471 472 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 473 #if defined(CONFIG_NAND) 474 #define CONFIG_A008044_WORKAROUND 475 #endif 476 #endif 477 478 #define CONFIG_BOARD_EARLY_INIT_R 479 #define CONFIG_MISC_INIT_R 480 481 #define CONFIG_HWCONFIG 482 483 /* define to use L1 as initial stack */ 484 #define CONFIG_L1_INIT_RAM 485 #define CONFIG_SYS_INIT_RAM_LOCK 486 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 487 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 488 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 489 /* The assembler doesn't like typecast */ 490 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 491 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 492 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 493 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 494 495 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 496 GENERATED_GBL_DATA_SIZE) 497 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 498 499 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 500 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 501 502 /* Serial Port - controlled on board with jumper J8 503 * open - index 2 504 * shorted - index 1 505 */ 506 #define CONFIG_CONS_INDEX 1 507 #define CONFIG_SYS_NS16550_SERIAL 508 #define CONFIG_SYS_NS16550_REG_SIZE 1 509 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 510 511 #define CONFIG_SYS_BAUDRATE_TABLE \ 512 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 513 514 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 515 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 516 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 517 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 518 519 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB) 520 /* Video */ 521 #define CONFIG_FSL_DIU_FB 522 523 #ifdef CONFIG_FSL_DIU_FB 524 #define CONFIG_FSL_DIU_CH7301 525 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 526 #define CONFIG_CMD_BMP 527 #define CONFIG_VIDEO_LOGO 528 #define CONFIG_VIDEO_BMP_LOGO 529 #endif 530 #endif 531 532 /* I2C */ 533 #define CONFIG_SYS_I2C 534 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 535 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 536 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 537 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 538 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 539 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 540 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 541 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 542 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 543 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 544 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 545 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 546 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 547 548 /* I2C bus multiplexer */ 549 #define I2C_MUX_PCA_ADDR 0x70 550 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 551 #define I2C_MUX_CH_DEFAULT 0x8 552 #endif 553 554 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) 555 /* LDI/DVI Encoder for display */ 556 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 557 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 558 559 /* 560 * RTC configuration 561 */ 562 #define RTC 563 #define CONFIG_RTC_DS1337 1 564 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 565 566 /*DVI encoder*/ 567 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 568 #endif 569 570 /* 571 * eSPI - Enhanced SPI 572 */ 573 #define CONFIG_SPI_FLASH_BAR 574 #define CONFIG_SF_DEFAULT_SPEED 10000000 575 #define CONFIG_SF_DEFAULT_MODE 0 576 #define CONFIG_ENV_SPI_BUS 0 577 #define CONFIG_ENV_SPI_CS 0 578 #define CONFIG_ENV_SPI_MAX_HZ 10000000 579 #define CONFIG_ENV_SPI_MODE 0 580 581 /* 582 * General PCI 583 * Memory space is mapped 1-1, but I/O space must start from 0. 584 */ 585 586 #ifdef CONFIG_PCI 587 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 588 #ifdef CONFIG_PCIE1 589 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 590 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 591 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 592 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 593 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 594 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 595 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 596 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 597 #endif 598 599 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 600 #ifdef CONFIG_PCIE2 601 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 602 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 603 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 604 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 605 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 606 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 607 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 608 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 609 #endif 610 611 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 612 #ifdef CONFIG_PCIE3 613 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 614 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 615 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 616 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 617 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 618 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 619 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 620 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 621 #endif 622 623 /* controller 4, Base address 203000 */ 624 #ifdef CONFIG_PCIE4 625 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 626 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 627 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 628 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 629 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 630 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 631 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 632 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 633 #endif 634 635 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 636 637 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 638 #define CONFIG_DOS_PARTITION 639 #endif /* CONFIG_PCI */ 640 641 /* SATA */ 642 #define CONFIG_FSL_SATA_V2 643 #ifdef CONFIG_FSL_SATA_V2 644 #define CONFIG_LIBATA 645 #define CONFIG_FSL_SATA 646 647 #define CONFIG_SYS_SATA_MAX_DEVICE 1 648 #define CONFIG_SATA1 649 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 650 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 651 652 #define CONFIG_LBA48 653 #define CONFIG_CMD_SATA 654 #define CONFIG_DOS_PARTITION 655 #endif 656 657 /* 658 * USB 659 */ 660 #define CONFIG_HAS_FSL_DR_USB 661 662 #ifdef CONFIG_HAS_FSL_DR_USB 663 #define CONFIG_USB_EHCI 664 665 #ifdef CONFIG_USB_EHCI 666 #define CONFIG_USB_EHCI_FSL 667 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 668 #endif 669 #endif 670 671 #define CONFIG_MMC 672 673 #ifdef CONFIG_MMC 674 #define CONFIG_FSL_ESDHC 675 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 676 #define CONFIG_GENERIC_MMC 677 #define CONFIG_DOS_PARTITION 678 #endif 679 680 /* Qman/Bman */ 681 #ifndef CONFIG_NOBQFMAN 682 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 683 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 684 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 685 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 686 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 687 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 688 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 689 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 690 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 691 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 692 CONFIG_SYS_BMAN_CENA_SIZE) 693 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 694 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 695 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 696 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 697 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 698 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 699 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 700 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 701 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 702 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 703 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 704 CONFIG_SYS_QMAN_CENA_SIZE) 705 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 706 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 707 708 #define CONFIG_SYS_DPAA_FMAN 709 #define CONFIG_SYS_DPAA_PME 710 711 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 712 #define CONFIG_QE 713 #define CONFIG_U_QE 714 #endif 715 716 /* Default address of microcode for the Linux Fman driver */ 717 #if defined(CONFIG_SPIFLASH) 718 /* 719 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 720 * env, so we got 0x110000. 721 */ 722 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 723 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 724 #elif defined(CONFIG_SDCARD) 725 /* 726 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 727 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 728 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 729 */ 730 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 731 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 732 #elif defined(CONFIG_NAND) 733 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 734 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 735 #else 736 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 737 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 738 #endif 739 740 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 741 #if defined(CONFIG_SPIFLASH) 742 #define CONFIG_SYS_QE_FW_ADDR 0x130000 743 #elif defined(CONFIG_SDCARD) 744 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 745 #elif defined(CONFIG_NAND) 746 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 747 #else 748 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 749 #endif 750 #endif 751 752 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 753 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 754 #endif /* CONFIG_NOBQFMAN */ 755 756 #ifdef CONFIG_SYS_DPAA_FMAN 757 #define CONFIG_FMAN_ENET 758 #define CONFIG_PHY_VITESSE 759 #define CONFIG_PHY_REALTEK 760 #endif 761 762 #ifdef CONFIG_FMAN_ENET 763 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 764 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 765 #elif defined(CONFIG_T1040D4RDB) 766 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 767 #elif defined(CONFIG_T1042D4RDB) 768 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 769 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 770 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 771 #endif 772 773 #ifdef CONFIG_T104XD4RDB 774 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 775 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 776 #else 777 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 778 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 779 #endif 780 781 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 782 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) 783 #define CONFIG_VSC9953 784 #define CONFIG_CMD_ETHSW 785 #ifdef CONFIG_T1040RDB 786 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 787 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 788 #else 789 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 790 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 791 #endif 792 #endif 793 794 #define CONFIG_MII /* MII PHY management */ 795 #define CONFIG_ETHPRIME "FM1@DTSEC4" 796 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 797 #endif 798 799 /* 800 * Environment 801 */ 802 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 803 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 804 805 /* 806 * Command line configuration. 807 */ 808 #ifdef CONFIG_T1042RDB_PI 809 #define CONFIG_CMD_DATE 810 #endif 811 #define CONFIG_CMD_ERRATA 812 #define CONFIG_CMD_IRQ 813 #define CONFIG_CMD_REGINFO 814 815 #ifdef CONFIG_PCI 816 #define CONFIG_CMD_PCI 817 #endif 818 819 /* Hash command with SHA acceleration supported in hardware */ 820 #ifdef CONFIG_FSL_CAAM 821 #define CONFIG_CMD_HASH 822 #define CONFIG_SHA_HW_ACCEL 823 #endif 824 825 /* 826 * Miscellaneous configurable options 827 */ 828 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 829 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 830 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 831 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 832 #ifdef CONFIG_CMD_KGDB 833 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 834 #else 835 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 836 #endif 837 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 838 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 839 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 840 841 /* 842 * For booting Linux, the board info and command line data 843 * have to be in the first 64 MB of memory, since this is 844 * the maximum mapped by the Linux kernel during initialization. 845 */ 846 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 847 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 848 849 #ifdef CONFIG_CMD_KGDB 850 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 851 #endif 852 853 /* 854 * Dynamic MTD Partition support with mtdparts 855 */ 856 #ifndef CONFIG_SYS_NO_FLASH 857 #define CONFIG_MTD_DEVICE 858 #define CONFIG_MTD_PARTITIONS 859 #define CONFIG_CMD_MTDPARTS 860 #define CONFIG_FLASH_CFI_MTD 861 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 862 "spi0=spife110000.0" 863 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 864 "128k(dtb),96m(fs),-(user);"\ 865 "fff800000.flash:2m(uboot),9m(kernel),"\ 866 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 867 "2m(uboot),9m(kernel),128k(dtb),-(user)" 868 #endif 869 870 /* 871 * Environment Configuration 872 */ 873 #define CONFIG_ROOTPATH "/opt/nfsroot" 874 #define CONFIG_BOOTFILE "uImage" 875 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 876 877 /* default location for tftp and bootm */ 878 #define CONFIG_LOADADDR 1000000 879 880 881 #define CONFIG_BAUDRATE 115200 882 883 #define __USB_PHY_TYPE utmi 884 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 885 886 #ifdef CONFIG_T1040RDB 887 #define FDTFILE "t1040rdb/t1040rdb.dtb" 888 #elif defined(CONFIG_T1042RDB_PI) 889 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 890 #elif defined(CONFIG_T1042RDB) 891 #define FDTFILE "t1042rdb/t1042rdb.dtb" 892 #elif defined(CONFIG_T1040D4RDB) 893 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 894 #elif defined(CONFIG_T1042D4RDB) 895 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 896 #endif 897 898 #ifdef CONFIG_FSL_DIU_FB 899 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 900 #else 901 #define DIU_ENVIRONMENT 902 #endif 903 904 #define CONFIG_EXTRA_ENV_SETTINGS \ 905 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 906 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 907 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 908 "netdev=eth0\0" \ 909 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 910 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 911 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 912 "tftpflash=tftpboot $loadaddr $uboot && " \ 913 "protect off $ubootaddr +$filesize && " \ 914 "erase $ubootaddr +$filesize && " \ 915 "cp.b $loadaddr $ubootaddr $filesize && " \ 916 "protect on $ubootaddr +$filesize && " \ 917 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 918 "consoledev=ttyS0\0" \ 919 "ramdiskaddr=2000000\0" \ 920 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 921 "fdtaddr=1e00000\0" \ 922 "fdtfile=" __stringify(FDTFILE) "\0" \ 923 "bdev=sda3\0" 924 925 #define CONFIG_LINUX \ 926 "setenv bootargs root=/dev/ram rw " \ 927 "console=$consoledev,$baudrate $othbootargs;" \ 928 "setenv ramdiskaddr 0x02000000;" \ 929 "setenv fdtaddr 0x00c00000;" \ 930 "setenv loadaddr 0x1000000;" \ 931 "bootm $loadaddr $ramdiskaddr $fdtaddr" 932 933 #define CONFIG_HDBOOT \ 934 "setenv bootargs root=/dev/$bdev rw " \ 935 "console=$consoledev,$baudrate $othbootargs;" \ 936 "tftp $loadaddr $bootfile;" \ 937 "tftp $fdtaddr $fdtfile;" \ 938 "bootm $loadaddr - $fdtaddr" 939 940 #define CONFIG_NFSBOOTCOMMAND \ 941 "setenv bootargs root=/dev/nfs rw " \ 942 "nfsroot=$serverip:$rootpath " \ 943 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 944 "console=$consoledev,$baudrate $othbootargs;" \ 945 "tftp $loadaddr $bootfile;" \ 946 "tftp $fdtaddr $fdtfile;" \ 947 "bootm $loadaddr - $fdtaddr" 948 949 #define CONFIG_RAMBOOTCOMMAND \ 950 "setenv bootargs root=/dev/ram rw " \ 951 "console=$consoledev,$baudrate $othbootargs;" \ 952 "tftp $ramdiskaddr $ramdiskfile;" \ 953 "tftp $loadaddr $bootfile;" \ 954 "tftp $fdtaddr $fdtfile;" \ 955 "bootm $loadaddr $ramdiskaddr $fdtaddr" 956 957 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 958 959 #include <asm/fsl_secure_boot.h> 960 961 #endif /* __CONFIG_H */ 962