1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 15 #define CONFIG_E500 /* BOOKE e500 family */ 16 #include <asm/config_mpc85xx.h> 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 20 #ifndef CONFIG_SECURE_BOOT 21 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 22 #else 23 #define CONFIG_SYS_FSL_PBL_PBI \ 24 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 25 #endif 26 27 #define CONFIG_SPL_FLUSH_IMAGE 28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 29 #define CONFIG_FSL_LAW /* Use common FSL init code */ 30 #define CONFIG_SYS_TEXT_BASE 0x30001000 31 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 32 #define CONFIG_SPL_PAD_TO 0x40000 33 #define CONFIG_SPL_MAX_SIZE 0x28000 34 #ifdef CONFIG_SPL_BUILD 35 #define CONFIG_SPL_SKIP_RELOCATE 36 #define CONFIG_SPL_COMMON_INIT_DDR 37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 38 #define CONFIG_SYS_NO_FLASH 39 #endif 40 #define RESET_VECTOR_OFFSET 0x27FFC 41 #define BOOT_PAGE_OFFSET 0x27000 42 43 #ifdef CONFIG_NAND 44 #ifdef CONFIG_SECURE_BOOT 45 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 46 /* 47 * HDR would be appended at end of image and copied to DDR along 48 * with U-Boot image. 49 */ 50 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 51 CONFIG_U_BOOT_HDR_SIZE) 52 #else 53 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 54 #endif 55 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 56 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 57 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 58 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 59 #ifdef CONFIG_T1040RDB 60 #define CONFIG_SYS_FSL_PBL_RCW \ 61 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 62 #endif 63 #ifdef CONFIG_T1042RDB_PI 64 #define CONFIG_SYS_FSL_PBL_RCW \ 65 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 66 #endif 67 #ifdef CONFIG_T1042RDB 68 #define CONFIG_SYS_FSL_PBL_RCW \ 69 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 70 #endif 71 #ifdef CONFIG_T1040D4RDB 72 #define CONFIG_SYS_FSL_PBL_RCW \ 73 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 74 #endif 75 #ifdef CONFIG_T1042D4RDB 76 #define CONFIG_SYS_FSL_PBL_RCW \ 77 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 78 #endif 79 #define CONFIG_SPL_NAND_BOOT 80 #endif 81 82 #ifdef CONFIG_SPIFLASH 83 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 84 #define CONFIG_SPL_SPI_FLASH_MINIMAL 85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 89 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 90 #ifndef CONFIG_SPL_BUILD 91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 92 #endif 93 #ifdef CONFIG_T1040RDB 94 #define CONFIG_SYS_FSL_PBL_RCW \ 95 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 96 #endif 97 #ifdef CONFIG_T1042RDB_PI 98 #define CONFIG_SYS_FSL_PBL_RCW \ 99 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 100 #endif 101 #ifdef CONFIG_T1042RDB 102 #define CONFIG_SYS_FSL_PBL_RCW \ 103 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 104 #endif 105 #ifdef CONFIG_T1040D4RDB 106 #define CONFIG_SYS_FSL_PBL_RCW \ 107 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 108 #endif 109 #ifdef CONFIG_T1042D4RDB 110 #define CONFIG_SYS_FSL_PBL_RCW \ 111 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 112 #endif 113 #define CONFIG_SPL_SPI_BOOT 114 #endif 115 116 #ifdef CONFIG_SDCARD 117 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 118 #define CONFIG_SPL_MMC_MINIMAL 119 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 120 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 121 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 122 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 123 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 124 #ifndef CONFIG_SPL_BUILD 125 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 126 #endif 127 #ifdef CONFIG_T1040RDB 128 #define CONFIG_SYS_FSL_PBL_RCW \ 129 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 130 #endif 131 #ifdef CONFIG_T1042RDB_PI 132 #define CONFIG_SYS_FSL_PBL_RCW \ 133 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 134 #endif 135 #ifdef CONFIG_T1042RDB 136 #define CONFIG_SYS_FSL_PBL_RCW \ 137 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 138 #endif 139 #ifdef CONFIG_T1040D4RDB 140 #define CONFIG_SYS_FSL_PBL_RCW \ 141 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 142 #endif 143 #ifdef CONFIG_T1042D4RDB 144 #define CONFIG_SYS_FSL_PBL_RCW \ 145 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 146 #endif 147 #define CONFIG_SPL_MMC_BOOT 148 #endif 149 150 #endif 151 152 /* High Level Configuration Options */ 153 #define CONFIG_BOOKE 154 #define CONFIG_E500MC /* BOOKE e500mc family */ 155 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 156 #define CONFIG_MP /* support multiple processors */ 157 158 /* support deep sleep */ 159 #define CONFIG_DEEP_SLEEP 160 #if defined(CONFIG_DEEP_SLEEP) 161 #define CONFIG_BOARD_EARLY_INIT_F 162 #define CONFIG_SILENT_CONSOLE 163 #endif 164 165 #ifndef CONFIG_SYS_TEXT_BASE 166 #define CONFIG_SYS_TEXT_BASE 0xeff40000 167 #endif 168 169 #ifndef CONFIG_RESET_VECTOR_ADDRESS 170 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 171 #endif 172 173 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 174 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 175 #define CONFIG_FSL_IFC /* Enable IFC Support */ 176 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 177 #define CONFIG_PCI /* Enable PCI/PCIE */ 178 #define CONFIG_PCI_INDIRECT_BRIDGE 179 #define CONFIG_PCIE1 /* PCIE controller 1 */ 180 #define CONFIG_PCIE2 /* PCIE controller 2 */ 181 #define CONFIG_PCIE3 /* PCIE controller 3 */ 182 #define CONFIG_PCIE4 /* PCIE controller 4 */ 183 184 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 185 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 186 187 #define CONFIG_FSL_LAW /* Use common FSL init code */ 188 189 #define CONFIG_ENV_OVERWRITE 190 191 #ifndef CONFIG_SYS_NO_FLASH 192 #define CONFIG_FLASH_CFI_DRIVER 193 #define CONFIG_SYS_FLASH_CFI 194 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 195 #endif 196 197 #if defined(CONFIG_SPIFLASH) 198 #define CONFIG_SYS_EXTRA_ENV_RELOC 199 #define CONFIG_ENV_IS_IN_SPI_FLASH 200 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 201 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 202 #define CONFIG_ENV_SECT_SIZE 0x10000 203 #elif defined(CONFIG_SDCARD) 204 #define CONFIG_SYS_EXTRA_ENV_RELOC 205 #define CONFIG_ENV_IS_IN_MMC 206 #define CONFIG_SYS_MMC_ENV_DEV 0 207 #define CONFIG_ENV_SIZE 0x2000 208 #define CONFIG_ENV_OFFSET (512 * 0x800) 209 #elif defined(CONFIG_NAND) 210 #ifdef CONFIG_SECURE_BOOT 211 #define CONFIG_RAMBOOT_NAND 212 #define CONFIG_BOOTSCRIPT_COPY_RAM 213 #endif 214 #define CONFIG_SYS_EXTRA_ENV_RELOC 215 #define CONFIG_ENV_IS_IN_NAND 216 #define CONFIG_ENV_SIZE 0x2000 217 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 218 #else 219 #define CONFIG_ENV_IS_IN_FLASH 220 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 221 #define CONFIG_ENV_SIZE 0x2000 222 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 223 #endif 224 225 #define CONFIG_SYS_CLK_FREQ 100000000 226 #define CONFIG_DDR_CLK_FREQ 66666666 227 228 /* 229 * These can be toggled for performance analysis, otherwise use default. 230 */ 231 #define CONFIG_SYS_CACHE_STASHING 232 #define CONFIG_BACKSIDE_L2_CACHE 233 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 234 #define CONFIG_BTB /* toggle branch predition */ 235 #define CONFIG_DDR_ECC 236 #ifdef CONFIG_DDR_ECC 237 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 238 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 239 #endif 240 241 #define CONFIG_ENABLE_36BIT_PHYS 242 243 #define CONFIG_ADDR_MAP 244 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 245 246 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 247 #define CONFIG_SYS_MEMTEST_END 0x00400000 248 #define CONFIG_SYS_ALT_MEMTEST 249 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 250 251 /* 252 * Config the L3 Cache as L3 SRAM 253 */ 254 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 255 /* 256 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 257 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 258 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 259 */ 260 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 261 #define CONFIG_SYS_L3_SIZE 256 << 10 262 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 263 #ifdef CONFIG_RAMBOOT_PBL 264 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 265 #endif 266 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 267 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 268 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 269 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 270 271 #define CONFIG_SYS_DCSRBAR 0xf0000000 272 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 273 274 /* 275 * DDR Setup 276 */ 277 #define CONFIG_VERY_BIG_RAM 278 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 279 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 280 281 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 282 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 283 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 284 285 #define CONFIG_DDR_SPD 286 #ifndef CONFIG_SYS_FSL_DDR4 287 #define CONFIG_SYS_FSL_DDR3 288 #endif 289 290 #define CONFIG_SYS_SPD_BUS_NUM 0 291 #define SPD_EEPROM_ADDRESS 0x51 292 293 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 294 295 /* 296 * IFC Definitions 297 */ 298 #define CONFIG_SYS_FLASH_BASE 0xe8000000 299 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 300 301 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 302 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 303 CSPR_PORT_SIZE_16 | \ 304 CSPR_MSEL_NOR | \ 305 CSPR_V) 306 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 307 308 /* 309 * TDM Definition 310 */ 311 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 312 313 /* NOR Flash Timing Params */ 314 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 315 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 316 FTIM0_NOR_TEADC(0x5) | \ 317 FTIM0_NOR_TEAHC(0x5)) 318 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 319 FTIM1_NOR_TRAD_NOR(0x1A) |\ 320 FTIM1_NOR_TSEQRAD_NOR(0x13)) 321 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 322 FTIM2_NOR_TCH(0x4) | \ 323 FTIM2_NOR_TWPH(0x0E) | \ 324 FTIM2_NOR_TWP(0x1c)) 325 #define CONFIG_SYS_NOR_FTIM3 0x0 326 327 #define CONFIG_SYS_FLASH_QUIET_TEST 328 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 329 330 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 331 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 332 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 333 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 334 335 #define CONFIG_SYS_FLASH_EMPTY_INFO 336 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 337 338 /* CPLD on IFC */ 339 #define CPLD_LBMAP_MASK 0x3F 340 #define CPLD_BANK_SEL_MASK 0x07 341 #define CPLD_BANK_OVERRIDE 0x40 342 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 343 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 344 #define CPLD_LBMAP_RESET 0xFF 345 #define CPLD_LBMAP_SHIFT 0x03 346 347 #if defined(CONFIG_T1042RDB_PI) 348 #define CPLD_DIU_SEL_DFP 0x80 349 #elif defined(CONFIG_T1042D4RDB) 350 #define CPLD_DIU_SEL_DFP 0xc0 351 #endif 352 353 #if defined(CONFIG_T1040D4RDB) 354 #define CPLD_INT_MASK_ALL 0xFF 355 #define CPLD_INT_MASK_THERM 0x80 356 #define CPLD_INT_MASK_DVI_DFP 0x40 357 #define CPLD_INT_MASK_QSGMII1 0x20 358 #define CPLD_INT_MASK_QSGMII2 0x10 359 #define CPLD_INT_MASK_SGMI1 0x08 360 #define CPLD_INT_MASK_SGMI2 0x04 361 #define CPLD_INT_MASK_TDMR1 0x02 362 #define CPLD_INT_MASK_TDMR2 0x01 363 #endif 364 365 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 366 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 367 #define CONFIG_SYS_CSPR2_EXT (0xf) 368 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 369 | CSPR_PORT_SIZE_8 \ 370 | CSPR_MSEL_GPCM \ 371 | CSPR_V) 372 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 373 #define CONFIG_SYS_CSOR2 0x0 374 /* CPLD Timing parameters for IFC CS2 */ 375 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 376 FTIM0_GPCM_TEADC(0x0e) | \ 377 FTIM0_GPCM_TEAHC(0x0e)) 378 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 379 FTIM1_GPCM_TRAD(0x1f)) 380 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 381 FTIM2_GPCM_TCH(0x8) | \ 382 FTIM2_GPCM_TWP(0x1f)) 383 #define CONFIG_SYS_CS2_FTIM3 0x0 384 385 /* NAND Flash on IFC */ 386 #define CONFIG_NAND_FSL_IFC 387 #define CONFIG_SYS_NAND_BASE 0xff800000 388 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 389 390 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 391 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 392 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 393 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 394 | CSPR_V) 395 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 396 397 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 398 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 399 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 400 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 401 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 402 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 403 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 404 405 #define CONFIG_SYS_NAND_ONFI_DETECTION 406 407 /* ONFI NAND Flash mode0 Timing Params */ 408 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 409 FTIM0_NAND_TWP(0x18) | \ 410 FTIM0_NAND_TWCHT(0x07) | \ 411 FTIM0_NAND_TWH(0x0a)) 412 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 413 FTIM1_NAND_TWBE(0x39) | \ 414 FTIM1_NAND_TRR(0x0e) | \ 415 FTIM1_NAND_TRP(0x18)) 416 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 417 FTIM2_NAND_TREH(0x0a) | \ 418 FTIM2_NAND_TWHRE(0x1e)) 419 #define CONFIG_SYS_NAND_FTIM3 0x0 420 421 #define CONFIG_SYS_NAND_DDR_LAW 11 422 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 423 #define CONFIG_SYS_MAX_NAND_DEVICE 1 424 #define CONFIG_CMD_NAND 425 426 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 427 428 #if defined(CONFIG_NAND) 429 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 430 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 431 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 432 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 433 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 434 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 435 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 436 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 437 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 438 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 439 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 440 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 441 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 442 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 443 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 444 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 445 #else 446 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 447 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 448 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 449 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 450 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 451 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 452 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 453 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 454 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 455 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 456 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 457 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 458 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 459 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 460 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 461 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 462 #endif 463 464 #ifdef CONFIG_SPL_BUILD 465 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 466 #else 467 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 468 #endif 469 470 #if defined(CONFIG_RAMBOOT_PBL) 471 #define CONFIG_SYS_RAMBOOT 472 #endif 473 474 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 475 #if defined(CONFIG_NAND) 476 #define CONFIG_A008044_WORKAROUND 477 #endif 478 #endif 479 480 #define CONFIG_BOARD_EARLY_INIT_R 481 #define CONFIG_MISC_INIT_R 482 483 #define CONFIG_HWCONFIG 484 485 /* define to use L1 as initial stack */ 486 #define CONFIG_L1_INIT_RAM 487 #define CONFIG_SYS_INIT_RAM_LOCK 488 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 489 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 490 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 491 /* The assembler doesn't like typecast */ 492 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 493 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 494 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 495 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 496 497 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 498 GENERATED_GBL_DATA_SIZE) 499 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 500 501 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 502 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 503 504 /* Serial Port - controlled on board with jumper J8 505 * open - index 2 506 * shorted - index 1 507 */ 508 #define CONFIG_CONS_INDEX 1 509 #define CONFIG_SYS_NS16550_SERIAL 510 #define CONFIG_SYS_NS16550_REG_SIZE 1 511 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 512 513 #define CONFIG_SYS_BAUDRATE_TABLE \ 514 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 515 516 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 517 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 518 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 519 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 520 #ifndef CONFIG_SPL_BUILD 521 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 522 #endif 523 524 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB) 525 /* Video */ 526 #define CONFIG_FSL_DIU_FB 527 528 #ifdef CONFIG_FSL_DIU_FB 529 #define CONFIG_FSL_DIU_CH7301 530 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 531 #define CONFIG_VIDEO 532 #define CONFIG_CMD_BMP 533 #define CONFIG_CFB_CONSOLE 534 #define CONFIG_CFB_CONSOLE_ANSI 535 #define CONFIG_VIDEO_SW_CURSOR 536 #define CONFIG_VGA_AS_SINGLE_DEVICE 537 #define CONFIG_VIDEO_LOGO 538 #define CONFIG_VIDEO_BMP_LOGO 539 #endif 540 #endif 541 542 /* I2C */ 543 #define CONFIG_SYS_I2C 544 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 545 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 546 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 547 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 548 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 549 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 550 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 551 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 552 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 553 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 554 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 555 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 556 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 557 558 /* I2C bus multiplexer */ 559 #define I2C_MUX_PCA_ADDR 0x70 560 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 561 #define I2C_MUX_CH_DEFAULT 0x8 562 #endif 563 564 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) 565 /* LDI/DVI Encoder for display */ 566 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 567 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 568 569 /* 570 * RTC configuration 571 */ 572 #define RTC 573 #define CONFIG_RTC_DS1337 1 574 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 575 576 /*DVI encoder*/ 577 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 578 #endif 579 580 /* 581 * eSPI - Enhanced SPI 582 */ 583 #define CONFIG_SPI_FLASH_BAR 584 #define CONFIG_SF_DEFAULT_SPEED 10000000 585 #define CONFIG_SF_DEFAULT_MODE 0 586 #define CONFIG_ENV_SPI_BUS 0 587 #define CONFIG_ENV_SPI_CS 0 588 #define CONFIG_ENV_SPI_MAX_HZ 10000000 589 #define CONFIG_ENV_SPI_MODE 0 590 591 /* 592 * General PCI 593 * Memory space is mapped 1-1, but I/O space must start from 0. 594 */ 595 596 #ifdef CONFIG_PCI 597 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 598 #ifdef CONFIG_PCIE1 599 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 600 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 601 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 602 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 603 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 604 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 605 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 606 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 607 #endif 608 609 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 610 #ifdef CONFIG_PCIE2 611 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 612 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 613 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 614 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 615 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 616 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 617 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 618 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 619 #endif 620 621 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 622 #ifdef CONFIG_PCIE3 623 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 624 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 625 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 626 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 627 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 628 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 629 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 630 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 631 #endif 632 633 /* controller 4, Base address 203000 */ 634 #ifdef CONFIG_PCIE4 635 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 636 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 637 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 638 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 639 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 640 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 641 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 642 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 643 #endif 644 645 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 646 647 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 648 #define CONFIG_DOS_PARTITION 649 #endif /* CONFIG_PCI */ 650 651 /* SATA */ 652 #define CONFIG_FSL_SATA_V2 653 #ifdef CONFIG_FSL_SATA_V2 654 #define CONFIG_LIBATA 655 #define CONFIG_FSL_SATA 656 657 #define CONFIG_SYS_SATA_MAX_DEVICE 1 658 #define CONFIG_SATA1 659 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 660 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 661 662 #define CONFIG_LBA48 663 #define CONFIG_CMD_SATA 664 #define CONFIG_DOS_PARTITION 665 #endif 666 667 /* 668 * USB 669 */ 670 #define CONFIG_HAS_FSL_DR_USB 671 672 #ifdef CONFIG_HAS_FSL_DR_USB 673 #define CONFIG_USB_EHCI 674 675 #ifdef CONFIG_USB_EHCI 676 #define CONFIG_USB_EHCI_FSL 677 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 678 #endif 679 #endif 680 681 #define CONFIG_MMC 682 683 #ifdef CONFIG_MMC 684 #define CONFIG_FSL_ESDHC 685 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 686 #define CONFIG_GENERIC_MMC 687 #define CONFIG_DOS_PARTITION 688 #endif 689 690 /* Qman/Bman */ 691 #ifndef CONFIG_NOBQFMAN 692 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 693 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 694 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 695 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 696 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 697 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 698 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 699 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 700 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 701 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 702 CONFIG_SYS_BMAN_CENA_SIZE) 703 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 704 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 705 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 706 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 707 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 708 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 709 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 710 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 711 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 712 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 713 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 714 CONFIG_SYS_QMAN_CENA_SIZE) 715 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 716 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 717 718 #define CONFIG_SYS_DPAA_FMAN 719 #define CONFIG_SYS_DPAA_PME 720 721 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 722 #define CONFIG_QE 723 #define CONFIG_U_QE 724 #endif 725 726 /* Default address of microcode for the Linux Fman driver */ 727 #if defined(CONFIG_SPIFLASH) 728 /* 729 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 730 * env, so we got 0x110000. 731 */ 732 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 733 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 734 #elif defined(CONFIG_SDCARD) 735 /* 736 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 737 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 738 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 739 */ 740 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 741 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 742 #elif defined(CONFIG_NAND) 743 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 744 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 745 #else 746 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 747 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 748 #endif 749 750 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 751 #if defined(CONFIG_SPIFLASH) 752 #define CONFIG_SYS_QE_FW_ADDR 0x130000 753 #elif defined(CONFIG_SDCARD) 754 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 755 #elif defined(CONFIG_NAND) 756 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 757 #else 758 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 759 #endif 760 #endif 761 762 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 763 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 764 #endif /* CONFIG_NOBQFMAN */ 765 766 #ifdef CONFIG_SYS_DPAA_FMAN 767 #define CONFIG_FMAN_ENET 768 #define CONFIG_PHY_VITESSE 769 #define CONFIG_PHY_REALTEK 770 #endif 771 772 #ifdef CONFIG_FMAN_ENET 773 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 774 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 775 #elif defined(CONFIG_T1040D4RDB) 776 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 777 #elif defined(CONFIG_T1042D4RDB) 778 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 779 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 780 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 781 #endif 782 783 #ifdef CONFIG_T104XD4RDB 784 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 785 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 786 #else 787 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 788 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 789 #endif 790 791 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 792 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) 793 #define CONFIG_VSC9953 794 #define CONFIG_CMD_ETHSW 795 #ifdef CONFIG_T1040RDB 796 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 797 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 798 #else 799 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 800 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 801 #endif 802 #endif 803 804 #define CONFIG_MII /* MII PHY management */ 805 #define CONFIG_ETHPRIME "FM1@DTSEC4" 806 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 807 #endif 808 809 /* 810 * Environment 811 */ 812 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 813 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 814 815 /* 816 * Command line configuration. 817 */ 818 #ifdef CONFIG_T1042RDB_PI 819 #define CONFIG_CMD_DATE 820 #endif 821 #define CONFIG_CMD_ERRATA 822 #define CONFIG_CMD_IRQ 823 #define CONFIG_CMD_REGINFO 824 825 #ifdef CONFIG_PCI 826 #define CONFIG_CMD_PCI 827 #endif 828 829 /* Hash command with SHA acceleration supported in hardware */ 830 #ifdef CONFIG_FSL_CAAM 831 #define CONFIG_CMD_HASH 832 #define CONFIG_SHA_HW_ACCEL 833 #endif 834 835 /* 836 * Miscellaneous configurable options 837 */ 838 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 839 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 840 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 841 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 842 #ifdef CONFIG_CMD_KGDB 843 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 844 #else 845 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 846 #endif 847 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 848 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 849 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 850 851 /* 852 * For booting Linux, the board info and command line data 853 * have to be in the first 64 MB of memory, since this is 854 * the maximum mapped by the Linux kernel during initialization. 855 */ 856 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 857 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 858 859 #ifdef CONFIG_CMD_KGDB 860 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 861 #endif 862 863 /* 864 * Dynamic MTD Partition support with mtdparts 865 */ 866 #ifndef CONFIG_SYS_NO_FLASH 867 #define CONFIG_MTD_DEVICE 868 #define CONFIG_MTD_PARTITIONS 869 #define CONFIG_CMD_MTDPARTS 870 #define CONFIG_FLASH_CFI_MTD 871 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 872 "spi0=spife110000.0" 873 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 874 "128k(dtb),96m(fs),-(user);"\ 875 "fff800000.flash:2m(uboot),9m(kernel),"\ 876 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 877 "2m(uboot),9m(kernel),128k(dtb),-(user)" 878 #endif 879 880 /* 881 * Environment Configuration 882 */ 883 #define CONFIG_ROOTPATH "/opt/nfsroot" 884 #define CONFIG_BOOTFILE "uImage" 885 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 886 887 /* default location for tftp and bootm */ 888 #define CONFIG_LOADADDR 1000000 889 890 891 #define CONFIG_BAUDRATE 115200 892 893 #define __USB_PHY_TYPE utmi 894 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 895 896 #ifdef CONFIG_T1040RDB 897 #define FDTFILE "t1040rdb/t1040rdb.dtb" 898 #elif defined(CONFIG_T1042RDB_PI) 899 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 900 #elif defined(CONFIG_T1042RDB) 901 #define FDTFILE "t1042rdb/t1042rdb.dtb" 902 #elif defined(CONFIG_T1040D4RDB) 903 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 904 #elif defined(CONFIG_T1042D4RDB) 905 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 906 #endif 907 908 #ifdef CONFIG_FSL_DIU_FB 909 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 910 #else 911 #define DIU_ENVIRONMENT 912 #endif 913 914 #define CONFIG_EXTRA_ENV_SETTINGS \ 915 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 916 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 917 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 918 "netdev=eth0\0" \ 919 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 920 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 921 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 922 "tftpflash=tftpboot $loadaddr $uboot && " \ 923 "protect off $ubootaddr +$filesize && " \ 924 "erase $ubootaddr +$filesize && " \ 925 "cp.b $loadaddr $ubootaddr $filesize && " \ 926 "protect on $ubootaddr +$filesize && " \ 927 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 928 "consoledev=ttyS0\0" \ 929 "ramdiskaddr=2000000\0" \ 930 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 931 "fdtaddr=1e00000\0" \ 932 "fdtfile=" __stringify(FDTFILE) "\0" \ 933 "bdev=sda3\0" 934 935 #define CONFIG_LINUX \ 936 "setenv bootargs root=/dev/ram rw " \ 937 "console=$consoledev,$baudrate $othbootargs;" \ 938 "setenv ramdiskaddr 0x02000000;" \ 939 "setenv fdtaddr 0x00c00000;" \ 940 "setenv loadaddr 0x1000000;" \ 941 "bootm $loadaddr $ramdiskaddr $fdtaddr" 942 943 #define CONFIG_HDBOOT \ 944 "setenv bootargs root=/dev/$bdev rw " \ 945 "console=$consoledev,$baudrate $othbootargs;" \ 946 "tftp $loadaddr $bootfile;" \ 947 "tftp $fdtaddr $fdtfile;" \ 948 "bootm $loadaddr - $fdtaddr" 949 950 #define CONFIG_NFSBOOTCOMMAND \ 951 "setenv bootargs root=/dev/nfs rw " \ 952 "nfsroot=$serverip:$rootpath " \ 953 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 954 "console=$consoledev,$baudrate $othbootargs;" \ 955 "tftp $loadaddr $bootfile;" \ 956 "tftp $fdtaddr $fdtfile;" \ 957 "bootm $loadaddr - $fdtaddr" 958 959 #define CONFIG_RAMBOOTCOMMAND \ 960 "setenv bootargs root=/dev/ram rw " \ 961 "console=$consoledev,$baudrate $othbootargs;" \ 962 "tftp $ramdiskaddr $ramdiskfile;" \ 963 "tftp $loadaddr $bootfile;" \ 964 "tftp $fdtaddr $fdtfile;" \ 965 "bootm $loadaddr $ramdiskaddr $fdtaddr" 966 967 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 968 969 #include <asm/fsl_secure_boot.h> 970 971 #endif /* __CONFIG_H */ 972