1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #include <asm/config_mpc85xx.h> 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 17 #ifndef CONFIG_SECURE_BOOT 18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 19 #else 20 #define CONFIG_SYS_FSL_PBL_PBI \ 21 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 22 #endif 23 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x30001000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #ifdef CONFIG_SPL_BUILD 31 #define CONFIG_SPL_SKIP_RELOCATE 32 #define CONFIG_SPL_COMMON_INIT_DDR 33 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 34 #endif 35 #define RESET_VECTOR_OFFSET 0x27FFC 36 #define BOOT_PAGE_OFFSET 0x27000 37 38 #ifdef CONFIG_NAND 39 #ifdef CONFIG_SECURE_BOOT 40 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 41 /* 42 * HDR would be appended at end of image and copied to DDR along 43 * with U-Boot image. 44 */ 45 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 46 CONFIG_U_BOOT_HDR_SIZE) 47 #else 48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 49 #endif 50 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 51 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 52 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 54 #ifdef CONFIG_TARGET_T1040RDB 55 #define CONFIG_SYS_FSL_PBL_RCW \ 56 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 57 #endif 58 #ifdef CONFIG_TARGET_T1042RDB_PI 59 #define CONFIG_SYS_FSL_PBL_RCW \ 60 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 61 #endif 62 #ifdef CONFIG_TARGET_T1042RDB 63 #define CONFIG_SYS_FSL_PBL_RCW \ 64 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 65 #endif 66 #ifdef CONFIG_TARGET_T1040D4RDB 67 #define CONFIG_SYS_FSL_PBL_RCW \ 68 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 69 #endif 70 #ifdef CONFIG_TARGET_T1042D4RDB 71 #define CONFIG_SYS_FSL_PBL_RCW \ 72 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 73 #endif 74 #define CONFIG_SPL_NAND_BOOT 75 #endif 76 77 #ifdef CONFIG_SPIFLASH 78 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 79 #define CONFIG_SPL_SPI_FLASH_MINIMAL 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 84 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 85 #ifndef CONFIG_SPL_BUILD 86 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 87 #endif 88 #ifdef CONFIG_TARGET_T1040RDB 89 #define CONFIG_SYS_FSL_PBL_RCW \ 90 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 91 #endif 92 #ifdef CONFIG_TARGET_T1042RDB_PI 93 #define CONFIG_SYS_FSL_PBL_RCW \ 94 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 95 #endif 96 #ifdef CONFIG_TARGET_T1042RDB 97 #define CONFIG_SYS_FSL_PBL_RCW \ 98 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 99 #endif 100 #ifdef CONFIG_TARGET_T1040D4RDB 101 #define CONFIG_SYS_FSL_PBL_RCW \ 102 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 103 #endif 104 #ifdef CONFIG_TARGET_T1042D4RDB 105 #define CONFIG_SYS_FSL_PBL_RCW \ 106 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 107 #endif 108 #define CONFIG_SPL_SPI_BOOT 109 #endif 110 111 #ifdef CONFIG_SDCARD 112 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 113 #define CONFIG_SPL_MMC_MINIMAL 114 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 115 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 116 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 117 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 118 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 119 #ifndef CONFIG_SPL_BUILD 120 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 121 #endif 122 #ifdef CONFIG_TARGET_T1040RDB 123 #define CONFIG_SYS_FSL_PBL_RCW \ 124 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 125 #endif 126 #ifdef CONFIG_TARGET_T1042RDB_PI 127 #define CONFIG_SYS_FSL_PBL_RCW \ 128 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 129 #endif 130 #ifdef CONFIG_TARGET_T1042RDB 131 #define CONFIG_SYS_FSL_PBL_RCW \ 132 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 133 #endif 134 #ifdef CONFIG_TARGET_T1040D4RDB 135 #define CONFIG_SYS_FSL_PBL_RCW \ 136 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 137 #endif 138 #ifdef CONFIG_TARGET_T1042D4RDB 139 #define CONFIG_SYS_FSL_PBL_RCW \ 140 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 141 #endif 142 #define CONFIG_SPL_MMC_BOOT 143 #endif 144 145 #endif 146 147 /* High Level Configuration Options */ 148 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 149 #define CONFIG_MP /* support multiple processors */ 150 151 /* support deep sleep */ 152 #define CONFIG_DEEP_SLEEP 153 154 #ifndef CONFIG_SYS_TEXT_BASE 155 #define CONFIG_SYS_TEXT_BASE 0xeff40000 156 #endif 157 158 #ifndef CONFIG_RESET_VECTOR_ADDRESS 159 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 160 #endif 161 162 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 163 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 164 #define CONFIG_PCI_INDIRECT_BRIDGE 165 #define CONFIG_PCIE1 /* PCIE controller 1 */ 166 #define CONFIG_PCIE2 /* PCIE controller 2 */ 167 #define CONFIG_PCIE3 /* PCIE controller 3 */ 168 #define CONFIG_PCIE4 /* PCIE controller 4 */ 169 170 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 171 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 172 173 #define CONFIG_ENV_OVERWRITE 174 175 #ifdef CONFIG_MTD_NOR_FLASH 176 #define CONFIG_FLASH_CFI_DRIVER 177 #define CONFIG_SYS_FLASH_CFI 178 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 179 #endif 180 181 #if defined(CONFIG_SPIFLASH) 182 #define CONFIG_SYS_EXTRA_ENV_RELOC 183 #define CONFIG_ENV_IS_IN_SPI_FLASH 184 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 185 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 186 #define CONFIG_ENV_SECT_SIZE 0x10000 187 #elif defined(CONFIG_SDCARD) 188 #define CONFIG_SYS_EXTRA_ENV_RELOC 189 #define CONFIG_SYS_MMC_ENV_DEV 0 190 #define CONFIG_ENV_SIZE 0x2000 191 #define CONFIG_ENV_OFFSET (512 * 0x800) 192 #elif defined(CONFIG_NAND) 193 #ifdef CONFIG_SECURE_BOOT 194 #define CONFIG_RAMBOOT_NAND 195 #define CONFIG_BOOTSCRIPT_COPY_RAM 196 #endif 197 #define CONFIG_SYS_EXTRA_ENV_RELOC 198 #define CONFIG_ENV_SIZE 0x2000 199 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 200 #else 201 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 202 #define CONFIG_ENV_SIZE 0x2000 203 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 204 #endif 205 206 #define CONFIG_SYS_CLK_FREQ 100000000 207 #define CONFIG_DDR_CLK_FREQ 66666666 208 209 /* 210 * These can be toggled for performance analysis, otherwise use default. 211 */ 212 #define CONFIG_SYS_CACHE_STASHING 213 #define CONFIG_BACKSIDE_L2_CACHE 214 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 215 #define CONFIG_BTB /* toggle branch predition */ 216 #define CONFIG_DDR_ECC 217 #ifdef CONFIG_DDR_ECC 218 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 219 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 220 #endif 221 222 #define CONFIG_ENABLE_36BIT_PHYS 223 224 #define CONFIG_ADDR_MAP 225 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 226 227 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 228 #define CONFIG_SYS_MEMTEST_END 0x00400000 229 #define CONFIG_SYS_ALT_MEMTEST 230 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 231 232 /* 233 * Config the L3 Cache as L3 SRAM 234 */ 235 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 236 /* 237 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 238 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 239 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 240 */ 241 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 242 #define CONFIG_SYS_L3_SIZE 256 << 10 243 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 244 #ifdef CONFIG_RAMBOOT_PBL 245 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 246 #endif 247 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 248 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 249 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 250 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 251 252 #define CONFIG_SYS_DCSRBAR 0xf0000000 253 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 254 255 /* 256 * DDR Setup 257 */ 258 #define CONFIG_VERY_BIG_RAM 259 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 260 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 261 262 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 263 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 264 265 #define CONFIG_DDR_SPD 266 267 #define CONFIG_SYS_SPD_BUS_NUM 0 268 #define SPD_EEPROM_ADDRESS 0x51 269 270 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 271 272 /* 273 * IFC Definitions 274 */ 275 #define CONFIG_SYS_FLASH_BASE 0xe8000000 276 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 277 278 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 279 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 280 CSPR_PORT_SIZE_16 | \ 281 CSPR_MSEL_NOR | \ 282 CSPR_V) 283 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 284 285 /* 286 * TDM Definition 287 */ 288 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 289 290 /* NOR Flash Timing Params */ 291 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 292 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 293 FTIM0_NOR_TEADC(0x5) | \ 294 FTIM0_NOR_TEAHC(0x5)) 295 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 296 FTIM1_NOR_TRAD_NOR(0x1A) |\ 297 FTIM1_NOR_TSEQRAD_NOR(0x13)) 298 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 299 FTIM2_NOR_TCH(0x4) | \ 300 FTIM2_NOR_TWPH(0x0E) | \ 301 FTIM2_NOR_TWP(0x1c)) 302 #define CONFIG_SYS_NOR_FTIM3 0x0 303 304 #define CONFIG_SYS_FLASH_QUIET_TEST 305 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 306 307 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 308 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 309 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 310 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 311 312 #define CONFIG_SYS_FLASH_EMPTY_INFO 313 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 314 315 /* CPLD on IFC */ 316 #define CPLD_LBMAP_MASK 0x3F 317 #define CPLD_BANK_SEL_MASK 0x07 318 #define CPLD_BANK_OVERRIDE 0x40 319 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 320 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 321 #define CPLD_LBMAP_RESET 0xFF 322 #define CPLD_LBMAP_SHIFT 0x03 323 324 #if defined(CONFIG_TARGET_T1042RDB_PI) 325 #define CPLD_DIU_SEL_DFP 0x80 326 #elif defined(CONFIG_TARGET_T1042D4RDB) 327 #define CPLD_DIU_SEL_DFP 0xc0 328 #endif 329 330 #if defined(CONFIG_TARGET_T1040D4RDB) 331 #define CPLD_INT_MASK_ALL 0xFF 332 #define CPLD_INT_MASK_THERM 0x80 333 #define CPLD_INT_MASK_DVI_DFP 0x40 334 #define CPLD_INT_MASK_QSGMII1 0x20 335 #define CPLD_INT_MASK_QSGMII2 0x10 336 #define CPLD_INT_MASK_SGMI1 0x08 337 #define CPLD_INT_MASK_SGMI2 0x04 338 #define CPLD_INT_MASK_TDMR1 0x02 339 #define CPLD_INT_MASK_TDMR2 0x01 340 #endif 341 342 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 343 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 344 #define CONFIG_SYS_CSPR2_EXT (0xf) 345 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 346 | CSPR_PORT_SIZE_8 \ 347 | CSPR_MSEL_GPCM \ 348 | CSPR_V) 349 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 350 #define CONFIG_SYS_CSOR2 0x0 351 /* CPLD Timing parameters for IFC CS2 */ 352 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 353 FTIM0_GPCM_TEADC(0x0e) | \ 354 FTIM0_GPCM_TEAHC(0x0e)) 355 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 356 FTIM1_GPCM_TRAD(0x1f)) 357 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 358 FTIM2_GPCM_TCH(0x8) | \ 359 FTIM2_GPCM_TWP(0x1f)) 360 #define CONFIG_SYS_CS2_FTIM3 0x0 361 362 /* NAND Flash on IFC */ 363 #define CONFIG_NAND_FSL_IFC 364 #define CONFIG_SYS_NAND_BASE 0xff800000 365 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 366 367 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 368 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 369 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 370 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 371 | CSPR_V) 372 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 373 374 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 375 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 376 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 377 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 378 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 379 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 380 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 381 382 #define CONFIG_SYS_NAND_ONFI_DETECTION 383 384 /* ONFI NAND Flash mode0 Timing Params */ 385 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 386 FTIM0_NAND_TWP(0x18) | \ 387 FTIM0_NAND_TWCHT(0x07) | \ 388 FTIM0_NAND_TWH(0x0a)) 389 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 390 FTIM1_NAND_TWBE(0x39) | \ 391 FTIM1_NAND_TRR(0x0e) | \ 392 FTIM1_NAND_TRP(0x18)) 393 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 394 FTIM2_NAND_TREH(0x0a) | \ 395 FTIM2_NAND_TWHRE(0x1e)) 396 #define CONFIG_SYS_NAND_FTIM3 0x0 397 398 #define CONFIG_SYS_NAND_DDR_LAW 11 399 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 400 #define CONFIG_SYS_MAX_NAND_DEVICE 1 401 #define CONFIG_CMD_NAND 402 403 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 404 405 #if defined(CONFIG_NAND) 406 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 407 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 408 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 409 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 410 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 411 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 412 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 413 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 414 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 415 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 416 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 417 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 418 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 419 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 420 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 421 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 422 #else 423 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 424 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 425 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 426 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 427 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 428 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 429 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 430 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 431 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 432 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 433 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 434 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 435 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 436 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 437 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 438 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 439 #endif 440 441 #ifdef CONFIG_SPL_BUILD 442 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 443 #else 444 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 445 #endif 446 447 #if defined(CONFIG_RAMBOOT_PBL) 448 #define CONFIG_SYS_RAMBOOT 449 #endif 450 451 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 452 #if defined(CONFIG_NAND) 453 #define CONFIG_A008044_WORKAROUND 454 #endif 455 #endif 456 457 #define CONFIG_BOARD_EARLY_INIT_R 458 #define CONFIG_MISC_INIT_R 459 460 #define CONFIG_HWCONFIG 461 462 /* define to use L1 as initial stack */ 463 #define CONFIG_L1_INIT_RAM 464 #define CONFIG_SYS_INIT_RAM_LOCK 465 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 466 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 467 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 468 /* The assembler doesn't like typecast */ 469 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 470 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 471 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 472 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 473 474 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 475 GENERATED_GBL_DATA_SIZE) 476 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 477 478 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 479 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 480 481 /* Serial Port - controlled on board with jumper J8 482 * open - index 2 483 * shorted - index 1 484 */ 485 #define CONFIG_CONS_INDEX 1 486 #define CONFIG_SYS_NS16550_SERIAL 487 #define CONFIG_SYS_NS16550_REG_SIZE 1 488 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 489 490 #define CONFIG_SYS_BAUDRATE_TABLE \ 491 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 492 493 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 494 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 495 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 496 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 497 498 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) 499 /* Video */ 500 #define CONFIG_FSL_DIU_FB 501 502 #ifdef CONFIG_FSL_DIU_FB 503 #define CONFIG_FSL_DIU_CH7301 504 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 505 #define CONFIG_VIDEO_LOGO 506 #define CONFIG_VIDEO_BMP_LOGO 507 #endif 508 #endif 509 510 /* I2C */ 511 #define CONFIG_SYS_I2C 512 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 513 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 514 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 515 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 516 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 517 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 518 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 519 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 520 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 521 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 522 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 523 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 524 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 525 526 /* I2C bus multiplexer */ 527 #define I2C_MUX_PCA_ADDR 0x70 528 #define I2C_MUX_CH_DEFAULT 0x8 529 530 #if defined(CONFIG_TARGET_T1042RDB_PI) || \ 531 defined(CONFIG_TARGET_T1040D4RDB) || \ 532 defined(CONFIG_TARGET_T1042D4RDB) 533 /* LDI/DVI Encoder for display */ 534 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 535 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 536 537 /* 538 * RTC configuration 539 */ 540 #define RTC 541 #define CONFIG_RTC_DS1337 1 542 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 543 544 /*DVI encoder*/ 545 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 546 #endif 547 548 /* 549 * eSPI - Enhanced SPI 550 */ 551 #define CONFIG_SPI_FLASH_BAR 552 #define CONFIG_SF_DEFAULT_SPEED 10000000 553 #define CONFIG_SF_DEFAULT_MODE 0 554 #define CONFIG_ENV_SPI_BUS 0 555 #define CONFIG_ENV_SPI_CS 0 556 #define CONFIG_ENV_SPI_MAX_HZ 10000000 557 #define CONFIG_ENV_SPI_MODE 0 558 559 /* 560 * General PCI 561 * Memory space is mapped 1-1, but I/O space must start from 0. 562 */ 563 564 #ifdef CONFIG_PCI 565 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 566 #ifdef CONFIG_PCIE1 567 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 568 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 569 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 570 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 571 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 572 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 573 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 574 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 575 #endif 576 577 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 578 #ifdef CONFIG_PCIE2 579 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 580 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 581 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 582 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 583 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 584 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 585 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 586 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 587 #endif 588 589 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 590 #ifdef CONFIG_PCIE3 591 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 592 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 593 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 594 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 595 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 596 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 597 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 598 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 599 #endif 600 601 /* controller 4, Base address 203000 */ 602 #ifdef CONFIG_PCIE4 603 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 604 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 605 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 606 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 607 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 608 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 609 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 610 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 611 #endif 612 613 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 614 #endif /* CONFIG_PCI */ 615 616 /* SATA */ 617 #define CONFIG_FSL_SATA_V2 618 #ifdef CONFIG_FSL_SATA_V2 619 #define CONFIG_LIBATA 620 #define CONFIG_FSL_SATA 621 622 #define CONFIG_SYS_SATA_MAX_DEVICE 1 623 #define CONFIG_SATA1 624 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 625 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 626 627 #define CONFIG_LBA48 628 #endif 629 630 /* 631 * USB 632 */ 633 #define CONFIG_HAS_FSL_DR_USB 634 635 #ifdef CONFIG_HAS_FSL_DR_USB 636 #ifdef CONFIG_USB_EHCI_HCD 637 #define CONFIG_USB_EHCI_FSL 638 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 639 #endif 640 #endif 641 642 #ifdef CONFIG_MMC 643 #define CONFIG_FSL_ESDHC 644 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 645 #endif 646 647 /* Qman/Bman */ 648 #ifndef CONFIG_NOBQFMAN 649 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 650 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 651 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 652 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 653 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 654 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 655 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 656 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 657 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 658 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 659 CONFIG_SYS_BMAN_CENA_SIZE) 660 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 661 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 662 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 663 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 664 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 665 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 666 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 667 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 668 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 669 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 670 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 671 CONFIG_SYS_QMAN_CENA_SIZE) 672 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 673 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 674 675 #define CONFIG_SYS_DPAA_FMAN 676 #define CONFIG_SYS_DPAA_PME 677 678 #define CONFIG_QE 679 #define CONFIG_U_QE 680 681 /* Default address of microcode for the Linux Fman driver */ 682 #if defined(CONFIG_SPIFLASH) 683 /* 684 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 685 * env, so we got 0x110000. 686 */ 687 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 688 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 689 #elif defined(CONFIG_SDCARD) 690 /* 691 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 692 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 693 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 694 */ 695 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 696 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 697 #elif defined(CONFIG_NAND) 698 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 699 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 700 #else 701 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 702 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 703 #endif 704 705 #if defined(CONFIG_SPIFLASH) 706 #define CONFIG_SYS_QE_FW_ADDR 0x130000 707 #elif defined(CONFIG_SDCARD) 708 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 709 #elif defined(CONFIG_NAND) 710 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 711 #else 712 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 713 #endif 714 715 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 716 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 717 #endif /* CONFIG_NOBQFMAN */ 718 719 #ifdef CONFIG_SYS_DPAA_FMAN 720 #define CONFIG_FMAN_ENET 721 #define CONFIG_PHY_VITESSE 722 #define CONFIG_PHY_REALTEK 723 #endif 724 725 #ifdef CONFIG_FMAN_ENET 726 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) 727 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 728 #elif defined(CONFIG_TARGET_T1040D4RDB) 729 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 730 #elif defined(CONFIG_TARGET_T1042D4RDB) 731 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 732 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 733 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 734 #endif 735 736 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 737 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 738 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 739 #else 740 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 741 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 742 #endif 743 744 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 745 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) 746 #define CONFIG_VSC9953 747 #ifdef CONFIG_TARGET_T1040RDB 748 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 749 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 750 #else 751 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 752 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 753 #endif 754 #endif 755 756 #define CONFIG_MII /* MII PHY management */ 757 #define CONFIG_ETHPRIME "FM1@DTSEC4" 758 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 759 #endif 760 761 /* 762 * Environment 763 */ 764 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 765 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 766 767 /* 768 * Command line configuration. 769 */ 770 #define CONFIG_CMD_REGINFO 771 772 #ifdef CONFIG_PCI 773 #define CONFIG_CMD_PCI 774 #endif 775 776 /* 777 * Miscellaneous configurable options 778 */ 779 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 780 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 781 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 782 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 783 #ifdef CONFIG_CMD_KGDB 784 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 785 #else 786 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 787 #endif 788 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 789 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 790 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 791 792 /* 793 * For booting Linux, the board info and command line data 794 * have to be in the first 64 MB of memory, since this is 795 * the maximum mapped by the Linux kernel during initialization. 796 */ 797 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 798 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 799 800 #ifdef CONFIG_CMD_KGDB 801 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 802 #endif 803 804 /* 805 * Dynamic MTD Partition support with mtdparts 806 */ 807 #ifdef CONFIG_MTD_NOR_FLASH 808 #define CONFIG_MTD_DEVICE 809 #define CONFIG_MTD_PARTITIONS 810 #define CONFIG_FLASH_CFI_MTD 811 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 812 "spi0=spife110000.0" 813 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 814 "128k(dtb),96m(fs),-(user);"\ 815 "fff800000.flash:2m(uboot),9m(kernel),"\ 816 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 817 "2m(uboot),9m(kernel),128k(dtb),-(user)" 818 #endif 819 820 /* 821 * Environment Configuration 822 */ 823 #define CONFIG_ROOTPATH "/opt/nfsroot" 824 #define CONFIG_BOOTFILE "uImage" 825 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 826 827 /* default location for tftp and bootm */ 828 #define CONFIG_LOADADDR 1000000 829 830 #define __USB_PHY_TYPE utmi 831 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 832 833 #ifdef CONFIG_TARGET_T1040RDB 834 #define FDTFILE "t1040rdb/t1040rdb.dtb" 835 #elif defined(CONFIG_TARGET_T1042RDB_PI) 836 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 837 #elif defined(CONFIG_TARGET_T1042RDB) 838 #define FDTFILE "t1042rdb/t1042rdb.dtb" 839 #elif defined(CONFIG_TARGET_T1040D4RDB) 840 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 841 #elif defined(CONFIG_TARGET_T1042D4RDB) 842 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 843 #endif 844 845 #ifdef CONFIG_FSL_DIU_FB 846 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 847 #else 848 #define DIU_ENVIRONMENT 849 #endif 850 851 #define CONFIG_EXTRA_ENV_SETTINGS \ 852 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 853 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 854 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 855 "netdev=eth0\0" \ 856 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 857 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 858 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 859 "tftpflash=tftpboot $loadaddr $uboot && " \ 860 "protect off $ubootaddr +$filesize && " \ 861 "erase $ubootaddr +$filesize && " \ 862 "cp.b $loadaddr $ubootaddr $filesize && " \ 863 "protect on $ubootaddr +$filesize && " \ 864 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 865 "consoledev=ttyS0\0" \ 866 "ramdiskaddr=2000000\0" \ 867 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 868 "fdtaddr=1e00000\0" \ 869 "fdtfile=" __stringify(FDTFILE) "\0" \ 870 "bdev=sda3\0" 871 872 #define CONFIG_LINUX \ 873 "setenv bootargs root=/dev/ram rw " \ 874 "console=$consoledev,$baudrate $othbootargs;" \ 875 "setenv ramdiskaddr 0x02000000;" \ 876 "setenv fdtaddr 0x00c00000;" \ 877 "setenv loadaddr 0x1000000;" \ 878 "bootm $loadaddr $ramdiskaddr $fdtaddr" 879 880 #define CONFIG_HDBOOT \ 881 "setenv bootargs root=/dev/$bdev rw " \ 882 "console=$consoledev,$baudrate $othbootargs;" \ 883 "tftp $loadaddr $bootfile;" \ 884 "tftp $fdtaddr $fdtfile;" \ 885 "bootm $loadaddr - $fdtaddr" 886 887 #define CONFIG_NFSBOOTCOMMAND \ 888 "setenv bootargs root=/dev/nfs rw " \ 889 "nfsroot=$serverip:$rootpath " \ 890 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 891 "console=$consoledev,$baudrate $othbootargs;" \ 892 "tftp $loadaddr $bootfile;" \ 893 "tftp $fdtaddr $fdtfile;" \ 894 "bootm $loadaddr - $fdtaddr" 895 896 #define CONFIG_RAMBOOTCOMMAND \ 897 "setenv bootargs root=/dev/ram rw " \ 898 "console=$consoledev,$baudrate $othbootargs;" \ 899 "tftp $ramdiskaddr $ramdiskfile;" \ 900 "tftp $loadaddr $bootfile;" \ 901 "tftp $fdtaddr $fdtfile;" \ 902 "bootm $loadaddr $ramdiskaddr $fdtaddr" 903 904 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 905 906 #include <asm/fsl_secure_boot.h> 907 908 #endif /* __CONFIG_H */ 909