1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 #define CONFIG_PHYS_64BIT 15 16 #ifdef CONFIG_RAMBOOT_PBL 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #endif 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 23 #define CONFIG_E500 /* BOOKE e500 family */ 24 #define CONFIG_E500MC /* BOOKE e500mc family */ 25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 26 #define CONFIG_MP /* support multiple processors */ 27 28 /* support deep sleep */ 29 #define CONFIG_DEEP_SLEEP 30 #define CONFIG_SILENT_CONSOLE 31 32 #ifndef CONFIG_SYS_TEXT_BASE 33 #define CONFIG_SYS_TEXT_BASE 0xeff40000 34 #endif 35 36 #ifndef CONFIG_RESET_VECTOR_ADDRESS 37 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 38 #endif 39 40 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 41 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 42 #define CONFIG_FSL_IFC /* Enable IFC Support */ 43 #define CONFIG_PCI /* Enable PCI/PCIE */ 44 #define CONFIG_PCI_INDIRECT_BRIDGE 45 #define CONFIG_PCIE1 /* PCIE controler 1 */ 46 #define CONFIG_PCIE2 /* PCIE controler 2 */ 47 #define CONFIG_PCIE3 /* PCIE controler 3 */ 48 #define CONFIG_PCIE4 /* PCIE controler 4 */ 49 50 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 51 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 52 53 #define CONFIG_FSL_LAW /* Use common FSL init code */ 54 55 #define CONFIG_ENV_OVERWRITE 56 57 #ifdef CONFIG_SYS_NO_FLASH 58 #define CONFIG_ENV_IS_NOWHERE 59 #else 60 #define CONFIG_FLASH_CFI_DRIVER 61 #define CONFIG_SYS_FLASH_CFI 62 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 63 #endif 64 65 #ifndef CONFIG_SYS_NO_FLASH 66 #if defined(CONFIG_SPIFLASH) 67 #define CONFIG_SYS_EXTRA_ENV_RELOC 68 #define CONFIG_ENV_IS_IN_SPI_FLASH 69 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 70 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 71 #define CONFIG_ENV_SECT_SIZE 0x10000 72 #elif defined(CONFIG_SDCARD) 73 #define CONFIG_SYS_EXTRA_ENV_RELOC 74 #define CONFIG_ENV_IS_IN_MMC 75 #define CONFIG_SYS_MMC_ENV_DEV 0 76 #define CONFIG_ENV_SIZE 0x2000 77 #define CONFIG_ENV_OFFSET (512 * 1658) 78 #elif defined(CONFIG_NAND) 79 #define CONFIG_SYS_EXTRA_ENV_RELOC 80 #define CONFIG_ENV_IS_IN_NAND 81 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 82 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 83 #else 84 #define CONFIG_ENV_IS_IN_FLASH 85 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 86 #define CONFIG_ENV_SIZE 0x2000 87 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 88 #endif 89 #else /* CONFIG_SYS_NO_FLASH */ 90 #define CONFIG_ENV_SIZE 0x2000 91 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 92 #endif 93 94 #define CONFIG_SYS_CLK_FREQ 100000000 95 #define CONFIG_DDR_CLK_FREQ 66666666 96 97 /* 98 * These can be toggled for performance analysis, otherwise use default. 99 */ 100 #define CONFIG_SYS_CACHE_STASHING 101 #define CONFIG_BACKSIDE_L2_CACHE 102 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 103 #define CONFIG_BTB /* toggle branch predition */ 104 #define CONFIG_DDR_ECC 105 #ifdef CONFIG_DDR_ECC 106 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 107 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 108 #endif 109 110 #define CONFIG_ENABLE_36BIT_PHYS 111 112 #define CONFIG_ADDR_MAP 113 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 114 115 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 116 #define CONFIG_SYS_MEMTEST_END 0x00400000 117 #define CONFIG_SYS_ALT_MEMTEST 118 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 119 120 /* 121 * Config the L3 Cache as L3 SRAM 122 */ 123 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 124 125 #define CONFIG_SYS_DCSRBAR 0xf0000000 126 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 127 128 /* 129 * DDR Setup 130 */ 131 #define CONFIG_VERY_BIG_RAM 132 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 133 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 134 135 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 136 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 137 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 138 139 #define CONFIG_DDR_SPD 140 #define CONFIG_SYS_DDR_RAW_TIMING 141 #define CONFIG_SYS_FSL_DDR3 142 143 #define CONFIG_SYS_SPD_BUS_NUM 0 144 #define SPD_EEPROM_ADDRESS 0x51 145 146 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 147 148 /* 149 * IFC Definitions 150 */ 151 #define CONFIG_SYS_FLASH_BASE 0xe8000000 152 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 153 154 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 155 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 156 CSPR_PORT_SIZE_16 | \ 157 CSPR_MSEL_NOR | \ 158 CSPR_V) 159 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 160 /* NOR Flash Timing Params */ 161 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 162 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 163 FTIM0_NOR_TEADC(0x5) | \ 164 FTIM0_NOR_TEAHC(0x5)) 165 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 166 FTIM1_NOR_TRAD_NOR(0x1A) |\ 167 FTIM1_NOR_TSEQRAD_NOR(0x13)) 168 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 169 FTIM2_NOR_TCH(0x4) | \ 170 FTIM2_NOR_TWPH(0x0E) | \ 171 FTIM2_NOR_TWP(0x1c)) 172 #define CONFIG_SYS_NOR_FTIM3 0x0 173 174 #define CONFIG_SYS_FLASH_QUIET_TEST 175 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 176 177 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 178 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 179 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 180 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 181 182 #define CONFIG_SYS_FLASH_EMPTY_INFO 183 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 184 185 /* CPLD on IFC */ 186 #define CPLD_LBMAP_MASK 0x3F 187 #define CPLD_BANK_SEL_MASK 0x07 188 #define CPLD_BANK_OVERRIDE 0x40 189 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 190 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 191 #define CPLD_LBMAP_RESET 0xFF 192 #define CPLD_LBMAP_SHIFT 0x03 193 194 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 195 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 196 #define CONFIG_SYS_CSPR2_EXT (0xf) 197 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 198 | CSPR_PORT_SIZE_8 \ 199 | CSPR_MSEL_GPCM \ 200 | CSPR_V) 201 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 202 #define CONFIG_SYS_CSOR2 0x0 203 /* CPLD Timing parameters for IFC CS2 */ 204 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 205 FTIM0_GPCM_TEADC(0x0e) | \ 206 FTIM0_GPCM_TEAHC(0x0e)) 207 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 208 FTIM1_GPCM_TRAD(0x1f)) 209 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 210 FTIM2_GPCM_TCH(0x0) | \ 211 FTIM2_GPCM_TWP(0x1f)) 212 #define CONFIG_SYS_CS2_FTIM3 0x0 213 214 /* NAND Flash on IFC */ 215 #define CONFIG_NAND_FSL_IFC 216 #define CONFIG_SYS_NAND_BASE 0xff800000 217 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 218 219 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 220 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 221 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 222 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 223 | CSPR_V) 224 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 225 226 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 227 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 228 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 229 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 230 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 231 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 232 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 233 234 #define CONFIG_SYS_NAND_ONFI_DETECTION 235 236 /* ONFI NAND Flash mode0 Timing Params */ 237 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 238 FTIM0_NAND_TWP(0x18) | \ 239 FTIM0_NAND_TWCHT(0x07) | \ 240 FTIM0_NAND_TWH(0x0a)) 241 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 242 FTIM1_NAND_TWBE(0x39) | \ 243 FTIM1_NAND_TRR(0x0e) | \ 244 FTIM1_NAND_TRP(0x18)) 245 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 246 FTIM2_NAND_TREH(0x0a) | \ 247 FTIM2_NAND_TWHRE(0x1e)) 248 #define CONFIG_SYS_NAND_FTIM3 0x0 249 250 #define CONFIG_SYS_NAND_DDR_LAW 11 251 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 252 #define CONFIG_SYS_MAX_NAND_DEVICE 1 253 #define CONFIG_MTD_NAND_VERIFY_WRITE 254 #define CONFIG_CMD_NAND 255 256 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 257 258 #if defined(CONFIG_NAND) 259 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 260 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 261 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 262 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 263 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 264 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 265 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 266 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 267 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 268 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 269 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 270 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 271 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 272 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 273 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 274 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 275 #else 276 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 277 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 278 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 279 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 280 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 281 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 282 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 283 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 284 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 285 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 286 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 287 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 288 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 289 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 290 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 291 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 292 #endif 293 294 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 295 296 #if defined(CONFIG_RAMBOOT_PBL) 297 #define CONFIG_SYS_RAMBOOT 298 #endif 299 300 #define CONFIG_BOARD_EARLY_INIT_R 301 #define CONFIG_MISC_INIT_R 302 303 #define CONFIG_HWCONFIG 304 305 /* define to use L1 as initial stack */ 306 #define CONFIG_L1_INIT_RAM 307 #define CONFIG_SYS_INIT_RAM_LOCK 308 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 311 /* The assembler doesn't like typecast */ 312 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 313 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 314 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 315 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 316 317 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 318 GENERATED_GBL_DATA_SIZE) 319 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 320 321 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 322 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 323 324 /* Serial Port - controlled on board with jumper J8 325 * open - index 2 326 * shorted - index 1 327 */ 328 #define CONFIG_CONS_INDEX 1 329 #define CONFIG_SYS_NS16550 330 #define CONFIG_SYS_NS16550_SERIAL 331 #define CONFIG_SYS_NS16550_REG_SIZE 1 332 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 333 334 #define CONFIG_SYS_BAUDRATE_TABLE \ 335 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 336 337 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 338 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 339 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 340 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 341 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 342 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 343 344 /* Use the HUSH parser */ 345 #define CONFIG_SYS_HUSH_PARSER 346 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 347 348 /* pass open firmware flat tree */ 349 #define CONFIG_OF_LIBFDT 350 #define CONFIG_OF_BOARD_SETUP 351 #define CONFIG_OF_STDOUT_VIA_ALIAS 352 353 /* new uImage format support */ 354 #define CONFIG_FIT 355 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 356 357 /* I2C */ 358 #define CONFIG_SYS_I2C 359 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 360 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 361 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 362 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 363 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 364 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 365 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 366 367 /* I2C bus multiplexer */ 368 #define I2C_MUX_PCA_ADDR 0x70 369 #ifdef CONFIG_T1040RDB 370 #define I2C_MUX_CH_DEFAULT 0x8 371 #endif 372 373 #ifdef CONFIG_T1042RDB_PI 374 /* 375 * RTC configuration 376 */ 377 #define RTC 378 #define CONFIG_RTC_DS1337 1 379 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 380 381 /*DVI encoder*/ 382 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 383 #endif 384 385 /* 386 * eSPI - Enhanced SPI 387 */ 388 #define CONFIG_FSL_ESPI 389 #define CONFIG_SPI_FLASH 390 #define CONFIG_SPI_FLASH_STMICRO 391 #define CONFIG_CMD_SF 392 #define CONFIG_SF_DEFAULT_SPEED 10000000 393 #define CONFIG_SF_DEFAULT_MODE 0 394 #define CONFIG_ENV_SPI_BUS 0 395 #define CONFIG_ENV_SPI_CS 0 396 #define CONFIG_ENV_SPI_MAX_HZ 10000000 397 #define CONFIG_ENV_SPI_MODE 0 398 399 /* 400 * General PCI 401 * Memory space is mapped 1-1, but I/O space must start from 0. 402 */ 403 404 #ifdef CONFIG_PCI 405 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 406 #ifdef CONFIG_PCIE1 407 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 408 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 409 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 410 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 411 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 412 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 413 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 414 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 415 #endif 416 417 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 418 #ifdef CONFIG_PCIE2 419 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 420 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 421 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 422 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 423 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 424 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 425 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 426 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 427 #endif 428 429 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 430 #ifdef CONFIG_PCIE3 431 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 432 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 433 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 434 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 435 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 436 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 437 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 438 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 439 #endif 440 441 /* controller 4, Base address 203000 */ 442 #ifdef CONFIG_PCIE4 443 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 444 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 445 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 446 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 447 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 448 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 449 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 450 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 451 #endif 452 453 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 454 #define CONFIG_E1000 455 456 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 457 #define CONFIG_DOS_PARTITION 458 #endif /* CONFIG_PCI */ 459 460 /* SATA */ 461 #define CONFIG_FSL_SATA_V2 462 #ifdef CONFIG_FSL_SATA_V2 463 #define CONFIG_LIBATA 464 #define CONFIG_FSL_SATA 465 466 #define CONFIG_SYS_SATA_MAX_DEVICE 1 467 #define CONFIG_SATA1 468 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 469 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 470 471 #define CONFIG_LBA48 472 #define CONFIG_CMD_SATA 473 #define CONFIG_DOS_PARTITION 474 #define CONFIG_CMD_EXT2 475 #endif 476 477 /* 478 * USB 479 */ 480 #define CONFIG_HAS_FSL_DR_USB 481 482 #ifdef CONFIG_HAS_FSL_DR_USB 483 #define CONFIG_USB_EHCI 484 485 #ifdef CONFIG_USB_EHCI 486 #define CONFIG_CMD_USB 487 #define CONFIG_USB_STORAGE 488 #define CONFIG_USB_EHCI_FSL 489 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 490 #define CONFIG_CMD_EXT2 491 #endif 492 #endif 493 494 #define CONFIG_MMC 495 496 #ifdef CONFIG_MMC 497 #define CONFIG_FSL_ESDHC 498 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 499 #define CONFIG_CMD_MMC 500 #define CONFIG_GENERIC_MMC 501 #define CONFIG_CMD_EXT2 502 #define CONFIG_CMD_FAT 503 #define CONFIG_DOS_PARTITION 504 #endif 505 506 /* Qman/Bman */ 507 #ifndef CONFIG_NOBQFMAN 508 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 509 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 510 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 511 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 512 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 513 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 514 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 515 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 516 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 517 518 #define CONFIG_SYS_DPAA_FMAN 519 #define CONFIG_SYS_DPAA_PME 520 521 #ifdef CONFIG_T1040RDB 522 #define CONFIG_QE 523 #define CONFIG_U_QE 524 #endif 525 526 /* Default address of microcode for the Linux Fman driver */ 527 #if defined(CONFIG_SPIFLASH) 528 /* 529 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 530 * env, so we got 0x110000. 531 */ 532 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 533 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 534 #elif defined(CONFIG_SDCARD) 535 /* 536 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 537 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 538 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 539 */ 540 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 541 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 542 #elif defined(CONFIG_NAND) 543 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 544 #define CONFIG_SYS_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 545 #else 546 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 547 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 548 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 549 #endif 550 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 551 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 552 #endif /* CONFIG_NOBQFMAN */ 553 554 #ifdef CONFIG_SYS_DPAA_FMAN 555 #define CONFIG_FMAN_ENET 556 #define CONFIG_PHY_VITESSE 557 #define CONFIG_PHY_REALTEK 558 #endif 559 560 #ifdef CONFIG_FMAN_ENET 561 #ifdef CONFIG_T1040RDB 562 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 563 #endif 564 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 565 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 566 567 #define CONFIG_MII /* MII PHY management */ 568 #define CONFIG_ETHPRIME "FM1@DTSEC4" 569 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 570 #endif 571 572 /* 573 * Environment 574 */ 575 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 576 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 577 578 /* 579 * Command line configuration. 580 */ 581 #include <config_cmd_default.h> 582 583 #ifdef CONFIG_T1042RDB_PI 584 #define CONFIG_CMD_DATE 585 #endif 586 #define CONFIG_CMD_DHCP 587 #define CONFIG_CMD_ELF 588 #define CONFIG_CMD_ERRATA 589 #define CONFIG_CMD_GREPENV 590 #define CONFIG_CMD_IRQ 591 #define CONFIG_CMD_I2C 592 #define CONFIG_CMD_MII 593 #define CONFIG_CMD_PING 594 #define CONFIG_CMD_REGINFO 595 #define CONFIG_CMD_SETEXPR 596 597 #ifdef CONFIG_PCI 598 #define CONFIG_CMD_PCI 599 #define CONFIG_CMD_NET 600 #endif 601 602 /* 603 * Miscellaneous configurable options 604 */ 605 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 606 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 607 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 608 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 609 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 610 #ifdef CONFIG_CMD_KGDB 611 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 612 #else 613 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 614 #endif 615 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 616 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 617 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 618 619 /* 620 * For booting Linux, the board info and command line data 621 * have to be in the first 64 MB of memory, since this is 622 * the maximum mapped by the Linux kernel during initialization. 623 */ 624 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 625 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 626 627 #ifdef CONFIG_CMD_KGDB 628 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 629 #endif 630 631 /* 632 * Dynamic MTD Partition support with mtdparts 633 */ 634 #ifndef CONFIG_SYS_NO_FLASH 635 #define CONFIG_MTD_DEVICE 636 #define CONFIG_MTD_PARTITIONS 637 #define CONFIG_CMD_MTDPARTS 638 #define CONFIG_FLASH_CFI_MTD 639 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 640 "spi0=spife110000.0" 641 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 642 "128k(dtb),96m(fs),-(user);"\ 643 "fff800000.flash:2m(uboot),9m(kernel),"\ 644 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 645 "2m(uboot),9m(kernel),128k(dtb),-(user)" 646 #endif 647 648 /* 649 * Environment Configuration 650 */ 651 #define CONFIG_ROOTPATH "/opt/nfsroot" 652 #define CONFIG_BOOTFILE "uImage" 653 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 654 655 /* default location for tftp and bootm */ 656 #define CONFIG_LOADADDR 1000000 657 658 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ 659 660 #define CONFIG_BAUDRATE 115200 661 662 #define __USB_PHY_TYPE utmi 663 664 #ifdef CONFIG_T1040RDB 665 #define FDTFILE "t1040rdb/t1040rdb.dtb" 666 #define RAMDISKFILE "t1040rdb/ramdisk.uboot" 667 #elif CONFIG_T1042RDB_PI 668 #define FDTFILE "t1040rdb_pi/t1040rdb_pi.dtb" 669 #define RAMDISKFILE "t1040rdb_pi/ramdisk.uboot" 670 #endif 671 672 #define CONFIG_EXTRA_ENV_SETTINGS \ 673 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 674 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 675 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 676 "netdev=eth0\0" \ 677 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 678 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 679 "tftpflash=tftpboot $loadaddr $uboot && " \ 680 "protect off $ubootaddr +$filesize && " \ 681 "erase $ubootaddr +$filesize && " \ 682 "cp.b $loadaddr $ubootaddr $filesize && " \ 683 "protect on $ubootaddr +$filesize && " \ 684 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 685 "consoledev=ttyS0\0" \ 686 "ramdiskaddr=2000000\0" \ 687 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 688 "fdtaddr=c00000\0" \ 689 "fdtfile=" __stringify(FDTFILE) "\0" \ 690 "bdev=sda3\0" \ 691 "c=ffe\0" 692 693 #define CONFIG_LINUX \ 694 "setenv bootargs root=/dev/ram rw " \ 695 "console=$consoledev,$baudrate $othbootargs;" \ 696 "setenv ramdiskaddr 0x02000000;" \ 697 "setenv fdtaddr 0x00c00000;" \ 698 "setenv loadaddr 0x1000000;" \ 699 "bootm $loadaddr $ramdiskaddr $fdtaddr" 700 701 #define CONFIG_HDBOOT \ 702 "setenv bootargs root=/dev/$bdev rw " \ 703 "console=$consoledev,$baudrate $othbootargs;" \ 704 "tftp $loadaddr $bootfile;" \ 705 "tftp $fdtaddr $fdtfile;" \ 706 "bootm $loadaddr - $fdtaddr" 707 708 #define CONFIG_NFSBOOTCOMMAND \ 709 "setenv bootargs root=/dev/nfs rw " \ 710 "nfsroot=$serverip:$rootpath " \ 711 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 712 "console=$consoledev,$baudrate $othbootargs;" \ 713 "tftp $loadaddr $bootfile;" \ 714 "tftp $fdtaddr $fdtfile;" \ 715 "bootm $loadaddr - $fdtaddr" 716 717 #define CONFIG_RAMBOOTCOMMAND \ 718 "setenv bootargs root=/dev/ram rw " \ 719 "console=$consoledev,$baudrate $othbootargs;" \ 720 "tftp $ramdiskaddr $ramdiskfile;" \ 721 "tftp $loadaddr $bootfile;" \ 722 "tftp $fdtaddr $fdtfile;" \ 723 "bootm $loadaddr $ramdiskaddr $fdtaddr" 724 725 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 726 727 #ifdef CONFIG_SECURE_BOOT 728 #include <asm/fsl_secure_boot.h> 729 #endif 730 731 #endif /* __CONFIG_H */ 732