1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 #define CONFIG_T1040QDS 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 35 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 36 #endif 37 38 /* High Level Configuration Options */ 39 #define CONFIG_BOOKE 40 #define CONFIG_E500 /* BOOKE e500 family */ 41 #define CONFIG_E500MC /* BOOKE e500mc family */ 42 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 43 #define CONFIG_MP /* support multiple processors */ 44 45 /* support deep sleep */ 46 #define CONFIG_DEEP_SLEEP 47 #if defined(CONFIG_DEEP_SLEEP) 48 #define CONFIG_BOARD_EARLY_INIT_F 49 #endif 50 51 #ifndef CONFIG_SYS_TEXT_BASE 52 #define CONFIG_SYS_TEXT_BASE 0xeff40000 53 #endif 54 55 #ifndef CONFIG_RESET_VECTOR_ADDRESS 56 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 57 #endif 58 59 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 60 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 61 #define CONFIG_FSL_IFC /* Enable IFC Support */ 62 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 63 #define CONFIG_PCI /* Enable PCI/PCIE */ 64 #define CONFIG_PCI_INDIRECT_BRIDGE 65 #define CONFIG_PCIE1 /* PCIE controller 1 */ 66 #define CONFIG_PCIE2 /* PCIE controller 2 */ 67 #define CONFIG_PCIE3 /* PCIE controller 3 */ 68 #define CONFIG_PCIE4 /* PCIE controller 4 */ 69 70 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 71 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 72 73 #define CONFIG_FSL_LAW /* Use common FSL init code */ 74 75 #define CONFIG_ENV_OVERWRITE 76 77 #ifdef CONFIG_SYS_NO_FLASH 78 #define CONFIG_ENV_IS_NOWHERE 79 #else 80 #define CONFIG_FLASH_CFI_DRIVER 81 #define CONFIG_SYS_FLASH_CFI 82 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 83 #endif 84 85 #ifndef CONFIG_SYS_NO_FLASH 86 #if defined(CONFIG_SPIFLASH) 87 #define CONFIG_SYS_EXTRA_ENV_RELOC 88 #define CONFIG_ENV_IS_IN_SPI_FLASH 89 #define CONFIG_ENV_SPI_BUS 0 90 #define CONFIG_ENV_SPI_CS 0 91 #define CONFIG_ENV_SPI_MAX_HZ 10000000 92 #define CONFIG_ENV_SPI_MODE 0 93 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 94 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 95 #define CONFIG_ENV_SECT_SIZE 0x10000 96 #elif defined(CONFIG_SDCARD) 97 #define CONFIG_SYS_EXTRA_ENV_RELOC 98 #define CONFIG_ENV_IS_IN_MMC 99 #define CONFIG_SYS_MMC_ENV_DEV 0 100 #define CONFIG_ENV_SIZE 0x2000 101 #define CONFIG_ENV_OFFSET (512 * 1658) 102 #elif defined(CONFIG_NAND) 103 #define CONFIG_SYS_EXTRA_ENV_RELOC 104 #define CONFIG_ENV_IS_IN_NAND 105 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 106 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 107 #else 108 #define CONFIG_ENV_IS_IN_FLASH 109 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 110 #define CONFIG_ENV_SIZE 0x2000 111 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 112 #endif 113 #else /* CONFIG_SYS_NO_FLASH */ 114 #define CONFIG_ENV_SIZE 0x2000 115 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 116 #endif 117 118 #ifndef __ASSEMBLY__ 119 unsigned long get_board_sys_clk(void); 120 unsigned long get_board_ddr_clk(void); 121 #endif 122 123 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 124 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 125 126 /* 127 * These can be toggled for performance analysis, otherwise use default. 128 */ 129 #define CONFIG_SYS_CACHE_STASHING 130 #define CONFIG_BACKSIDE_L2_CACHE 131 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 132 #define CONFIG_BTB /* toggle branch predition */ 133 #define CONFIG_DDR_ECC 134 #ifdef CONFIG_DDR_ECC 135 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 136 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 137 #endif 138 139 #define CONFIG_ENABLE_36BIT_PHYS 140 141 #define CONFIG_ADDR_MAP 142 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 143 144 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 145 #define CONFIG_SYS_MEMTEST_END 0x00400000 146 #define CONFIG_SYS_ALT_MEMTEST 147 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 148 149 /* 150 * Config the L3 Cache as L3 SRAM 151 */ 152 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 153 154 #define CONFIG_SYS_DCSRBAR 0xf0000000 155 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 156 157 /* EEPROM */ 158 #define CONFIG_ID_EEPROM 159 #define CONFIG_SYS_I2C_EEPROM_NXID 160 #define CONFIG_SYS_EEPROM_BUS_NUM 0 161 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 162 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 163 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 164 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 165 166 /* 167 * DDR Setup 168 */ 169 #define CONFIG_VERY_BIG_RAM 170 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 171 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 172 173 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 174 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 175 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 176 177 #define CONFIG_DDR_SPD 178 #ifndef CONFIG_SYS_FSL_DDR4 179 #define CONFIG_SYS_FSL_DDR3 180 #endif 181 #define CONFIG_FSL_DDR_INTERACTIVE 182 183 #define CONFIG_SYS_SPD_BUS_NUM 0 184 #define SPD_EEPROM_ADDRESS 0x51 185 186 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 187 188 /* 189 * IFC Definitions 190 */ 191 #define CONFIG_SYS_FLASH_BASE 0xe0000000 192 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 193 194 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 195 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 196 + 0x8000000) | \ 197 CSPR_PORT_SIZE_16 | \ 198 CSPR_MSEL_NOR | \ 199 CSPR_V) 200 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 201 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 202 CSPR_PORT_SIZE_16 | \ 203 CSPR_MSEL_NOR | \ 204 CSPR_V) 205 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 206 207 /* 208 * TDM Definition 209 */ 210 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 211 212 /* NOR Flash Timing Params */ 213 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 214 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 215 FTIM0_NOR_TEADC(0x5) | \ 216 FTIM0_NOR_TEAHC(0x5)) 217 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 218 FTIM1_NOR_TRAD_NOR(0x1A) |\ 219 FTIM1_NOR_TSEQRAD_NOR(0x13)) 220 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 221 FTIM2_NOR_TCH(0x4) | \ 222 FTIM2_NOR_TWPH(0x0E) | \ 223 FTIM2_NOR_TWP(0x1c)) 224 #define CONFIG_SYS_NOR_FTIM3 0x0 225 226 #define CONFIG_SYS_FLASH_QUIET_TEST 227 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 228 229 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 230 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 231 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 232 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 233 234 #define CONFIG_SYS_FLASH_EMPTY_INFO 235 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 236 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 237 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 238 #define QIXIS_BASE 0xffdf0000 239 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 240 #define QIXIS_LBMAP_SWITCH 0x06 241 #define QIXIS_LBMAP_MASK 0x0f 242 #define QIXIS_LBMAP_SHIFT 0 243 #define QIXIS_LBMAP_DFLTBANK 0x00 244 #define QIXIS_LBMAP_ALTBANK 0x04 245 #define QIXIS_RST_CTL_RESET 0x31 246 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 247 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 248 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 249 #define QIXIS_RST_FORCE_MEM 0x01 250 251 #define CONFIG_SYS_CSPR3_EXT (0xf) 252 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 253 | CSPR_PORT_SIZE_8 \ 254 | CSPR_MSEL_GPCM \ 255 | CSPR_V) 256 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 257 #define CONFIG_SYS_CSOR3 0x0 258 /* QIXIS Timing parameters for IFC CS3 */ 259 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 260 FTIM0_GPCM_TEADC(0x0e) | \ 261 FTIM0_GPCM_TEAHC(0x0e)) 262 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 263 FTIM1_GPCM_TRAD(0x3f)) 264 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 265 FTIM2_GPCM_TCH(0x8) | \ 266 FTIM2_GPCM_TWP(0x1f)) 267 #define CONFIG_SYS_CS3_FTIM3 0x0 268 269 #define CONFIG_NAND_FSL_IFC 270 #define CONFIG_SYS_NAND_BASE 0xff800000 271 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 272 273 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 274 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 275 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 276 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 277 | CSPR_V) 278 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 279 280 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 281 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 282 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 283 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 284 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 285 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 286 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 287 288 #define CONFIG_SYS_NAND_ONFI_DETECTION 289 290 /* ONFI NAND Flash mode0 Timing Params */ 291 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 292 FTIM0_NAND_TWP(0x18) | \ 293 FTIM0_NAND_TWCHT(0x07) | \ 294 FTIM0_NAND_TWH(0x0a)) 295 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 296 FTIM1_NAND_TWBE(0x39) | \ 297 FTIM1_NAND_TRR(0x0e) | \ 298 FTIM1_NAND_TRP(0x18)) 299 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 300 FTIM2_NAND_TREH(0x0a) | \ 301 FTIM2_NAND_TWHRE(0x1e)) 302 #define CONFIG_SYS_NAND_FTIM3 0x0 303 304 #define CONFIG_SYS_NAND_DDR_LAW 11 305 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 306 #define CONFIG_SYS_MAX_NAND_DEVICE 1 307 #define CONFIG_CMD_NAND 308 309 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 310 311 #if defined(CONFIG_NAND) 312 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 313 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 314 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 315 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 316 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 317 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 318 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 319 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 320 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 321 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 322 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 323 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 324 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 325 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 326 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 327 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 328 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 329 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 330 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 331 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 332 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 333 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 334 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 335 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 336 #else 337 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 338 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 339 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 340 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 341 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 342 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 343 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 344 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 345 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 346 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 347 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 348 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 349 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 350 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 351 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 352 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 353 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 354 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 355 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 356 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 357 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 358 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 359 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 360 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 361 #endif 362 363 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 364 365 #if defined(CONFIG_RAMBOOT_PBL) 366 #define CONFIG_SYS_RAMBOOT 367 #endif 368 369 #define CONFIG_BOARD_EARLY_INIT_R 370 #define CONFIG_MISC_INIT_R 371 372 #define CONFIG_HWCONFIG 373 374 /* define to use L1 as initial stack */ 375 #define CONFIG_L1_INIT_RAM 376 #define CONFIG_SYS_INIT_RAM_LOCK 377 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 378 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 379 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 380 /* The assembler doesn't like typecast */ 381 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 382 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 383 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 384 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 385 386 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 387 GENERATED_GBL_DATA_SIZE) 388 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 389 390 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 391 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 392 393 /* Serial Port - controlled on board with jumper J8 394 * open - index 2 395 * shorted - index 1 396 */ 397 #define CONFIG_CONS_INDEX 1 398 #define CONFIG_SYS_NS16550_SERIAL 399 #define CONFIG_SYS_NS16550_REG_SIZE 1 400 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 401 402 #define CONFIG_SYS_BAUDRATE_TABLE \ 403 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 404 405 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 406 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 407 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 408 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 409 410 /* Video */ 411 #define CONFIG_FSL_DIU_FB 412 #ifdef CONFIG_FSL_DIU_FB 413 #define CONFIG_FSL_DIU_CH7301 414 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 415 #define CONFIG_CMD_BMP 416 #define CONFIG_VIDEO_SW_CURSOR 417 #define CONFIG_VGA_AS_SINGLE_DEVICE 418 #define CONFIG_VIDEO_LOGO 419 #define CONFIG_VIDEO_BMP_LOGO 420 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 421 /* 422 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 423 * disable empty flash sector detection, which is I/O-intensive. 424 */ 425 #undef CONFIG_SYS_FLASH_EMPTY_INFO 426 #endif 427 428 /* I2C */ 429 #define CONFIG_SYS_I2C 430 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 431 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 432 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 433 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 434 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 435 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 436 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 437 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 438 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 439 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 440 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 441 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 442 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 443 444 #define I2C_MUX_PCA_ADDR 0x77 445 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 446 447 /* I2C bus multiplexer */ 448 #define I2C_MUX_CH_DEFAULT 0x8 449 #define I2C_MUX_CH_DIU 0xC 450 451 /* LDI/DVI Encoder for display */ 452 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 453 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 454 455 /* 456 * RTC configuration 457 */ 458 #define RTC 459 #define CONFIG_RTC_DS3231 1 460 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 461 462 /* 463 * eSPI - Enhanced SPI 464 */ 465 #define CONFIG_SF_DEFAULT_SPEED 10000000 466 #define CONFIG_SF_DEFAULT_MODE 0 467 468 /* 469 * General PCI 470 * Memory space is mapped 1-1, but I/O space must start from 0. 471 */ 472 473 #ifdef CONFIG_PCI 474 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 475 #ifdef CONFIG_PCIE1 476 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 477 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 478 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 479 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 480 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 481 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 482 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 483 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 484 #endif 485 486 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 487 #ifdef CONFIG_PCIE2 488 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 489 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 490 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 491 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 492 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 493 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 494 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 495 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 496 #endif 497 498 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 499 #ifdef CONFIG_PCIE3 500 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 501 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 502 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 503 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 504 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 505 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 506 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 507 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 508 #endif 509 510 /* controller 4, Base address 203000 */ 511 #ifdef CONFIG_PCIE4 512 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 513 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 514 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 515 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 516 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 517 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 518 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 519 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 520 #endif 521 522 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 523 524 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 525 #define CONFIG_DOS_PARTITION 526 #endif /* CONFIG_PCI */ 527 528 /* SATA */ 529 #define CONFIG_FSL_SATA_V2 530 #ifdef CONFIG_FSL_SATA_V2 531 #define CONFIG_LIBATA 532 #define CONFIG_FSL_SATA 533 534 #define CONFIG_SYS_SATA_MAX_DEVICE 2 535 #define CONFIG_SATA1 536 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 537 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 538 #define CONFIG_SATA2 539 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 540 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 541 542 #define CONFIG_LBA48 543 #define CONFIG_CMD_SATA 544 #define CONFIG_DOS_PARTITION 545 #endif 546 547 /* 548 * USB 549 */ 550 #define CONFIG_HAS_FSL_DR_USB 551 552 #ifdef CONFIG_HAS_FSL_DR_USB 553 #define CONFIG_USB_EHCI 554 555 #ifdef CONFIG_USB_EHCI 556 #define CONFIG_USB_EHCI_FSL 557 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 558 #endif 559 #endif 560 561 #define CONFIG_MMC 562 563 #ifdef CONFIG_MMC 564 #define CONFIG_FSL_ESDHC 565 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 566 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 567 #define CONFIG_GENERIC_MMC 568 #define CONFIG_DOS_PARTITION 569 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 570 #endif 571 572 /* Qman/Bman */ 573 #ifndef CONFIG_NOBQFMAN 574 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 575 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 576 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 577 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 578 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 579 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 580 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 581 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 582 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 583 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 584 CONFIG_SYS_BMAN_CENA_SIZE) 585 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 586 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 587 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 588 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 589 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 590 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 591 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 592 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 593 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 594 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 595 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 596 CONFIG_SYS_QMAN_CENA_SIZE) 597 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 598 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 599 600 #define CONFIG_SYS_DPAA_FMAN 601 #define CONFIG_SYS_DPAA_PME 602 603 #define CONFIG_QE 604 #define CONFIG_U_QE 605 /* Default address of microcode for the Linux Fman driver */ 606 #if defined(CONFIG_SPIFLASH) 607 /* 608 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 609 * env, so we got 0x110000. 610 */ 611 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 612 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 613 #elif defined(CONFIG_SDCARD) 614 /* 615 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 616 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 617 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 618 */ 619 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 620 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 621 #elif defined(CONFIG_NAND) 622 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 623 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 624 #else 625 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 626 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 627 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 628 #endif 629 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 630 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 631 #endif /* CONFIG_NOBQFMAN */ 632 633 #ifdef CONFIG_SYS_DPAA_FMAN 634 #define CONFIG_FMAN_ENET 635 #define CONFIG_PHYLIB_10G 636 #define CONFIG_PHY_VITESSE 637 #define CONFIG_PHY_REALTEK 638 #define CONFIG_PHY_TERANETICS 639 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 640 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 641 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 642 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 643 #endif 644 645 #ifdef CONFIG_FMAN_ENET 646 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 647 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 648 649 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 650 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 651 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 652 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 653 654 #define CONFIG_MII /* MII PHY management */ 655 #define CONFIG_ETHPRIME "FM1@DTSEC1" 656 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 657 #endif 658 659 /* Enable VSC9953 L2 Switch driver */ 660 #define CONFIG_VSC9953 661 #define CONFIG_CMD_ETHSW 662 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 663 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 664 665 /* 666 * Dynamic MTD Partition support with mtdparts 667 */ 668 #ifndef CONFIG_SYS_NO_FLASH 669 #define CONFIG_MTD_DEVICE 670 #define CONFIG_MTD_PARTITIONS 671 #define CONFIG_CMD_MTDPARTS 672 #define CONFIG_FLASH_CFI_MTD 673 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 674 "spi0=spife110000.0" 675 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 676 "128k(dtb),96m(fs),-(user);"\ 677 "fff800000.flash:2m(uboot),9m(kernel),"\ 678 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 679 "2m(uboot),9m(kernel),128k(dtb),-(user)" 680 #endif 681 682 /* 683 * Environment 684 */ 685 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 686 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 687 688 /* 689 * Command line configuration. 690 */ 691 #define CONFIG_CMD_DATE 692 #define CONFIG_CMD_EEPROM 693 #define CONFIG_CMD_ERRATA 694 #define CONFIG_CMD_IRQ 695 #define CONFIG_CMD_REGINFO 696 697 #ifdef CONFIG_PCI 698 #define CONFIG_CMD_PCI 699 #endif 700 701 /* Hash command with SHA acceleration supported in hardware */ 702 #ifdef CONFIG_FSL_CAAM 703 #define CONFIG_CMD_HASH 704 #define CONFIG_SHA_HW_ACCEL 705 #endif 706 707 /* 708 * Miscellaneous configurable options 709 */ 710 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 711 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 712 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 713 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 714 #ifdef CONFIG_CMD_KGDB 715 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 716 #else 717 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 718 #endif 719 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 720 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 721 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 722 723 /* 724 * For booting Linux, the board info and command line data 725 * have to be in the first 64 MB of memory, since this is 726 * the maximum mapped by the Linux kernel during initialization. 727 */ 728 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 729 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 730 731 #ifdef CONFIG_CMD_KGDB 732 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 733 #endif 734 735 /* 736 * Environment Configuration 737 */ 738 #define CONFIG_ROOTPATH "/opt/nfsroot" 739 #define CONFIG_BOOTFILE "uImage" 740 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 741 742 /* default location for tftp and bootm */ 743 #define CONFIG_LOADADDR 1000000 744 745 746 #define CONFIG_BAUDRATE 115200 747 748 #define __USB_PHY_TYPE utmi 749 750 #define CONFIG_EXTRA_ENV_SETTINGS \ 751 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 752 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 753 "netdev=eth0\0" \ 754 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 755 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 756 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 757 "tftpflash=tftpboot $loadaddr $uboot && " \ 758 "protect off $ubootaddr +$filesize && " \ 759 "erase $ubootaddr +$filesize && " \ 760 "cp.b $loadaddr $ubootaddr $filesize && " \ 761 "protect on $ubootaddr +$filesize && " \ 762 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 763 "consoledev=ttyS0\0" \ 764 "ramdiskaddr=2000000\0" \ 765 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 766 "fdtaddr=1e00000\0" \ 767 "fdtfile=t1040qds/t1040qds.dtb\0" \ 768 "bdev=sda3\0" 769 770 #define CONFIG_LINUX \ 771 "setenv bootargs root=/dev/ram rw " \ 772 "console=$consoledev,$baudrate $othbootargs;" \ 773 "setenv ramdiskaddr 0x02000000;" \ 774 "setenv fdtaddr 0x00c00000;" \ 775 "setenv loadaddr 0x1000000;" \ 776 "bootm $loadaddr $ramdiskaddr $fdtaddr" 777 778 #define CONFIG_HDBOOT \ 779 "setenv bootargs root=/dev/$bdev rw " \ 780 "console=$consoledev,$baudrate $othbootargs;" \ 781 "tftp $loadaddr $bootfile;" \ 782 "tftp $fdtaddr $fdtfile;" \ 783 "bootm $loadaddr - $fdtaddr" 784 785 #define CONFIG_NFSBOOTCOMMAND \ 786 "setenv bootargs root=/dev/nfs rw " \ 787 "nfsroot=$serverip:$rootpath " \ 788 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 789 "console=$consoledev,$baudrate $othbootargs;" \ 790 "tftp $loadaddr $bootfile;" \ 791 "tftp $fdtaddr $fdtfile;" \ 792 "bootm $loadaddr - $fdtaddr" 793 794 #define CONFIG_RAMBOOTCOMMAND \ 795 "setenv bootargs root=/dev/ram rw " \ 796 "console=$consoledev,$baudrate $othbootargs;" \ 797 "tftp $ramdiskaddr $ramdiskfile;" \ 798 "tftp $loadaddr $bootfile;" \ 799 "tftp $fdtaddr $fdtfile;" \ 800 "bootm $loadaddr $ramdiskaddr $fdtaddr" 801 802 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 803 804 #include <asm/fsl_secure_boot.h> 805 806 #endif /* __CONFIG_H */ 807