1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 30 #ifdef CONFIG_RAMBOOT_PBL 31 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 39 #define CONFIG_MP /* support multiple processors */ 40 41 /* support deep sleep */ 42 #define CONFIG_DEEP_SLEEP 43 #if defined(CONFIG_DEEP_SLEEP) 44 #define CONFIG_BOARD_EARLY_INIT_F 45 #endif 46 47 #ifndef CONFIG_SYS_TEXT_BASE 48 #define CONFIG_SYS_TEXT_BASE 0xeff40000 49 #endif 50 51 #ifndef CONFIG_RESET_VECTOR_ADDRESS 52 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 53 #endif 54 55 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 56 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 57 #define CONFIG_FSL_IFC /* Enable IFC Support */ 58 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 59 #define CONFIG_PCI_INDIRECT_BRIDGE 60 #define CONFIG_PCIE1 /* PCIE controller 1 */ 61 #define CONFIG_PCIE2 /* PCIE controller 2 */ 62 #define CONFIG_PCIE3 /* PCIE controller 3 */ 63 #define CONFIG_PCIE4 /* PCIE controller 4 */ 64 65 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 66 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 67 68 #define CONFIG_ENV_OVERWRITE 69 70 #ifdef CONFIG_SYS_NO_FLASH 71 #define CONFIG_ENV_IS_NOWHERE 72 #else 73 #define CONFIG_FLASH_CFI_DRIVER 74 #define CONFIG_SYS_FLASH_CFI 75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 76 #endif 77 78 #ifndef CONFIG_SYS_NO_FLASH 79 #if defined(CONFIG_SPIFLASH) 80 #define CONFIG_SYS_EXTRA_ENV_RELOC 81 #define CONFIG_ENV_IS_IN_SPI_FLASH 82 #define CONFIG_ENV_SPI_BUS 0 83 #define CONFIG_ENV_SPI_CS 0 84 #define CONFIG_ENV_SPI_MAX_HZ 10000000 85 #define CONFIG_ENV_SPI_MODE 0 86 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 87 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 88 #define CONFIG_ENV_SECT_SIZE 0x10000 89 #elif defined(CONFIG_SDCARD) 90 #define CONFIG_SYS_EXTRA_ENV_RELOC 91 #define CONFIG_ENV_IS_IN_MMC 92 #define CONFIG_SYS_MMC_ENV_DEV 0 93 #define CONFIG_ENV_SIZE 0x2000 94 #define CONFIG_ENV_OFFSET (512 * 1658) 95 #elif defined(CONFIG_NAND) 96 #define CONFIG_SYS_EXTRA_ENV_RELOC 97 #define CONFIG_ENV_IS_IN_NAND 98 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 99 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 100 #else 101 #define CONFIG_ENV_IS_IN_FLASH 102 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 103 #define CONFIG_ENV_SIZE 0x2000 104 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 105 #endif 106 #else /* CONFIG_SYS_NO_FLASH */ 107 #define CONFIG_ENV_SIZE 0x2000 108 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 109 #endif 110 111 #ifndef __ASSEMBLY__ 112 unsigned long get_board_sys_clk(void); 113 unsigned long get_board_ddr_clk(void); 114 #endif 115 116 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 117 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 118 119 /* 120 * These can be toggled for performance analysis, otherwise use default. 121 */ 122 #define CONFIG_SYS_CACHE_STASHING 123 #define CONFIG_BACKSIDE_L2_CACHE 124 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 125 #define CONFIG_BTB /* toggle branch predition */ 126 #define CONFIG_DDR_ECC 127 #ifdef CONFIG_DDR_ECC 128 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 129 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 130 #endif 131 132 #define CONFIG_ENABLE_36BIT_PHYS 133 134 #define CONFIG_ADDR_MAP 135 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 136 137 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 138 #define CONFIG_SYS_MEMTEST_END 0x00400000 139 #define CONFIG_SYS_ALT_MEMTEST 140 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 141 142 /* 143 * Config the L3 Cache as L3 SRAM 144 */ 145 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 146 147 #define CONFIG_SYS_DCSRBAR 0xf0000000 148 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 149 150 /* EEPROM */ 151 #define CONFIG_ID_EEPROM 152 #define CONFIG_SYS_I2C_EEPROM_NXID 153 #define CONFIG_SYS_EEPROM_BUS_NUM 0 154 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 156 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 157 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 158 159 /* 160 * DDR Setup 161 */ 162 #define CONFIG_VERY_BIG_RAM 163 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 164 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 165 166 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 167 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 168 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 169 170 #define CONFIG_DDR_SPD 171 #ifndef CONFIG_SYS_FSL_DDR4 172 #define CONFIG_SYS_FSL_DDR3 173 #endif 174 #define CONFIG_FSL_DDR_INTERACTIVE 175 176 #define CONFIG_SYS_SPD_BUS_NUM 0 177 #define SPD_EEPROM_ADDRESS 0x51 178 179 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 180 181 /* 182 * IFC Definitions 183 */ 184 #define CONFIG_SYS_FLASH_BASE 0xe0000000 185 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 186 187 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 188 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 189 + 0x8000000) | \ 190 CSPR_PORT_SIZE_16 | \ 191 CSPR_MSEL_NOR | \ 192 CSPR_V) 193 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 194 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 195 CSPR_PORT_SIZE_16 | \ 196 CSPR_MSEL_NOR | \ 197 CSPR_V) 198 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 199 200 /* 201 * TDM Definition 202 */ 203 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 204 205 /* NOR Flash Timing Params */ 206 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 207 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 208 FTIM0_NOR_TEADC(0x5) | \ 209 FTIM0_NOR_TEAHC(0x5)) 210 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 211 FTIM1_NOR_TRAD_NOR(0x1A) |\ 212 FTIM1_NOR_TSEQRAD_NOR(0x13)) 213 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 214 FTIM2_NOR_TCH(0x4) | \ 215 FTIM2_NOR_TWPH(0x0E) | \ 216 FTIM2_NOR_TWP(0x1c)) 217 #define CONFIG_SYS_NOR_FTIM3 0x0 218 219 #define CONFIG_SYS_FLASH_QUIET_TEST 220 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 221 222 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 223 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 224 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 225 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 226 227 #define CONFIG_SYS_FLASH_EMPTY_INFO 228 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 229 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 230 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 231 #define QIXIS_BASE 0xffdf0000 232 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 233 #define QIXIS_LBMAP_SWITCH 0x06 234 #define QIXIS_LBMAP_MASK 0x0f 235 #define QIXIS_LBMAP_SHIFT 0 236 #define QIXIS_LBMAP_DFLTBANK 0x00 237 #define QIXIS_LBMAP_ALTBANK 0x04 238 #define QIXIS_RST_CTL_RESET 0x31 239 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 240 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 241 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 242 #define QIXIS_RST_FORCE_MEM 0x01 243 244 #define CONFIG_SYS_CSPR3_EXT (0xf) 245 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 246 | CSPR_PORT_SIZE_8 \ 247 | CSPR_MSEL_GPCM \ 248 | CSPR_V) 249 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 250 #define CONFIG_SYS_CSOR3 0x0 251 /* QIXIS Timing parameters for IFC CS3 */ 252 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 253 FTIM0_GPCM_TEADC(0x0e) | \ 254 FTIM0_GPCM_TEAHC(0x0e)) 255 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 256 FTIM1_GPCM_TRAD(0x3f)) 257 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 258 FTIM2_GPCM_TCH(0x8) | \ 259 FTIM2_GPCM_TWP(0x1f)) 260 #define CONFIG_SYS_CS3_FTIM3 0x0 261 262 #define CONFIG_NAND_FSL_IFC 263 #define CONFIG_SYS_NAND_BASE 0xff800000 264 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 265 266 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 267 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 268 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 269 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 270 | CSPR_V) 271 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 272 273 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 274 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 275 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 276 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 277 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 278 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 279 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 280 281 #define CONFIG_SYS_NAND_ONFI_DETECTION 282 283 /* ONFI NAND Flash mode0 Timing Params */ 284 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 285 FTIM0_NAND_TWP(0x18) | \ 286 FTIM0_NAND_TWCHT(0x07) | \ 287 FTIM0_NAND_TWH(0x0a)) 288 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 289 FTIM1_NAND_TWBE(0x39) | \ 290 FTIM1_NAND_TRR(0x0e) | \ 291 FTIM1_NAND_TRP(0x18)) 292 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 293 FTIM2_NAND_TREH(0x0a) | \ 294 FTIM2_NAND_TWHRE(0x1e)) 295 #define CONFIG_SYS_NAND_FTIM3 0x0 296 297 #define CONFIG_SYS_NAND_DDR_LAW 11 298 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 299 #define CONFIG_SYS_MAX_NAND_DEVICE 1 300 #define CONFIG_CMD_NAND 301 302 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 303 304 #if defined(CONFIG_NAND) 305 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 306 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 307 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 308 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 309 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 310 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 311 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 312 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 313 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 314 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 315 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 316 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 317 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 318 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 319 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 320 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 321 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 322 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 323 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 324 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 325 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 326 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 327 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 328 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 329 #else 330 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 331 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 332 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 333 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 334 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 335 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 336 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 337 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 338 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 339 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 340 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 341 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 342 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 343 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 344 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 345 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 346 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 347 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 348 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 349 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 350 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 351 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 352 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 353 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 354 #endif 355 356 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 357 358 #if defined(CONFIG_RAMBOOT_PBL) 359 #define CONFIG_SYS_RAMBOOT 360 #endif 361 362 #define CONFIG_BOARD_EARLY_INIT_R 363 #define CONFIG_MISC_INIT_R 364 365 #define CONFIG_HWCONFIG 366 367 /* define to use L1 as initial stack */ 368 #define CONFIG_L1_INIT_RAM 369 #define CONFIG_SYS_INIT_RAM_LOCK 370 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 371 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 372 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 373 /* The assembler doesn't like typecast */ 374 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 375 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 376 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 377 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 378 379 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 380 GENERATED_GBL_DATA_SIZE) 381 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 382 383 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 384 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 385 386 /* Serial Port - controlled on board with jumper J8 387 * open - index 2 388 * shorted - index 1 389 */ 390 #define CONFIG_CONS_INDEX 1 391 #define CONFIG_SYS_NS16550_SERIAL 392 #define CONFIG_SYS_NS16550_REG_SIZE 1 393 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 394 395 #define CONFIG_SYS_BAUDRATE_TABLE \ 396 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 397 398 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 399 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 400 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 401 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 402 403 /* Video */ 404 #define CONFIG_FSL_DIU_FB 405 #ifdef CONFIG_FSL_DIU_FB 406 #define CONFIG_FSL_DIU_CH7301 407 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 408 #define CONFIG_CMD_BMP 409 #define CONFIG_VIDEO_LOGO 410 #define CONFIG_VIDEO_BMP_LOGO 411 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 412 /* 413 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 414 * disable empty flash sector detection, which is I/O-intensive. 415 */ 416 #undef CONFIG_SYS_FLASH_EMPTY_INFO 417 #endif 418 419 /* I2C */ 420 #define CONFIG_SYS_I2C 421 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 422 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 423 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 424 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 425 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 426 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 427 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 428 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 429 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 430 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 431 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 432 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 433 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 434 435 #define I2C_MUX_PCA_ADDR 0x77 436 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 437 438 /* I2C bus multiplexer */ 439 #define I2C_MUX_CH_DEFAULT 0x8 440 #define I2C_MUX_CH_DIU 0xC 441 442 /* LDI/DVI Encoder for display */ 443 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 444 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 445 446 /* 447 * RTC configuration 448 */ 449 #define RTC 450 #define CONFIG_RTC_DS3231 1 451 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 452 453 /* 454 * eSPI - Enhanced SPI 455 */ 456 #define CONFIG_SF_DEFAULT_SPEED 10000000 457 #define CONFIG_SF_DEFAULT_MODE 0 458 459 /* 460 * General PCI 461 * Memory space is mapped 1-1, but I/O space must start from 0. 462 */ 463 464 #ifdef CONFIG_PCI 465 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 466 #ifdef CONFIG_PCIE1 467 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 468 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 469 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 470 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 471 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 472 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 473 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 474 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 475 #endif 476 477 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 478 #ifdef CONFIG_PCIE2 479 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 480 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 481 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 482 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 483 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 484 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 485 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 486 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 487 #endif 488 489 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 490 #ifdef CONFIG_PCIE3 491 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 492 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 493 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 494 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 495 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 496 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 497 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 498 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 499 #endif 500 501 /* controller 4, Base address 203000 */ 502 #ifdef CONFIG_PCIE4 503 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 504 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 505 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 506 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 507 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 508 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 509 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 510 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 511 #endif 512 513 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 514 #define CONFIG_DOS_PARTITION 515 #endif /* CONFIG_PCI */ 516 517 /* SATA */ 518 #define CONFIG_FSL_SATA_V2 519 #ifdef CONFIG_FSL_SATA_V2 520 #define CONFIG_LIBATA 521 #define CONFIG_FSL_SATA 522 523 #define CONFIG_SYS_SATA_MAX_DEVICE 2 524 #define CONFIG_SATA1 525 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 526 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 527 #define CONFIG_SATA2 528 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 529 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 530 531 #define CONFIG_LBA48 532 #define CONFIG_CMD_SATA 533 #define CONFIG_DOS_PARTITION 534 #endif 535 536 /* 537 * USB 538 */ 539 #define CONFIG_HAS_FSL_DR_USB 540 541 #ifdef CONFIG_HAS_FSL_DR_USB 542 #define CONFIG_USB_EHCI 543 544 #ifdef CONFIG_USB_EHCI 545 #define CONFIG_USB_EHCI_FSL 546 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 547 #endif 548 #endif 549 550 #ifdef CONFIG_MMC 551 #define CONFIG_FSL_ESDHC 552 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 553 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 554 #define CONFIG_GENERIC_MMC 555 #define CONFIG_DOS_PARTITION 556 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 557 #endif 558 559 /* Qman/Bman */ 560 #ifndef CONFIG_NOBQFMAN 561 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 562 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 563 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 564 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 565 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 566 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 567 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 568 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 569 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 570 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 571 CONFIG_SYS_BMAN_CENA_SIZE) 572 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 573 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 574 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 575 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 576 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 577 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 578 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 579 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 580 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 581 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 582 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 583 CONFIG_SYS_QMAN_CENA_SIZE) 584 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 585 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 586 587 #define CONFIG_SYS_DPAA_FMAN 588 #define CONFIG_SYS_DPAA_PME 589 590 #define CONFIG_QE 591 #define CONFIG_U_QE 592 /* Default address of microcode for the Linux Fman driver */ 593 #if defined(CONFIG_SPIFLASH) 594 /* 595 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 596 * env, so we got 0x110000. 597 */ 598 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 599 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 600 #elif defined(CONFIG_SDCARD) 601 /* 602 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 603 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 604 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 605 */ 606 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 607 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 608 #elif defined(CONFIG_NAND) 609 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 610 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 611 #else 612 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 613 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 614 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 615 #endif 616 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 617 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 618 #endif /* CONFIG_NOBQFMAN */ 619 620 #ifdef CONFIG_SYS_DPAA_FMAN 621 #define CONFIG_FMAN_ENET 622 #define CONFIG_PHYLIB_10G 623 #define CONFIG_PHY_VITESSE 624 #define CONFIG_PHY_REALTEK 625 #define CONFIG_PHY_TERANETICS 626 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 627 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 628 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 629 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 630 #endif 631 632 #ifdef CONFIG_FMAN_ENET 633 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 634 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 635 636 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 637 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 638 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 639 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 640 641 #define CONFIG_MII /* MII PHY management */ 642 #define CONFIG_ETHPRIME "FM1@DTSEC1" 643 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 644 #endif 645 646 /* Enable VSC9953 L2 Switch driver */ 647 #define CONFIG_VSC9953 648 #define CONFIG_CMD_ETHSW 649 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 650 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 651 652 /* 653 * Dynamic MTD Partition support with mtdparts 654 */ 655 #ifndef CONFIG_SYS_NO_FLASH 656 #define CONFIG_MTD_DEVICE 657 #define CONFIG_MTD_PARTITIONS 658 #define CONFIG_CMD_MTDPARTS 659 #define CONFIG_FLASH_CFI_MTD 660 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 661 "spi0=spife110000.0" 662 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 663 "128k(dtb),96m(fs),-(user);"\ 664 "fff800000.flash:2m(uboot),9m(kernel),"\ 665 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 666 "2m(uboot),9m(kernel),128k(dtb),-(user)" 667 #endif 668 669 /* 670 * Environment 671 */ 672 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 673 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 674 675 /* 676 * Command line configuration. 677 */ 678 #define CONFIG_CMD_DATE 679 #define CONFIG_CMD_EEPROM 680 #define CONFIG_CMD_ERRATA 681 #define CONFIG_CMD_IRQ 682 #define CONFIG_CMD_REGINFO 683 684 #ifdef CONFIG_PCI 685 #define CONFIG_CMD_PCI 686 #endif 687 688 /* Hash command with SHA acceleration supported in hardware */ 689 #ifdef CONFIG_FSL_CAAM 690 #define CONFIG_CMD_HASH 691 #define CONFIG_SHA_HW_ACCEL 692 #endif 693 694 /* 695 * Miscellaneous configurable options 696 */ 697 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 698 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 699 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 700 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 701 #ifdef CONFIG_CMD_KGDB 702 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 703 #else 704 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 705 #endif 706 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 707 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 708 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 709 710 /* 711 * For booting Linux, the board info and command line data 712 * have to be in the first 64 MB of memory, since this is 713 * the maximum mapped by the Linux kernel during initialization. 714 */ 715 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 716 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 717 718 #ifdef CONFIG_CMD_KGDB 719 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 720 #endif 721 722 /* 723 * Environment Configuration 724 */ 725 #define CONFIG_ROOTPATH "/opt/nfsroot" 726 #define CONFIG_BOOTFILE "uImage" 727 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 728 729 /* default location for tftp and bootm */ 730 #define CONFIG_LOADADDR 1000000 731 732 733 #define CONFIG_BAUDRATE 115200 734 735 #define __USB_PHY_TYPE utmi 736 737 #define CONFIG_EXTRA_ENV_SETTINGS \ 738 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 739 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 740 "netdev=eth0\0" \ 741 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 742 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 743 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 744 "tftpflash=tftpboot $loadaddr $uboot && " \ 745 "protect off $ubootaddr +$filesize && " \ 746 "erase $ubootaddr +$filesize && " \ 747 "cp.b $loadaddr $ubootaddr $filesize && " \ 748 "protect on $ubootaddr +$filesize && " \ 749 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 750 "consoledev=ttyS0\0" \ 751 "ramdiskaddr=2000000\0" \ 752 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 753 "fdtaddr=1e00000\0" \ 754 "fdtfile=t1040qds/t1040qds.dtb\0" \ 755 "bdev=sda3\0" 756 757 #define CONFIG_LINUX \ 758 "setenv bootargs root=/dev/ram rw " \ 759 "console=$consoledev,$baudrate $othbootargs;" \ 760 "setenv ramdiskaddr 0x02000000;" \ 761 "setenv fdtaddr 0x00c00000;" \ 762 "setenv loadaddr 0x1000000;" \ 763 "bootm $loadaddr $ramdiskaddr $fdtaddr" 764 765 #define CONFIG_HDBOOT \ 766 "setenv bootargs root=/dev/$bdev rw " \ 767 "console=$consoledev,$baudrate $othbootargs;" \ 768 "tftp $loadaddr $bootfile;" \ 769 "tftp $fdtaddr $fdtfile;" \ 770 "bootm $loadaddr - $fdtaddr" 771 772 #define CONFIG_NFSBOOTCOMMAND \ 773 "setenv bootargs root=/dev/nfs rw " \ 774 "nfsroot=$serverip:$rootpath " \ 775 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 776 "console=$consoledev,$baudrate $othbootargs;" \ 777 "tftp $loadaddr $bootfile;" \ 778 "tftp $fdtaddr $fdtfile;" \ 779 "bootm $loadaddr - $fdtaddr" 780 781 #define CONFIG_RAMBOOTCOMMAND \ 782 "setenv bootargs root=/dev/ram rw " \ 783 "console=$consoledev,$baudrate $othbootargs;" \ 784 "tftp $ramdiskaddr $ramdiskfile;" \ 785 "tftp $loadaddr $bootfile;" \ 786 "tftp $fdtaddr $fdtfile;" \ 787 "bootm $loadaddr $ramdiskaddr $fdtaddr" 788 789 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 790 791 #include <asm/fsl_secure_boot.h> 792 793 #endif /* __CONFIG_H */ 794