1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 #define CONFIG_T1040QDS 30 #define CONFIG_PHYS_64BIT 31 #define CONFIG_DISPLAY_BOARDINFO 32 33 #ifdef CONFIG_RAMBOOT_PBL 34 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 35 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 36 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 37 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 38 #endif 39 40 /* High Level Configuration Options */ 41 #define CONFIG_BOOKE 42 #define CONFIG_E500 /* BOOKE e500 family */ 43 #define CONFIG_E500MC /* BOOKE e500mc family */ 44 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 45 #define CONFIG_MP /* support multiple processors */ 46 47 /* support deep sleep */ 48 #define CONFIG_DEEP_SLEEP 49 #if defined(CONFIG_DEEP_SLEEP) 50 #define CONFIG_SILENT_CONSOLE 51 #define CONFIG_BOARD_EARLY_INIT_F 52 #endif 53 54 #ifndef CONFIG_SYS_TEXT_BASE 55 #define CONFIG_SYS_TEXT_BASE 0xeff40000 56 #endif 57 58 #ifndef CONFIG_RESET_VECTOR_ADDRESS 59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 60 #endif 61 62 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 63 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 64 #define CONFIG_FSL_IFC /* Enable IFC Support */ 65 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 66 #define CONFIG_PCI /* Enable PCI/PCIE */ 67 #define CONFIG_PCI_INDIRECT_BRIDGE 68 #define CONFIG_PCIE1 /* PCIE controler 1 */ 69 #define CONFIG_PCIE2 /* PCIE controler 2 */ 70 #define CONFIG_PCIE3 /* PCIE controler 3 */ 71 #define CONFIG_PCIE4 /* PCIE controler 4 */ 72 73 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 74 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 75 76 #define CONFIG_FSL_LAW /* Use common FSL init code */ 77 78 #define CONFIG_ENV_OVERWRITE 79 80 #ifdef CONFIG_SYS_NO_FLASH 81 #define CONFIG_ENV_IS_NOWHERE 82 #else 83 #define CONFIG_FLASH_CFI_DRIVER 84 #define CONFIG_SYS_FLASH_CFI 85 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 86 #endif 87 88 #ifndef CONFIG_SYS_NO_FLASH 89 #if defined(CONFIG_SPIFLASH) 90 #define CONFIG_SYS_EXTRA_ENV_RELOC 91 #define CONFIG_ENV_IS_IN_SPI_FLASH 92 #define CONFIG_ENV_SPI_BUS 0 93 #define CONFIG_ENV_SPI_CS 0 94 #define CONFIG_ENV_SPI_MAX_HZ 10000000 95 #define CONFIG_ENV_SPI_MODE 0 96 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 97 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 98 #define CONFIG_ENV_SECT_SIZE 0x10000 99 #elif defined(CONFIG_SDCARD) 100 #define CONFIG_SYS_EXTRA_ENV_RELOC 101 #define CONFIG_ENV_IS_IN_MMC 102 #define CONFIG_SYS_MMC_ENV_DEV 0 103 #define CONFIG_ENV_SIZE 0x2000 104 #define CONFIG_ENV_OFFSET (512 * 1658) 105 #elif defined(CONFIG_NAND) 106 #define CONFIG_SYS_EXTRA_ENV_RELOC 107 #define CONFIG_ENV_IS_IN_NAND 108 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 109 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 110 #else 111 #define CONFIG_ENV_IS_IN_FLASH 112 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 113 #define CONFIG_ENV_SIZE 0x2000 114 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 115 #endif 116 #else /* CONFIG_SYS_NO_FLASH */ 117 #define CONFIG_ENV_SIZE 0x2000 118 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 119 #endif 120 121 #ifndef __ASSEMBLY__ 122 unsigned long get_board_sys_clk(void); 123 unsigned long get_board_ddr_clk(void); 124 #endif 125 126 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 127 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 128 129 /* 130 * These can be toggled for performance analysis, otherwise use default. 131 */ 132 #define CONFIG_SYS_CACHE_STASHING 133 #define CONFIG_BACKSIDE_L2_CACHE 134 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 135 #define CONFIG_BTB /* toggle branch predition */ 136 #define CONFIG_DDR_ECC 137 #ifdef CONFIG_DDR_ECC 138 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 139 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 140 #endif 141 142 #define CONFIG_ENABLE_36BIT_PHYS 143 144 #define CONFIG_ADDR_MAP 145 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 146 147 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 148 #define CONFIG_SYS_MEMTEST_END 0x00400000 149 #define CONFIG_SYS_ALT_MEMTEST 150 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 151 152 /* 153 * Config the L3 Cache as L3 SRAM 154 */ 155 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 156 157 #define CONFIG_SYS_DCSRBAR 0xf0000000 158 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 159 160 /* EEPROM */ 161 #define CONFIG_ID_EEPROM 162 #define CONFIG_SYS_I2C_EEPROM_NXID 163 #define CONFIG_SYS_EEPROM_BUS_NUM 0 164 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 165 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 166 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 167 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 168 169 /* 170 * DDR Setup 171 */ 172 #define CONFIG_VERY_BIG_RAM 173 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 174 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 175 176 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 177 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 178 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 179 180 #define CONFIG_DDR_SPD 181 #ifndef CONFIG_SYS_FSL_DDR4 182 #define CONFIG_SYS_FSL_DDR3 183 #endif 184 #define CONFIG_FSL_DDR_INTERACTIVE 185 186 #define CONFIG_SYS_SPD_BUS_NUM 0 187 #define SPD_EEPROM_ADDRESS 0x51 188 189 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 190 191 /* 192 * IFC Definitions 193 */ 194 #define CONFIG_SYS_FLASH_BASE 0xe0000000 195 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 196 197 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 198 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 199 + 0x8000000) | \ 200 CSPR_PORT_SIZE_16 | \ 201 CSPR_MSEL_NOR | \ 202 CSPR_V) 203 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 204 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 205 CSPR_PORT_SIZE_16 | \ 206 CSPR_MSEL_NOR | \ 207 CSPR_V) 208 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 209 210 /* 211 * TDM Definition 212 */ 213 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 214 215 /* NOR Flash Timing Params */ 216 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 217 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 218 FTIM0_NOR_TEADC(0x5) | \ 219 FTIM0_NOR_TEAHC(0x5)) 220 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 221 FTIM1_NOR_TRAD_NOR(0x1A) |\ 222 FTIM1_NOR_TSEQRAD_NOR(0x13)) 223 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 224 FTIM2_NOR_TCH(0x4) | \ 225 FTIM2_NOR_TWPH(0x0E) | \ 226 FTIM2_NOR_TWP(0x1c)) 227 #define CONFIG_SYS_NOR_FTIM3 0x0 228 229 #define CONFIG_SYS_FLASH_QUIET_TEST 230 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 231 232 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 233 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 234 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 235 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 236 237 #define CONFIG_SYS_FLASH_EMPTY_INFO 238 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 239 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 240 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 241 #define QIXIS_BASE 0xffdf0000 242 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 243 #define QIXIS_LBMAP_SWITCH 0x06 244 #define QIXIS_LBMAP_MASK 0x0f 245 #define QIXIS_LBMAP_SHIFT 0 246 #define QIXIS_LBMAP_DFLTBANK 0x00 247 #define QIXIS_LBMAP_ALTBANK 0x04 248 #define QIXIS_RST_CTL_RESET 0x31 249 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 250 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 251 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 252 #define QIXIS_RST_FORCE_MEM 0x01 253 254 #define CONFIG_SYS_CSPR3_EXT (0xf) 255 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 256 | CSPR_PORT_SIZE_8 \ 257 | CSPR_MSEL_GPCM \ 258 | CSPR_V) 259 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 260 #define CONFIG_SYS_CSOR3 0x0 261 /* QIXIS Timing parameters for IFC CS3 */ 262 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 263 FTIM0_GPCM_TEADC(0x0e) | \ 264 FTIM0_GPCM_TEAHC(0x0e)) 265 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 266 FTIM1_GPCM_TRAD(0x3f)) 267 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 268 FTIM2_GPCM_TCH(0x8) | \ 269 FTIM2_GPCM_TWP(0x1f)) 270 #define CONFIG_SYS_CS3_FTIM3 0x0 271 272 #define CONFIG_NAND_FSL_IFC 273 #define CONFIG_SYS_NAND_BASE 0xff800000 274 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 275 276 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 277 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 278 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 279 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 280 | CSPR_V) 281 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 282 283 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 284 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 285 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 286 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 287 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 288 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 289 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 290 291 #define CONFIG_SYS_NAND_ONFI_DETECTION 292 293 /* ONFI NAND Flash mode0 Timing Params */ 294 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 295 FTIM0_NAND_TWP(0x18) | \ 296 FTIM0_NAND_TWCHT(0x07) | \ 297 FTIM0_NAND_TWH(0x0a)) 298 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 299 FTIM1_NAND_TWBE(0x39) | \ 300 FTIM1_NAND_TRR(0x0e) | \ 301 FTIM1_NAND_TRP(0x18)) 302 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 303 FTIM2_NAND_TREH(0x0a) | \ 304 FTIM2_NAND_TWHRE(0x1e)) 305 #define CONFIG_SYS_NAND_FTIM3 0x0 306 307 #define CONFIG_SYS_NAND_DDR_LAW 11 308 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 309 #define CONFIG_SYS_MAX_NAND_DEVICE 1 310 #define CONFIG_CMD_NAND 311 312 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 313 314 #if defined(CONFIG_NAND) 315 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 316 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 317 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 318 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 319 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 320 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 321 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 322 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 323 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 324 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 325 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 326 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 327 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 328 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 329 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 330 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 331 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 332 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 333 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 334 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 335 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 336 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 337 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 338 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 339 #else 340 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 341 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 342 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 343 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 344 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 345 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 346 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 347 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 348 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 349 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 350 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 351 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 352 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 353 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 354 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 355 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 356 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 357 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 358 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 359 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 360 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 361 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 362 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 363 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 364 #endif 365 366 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 367 368 #if defined(CONFIG_RAMBOOT_PBL) 369 #define CONFIG_SYS_RAMBOOT 370 #endif 371 372 #define CONFIG_BOARD_EARLY_INIT_R 373 #define CONFIG_MISC_INIT_R 374 375 #define CONFIG_HWCONFIG 376 377 /* define to use L1 as initial stack */ 378 #define CONFIG_L1_INIT_RAM 379 #define CONFIG_SYS_INIT_RAM_LOCK 380 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 381 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 382 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 383 /* The assembler doesn't like typecast */ 384 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 385 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 386 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 387 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 388 389 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 390 GENERATED_GBL_DATA_SIZE) 391 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 392 393 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 394 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 395 396 /* Serial Port - controlled on board with jumper J8 397 * open - index 2 398 * shorted - index 1 399 */ 400 #define CONFIG_CONS_INDEX 1 401 #define CONFIG_SYS_NS16550_SERIAL 402 #define CONFIG_SYS_NS16550_REG_SIZE 1 403 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 404 405 #define CONFIG_SYS_BAUDRATE_TABLE \ 406 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 407 408 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 409 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 410 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 411 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 412 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 413 414 /* Video */ 415 #define CONFIG_FSL_DIU_FB 416 #ifdef CONFIG_FSL_DIU_FB 417 #define CONFIG_FSL_DIU_CH7301 418 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 419 #define CONFIG_VIDEO 420 #define CONFIG_CMD_BMP 421 #define CONFIG_CFB_CONSOLE 422 #define CONFIG_VIDEO_SW_CURSOR 423 #define CONFIG_VGA_AS_SINGLE_DEVICE 424 #define CONFIG_VIDEO_LOGO 425 #define CONFIG_VIDEO_BMP_LOGO 426 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 427 /* 428 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 429 * disable empty flash sector detection, which is I/O-intensive. 430 */ 431 #undef CONFIG_SYS_FLASH_EMPTY_INFO 432 #endif 433 434 /* I2C */ 435 #define CONFIG_SYS_I2C 436 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 437 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 438 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 439 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 440 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 441 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 442 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 443 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 444 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 445 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 446 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 447 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 448 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 449 450 #define I2C_MUX_PCA_ADDR 0x77 451 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 452 453 454 /* I2C bus multiplexer */ 455 #define I2C_MUX_CH_DEFAULT 0x8 456 #define I2C_MUX_CH_DIU 0xC 457 458 /* LDI/DVI Encoder for display */ 459 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 460 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 461 462 /* 463 * RTC configuration 464 */ 465 #define RTC 466 #define CONFIG_RTC_DS3231 1 467 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 468 469 /* 470 * eSPI - Enhanced SPI 471 */ 472 #define CONFIG_SF_DEFAULT_SPEED 10000000 473 #define CONFIG_SF_DEFAULT_MODE 0 474 475 /* 476 * General PCI 477 * Memory space is mapped 1-1, but I/O space must start from 0. 478 */ 479 480 #ifdef CONFIG_PCI 481 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 482 #ifdef CONFIG_PCIE1 483 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 484 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 485 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 486 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 487 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 488 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 489 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 490 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 491 #endif 492 493 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 494 #ifdef CONFIG_PCIE2 495 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 496 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 497 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 498 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 499 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 500 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 501 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 502 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 503 #endif 504 505 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 506 #ifdef CONFIG_PCIE3 507 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 508 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 509 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 510 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 511 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 512 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 513 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 514 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 515 #endif 516 517 /* controller 4, Base address 203000 */ 518 #ifdef CONFIG_PCIE4 519 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 520 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 521 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 522 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 523 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 524 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 525 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 526 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 527 #endif 528 529 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 530 531 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 532 #define CONFIG_DOS_PARTITION 533 #endif /* CONFIG_PCI */ 534 535 /* SATA */ 536 #define CONFIG_FSL_SATA_V2 537 #ifdef CONFIG_FSL_SATA_V2 538 #define CONFIG_LIBATA 539 #define CONFIG_FSL_SATA 540 541 #define CONFIG_SYS_SATA_MAX_DEVICE 2 542 #define CONFIG_SATA1 543 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 544 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 545 #define CONFIG_SATA2 546 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 547 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 548 549 #define CONFIG_LBA48 550 #define CONFIG_CMD_SATA 551 #define CONFIG_DOS_PARTITION 552 #define CONFIG_CMD_EXT2 553 #endif 554 555 /* 556 * USB 557 */ 558 #define CONFIG_HAS_FSL_DR_USB 559 560 #ifdef CONFIG_HAS_FSL_DR_USB 561 #define CONFIG_USB_EHCI 562 563 #ifdef CONFIG_USB_EHCI 564 #define CONFIG_USB_STORAGE 565 #define CONFIG_USB_EHCI_FSL 566 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 567 #define CONFIG_CMD_EXT2 568 #endif 569 #endif 570 571 #define CONFIG_MMC 572 573 #ifdef CONFIG_MMC 574 #define CONFIG_FSL_ESDHC 575 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 576 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 577 #define CONFIG_CMD_MMC 578 #define CONFIG_GENERIC_MMC 579 #define CONFIG_CMD_EXT2 580 #define CONFIG_CMD_FAT 581 #define CONFIG_DOS_PARTITION 582 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 583 #endif 584 585 /* Qman/Bman */ 586 #ifndef CONFIG_NOBQFMAN 587 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 588 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 589 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 590 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 591 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 592 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 593 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 594 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 595 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 596 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 597 CONFIG_SYS_BMAN_CENA_SIZE) 598 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 599 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 600 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 601 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 602 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 603 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 604 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 605 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 606 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 607 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 608 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 609 CONFIG_SYS_QMAN_CENA_SIZE) 610 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 611 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 612 613 #define CONFIG_SYS_DPAA_FMAN 614 #define CONFIG_SYS_DPAA_PME 615 616 #define CONFIG_QE 617 #define CONFIG_U_QE 618 /* Default address of microcode for the Linux Fman driver */ 619 #if defined(CONFIG_SPIFLASH) 620 /* 621 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 622 * env, so we got 0x110000. 623 */ 624 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 625 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 626 #elif defined(CONFIG_SDCARD) 627 /* 628 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 629 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 630 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 631 */ 632 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 633 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 634 #elif defined(CONFIG_NAND) 635 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 636 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 637 #else 638 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 639 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 640 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 641 #endif 642 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 643 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 644 #endif /* CONFIG_NOBQFMAN */ 645 646 #ifdef CONFIG_SYS_DPAA_FMAN 647 #define CONFIG_FMAN_ENET 648 #define CONFIG_PHYLIB_10G 649 #define CONFIG_PHY_VITESSE 650 #define CONFIG_PHY_REALTEK 651 #define CONFIG_PHY_TERANETICS 652 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 653 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 654 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 655 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 656 #endif 657 658 #ifdef CONFIG_FMAN_ENET 659 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 660 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 661 662 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 663 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 664 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 665 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 666 667 #define CONFIG_MII /* MII PHY management */ 668 #define CONFIG_ETHPRIME "FM1@DTSEC1" 669 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 670 #endif 671 672 /* Enable VSC9953 L2 Switch driver */ 673 #define CONFIG_VSC9953 674 #define CONFIG_CMD_ETHSW 675 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 676 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 677 678 /* 679 * Dynamic MTD Partition support with mtdparts 680 */ 681 #ifndef CONFIG_SYS_NO_FLASH 682 #define CONFIG_MTD_DEVICE 683 #define CONFIG_MTD_PARTITIONS 684 #define CONFIG_CMD_MTDPARTS 685 #define CONFIG_FLASH_CFI_MTD 686 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 687 "spi0=spife110000.0" 688 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 689 "128k(dtb),96m(fs),-(user);"\ 690 "fff800000.flash:2m(uboot),9m(kernel),"\ 691 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 692 "2m(uboot),9m(kernel),128k(dtb),-(user)" 693 #endif 694 695 /* 696 * Environment 697 */ 698 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 699 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 700 701 /* 702 * Command line configuration. 703 */ 704 #define CONFIG_CMD_DATE 705 #define CONFIG_CMD_EEPROM 706 #define CONFIG_CMD_ERRATA 707 #define CONFIG_CMD_GREPENV 708 #define CONFIG_CMD_IRQ 709 #define CONFIG_CMD_MII 710 #define CONFIG_CMD_REGINFO 711 712 #ifdef CONFIG_PCI 713 #define CONFIG_CMD_PCI 714 #endif 715 716 /* Hash command with SHA acceleration supported in hardware */ 717 #ifdef CONFIG_FSL_CAAM 718 #define CONFIG_CMD_HASH 719 #define CONFIG_SHA_HW_ACCEL 720 #endif 721 722 /* 723 * Miscellaneous configurable options 724 */ 725 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 726 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 727 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 728 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 729 #ifdef CONFIG_CMD_KGDB 730 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 731 #else 732 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 733 #endif 734 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 735 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 736 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 737 738 /* 739 * For booting Linux, the board info and command line data 740 * have to be in the first 64 MB of memory, since this is 741 * the maximum mapped by the Linux kernel during initialization. 742 */ 743 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 744 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 745 746 #ifdef CONFIG_CMD_KGDB 747 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 748 #endif 749 750 /* 751 * Environment Configuration 752 */ 753 #define CONFIG_ROOTPATH "/opt/nfsroot" 754 #define CONFIG_BOOTFILE "uImage" 755 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 756 757 /* default location for tftp and bootm */ 758 #define CONFIG_LOADADDR 1000000 759 760 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 761 762 #define CONFIG_BAUDRATE 115200 763 764 #define __USB_PHY_TYPE utmi 765 766 #define CONFIG_EXTRA_ENV_SETTINGS \ 767 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 768 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 769 "netdev=eth0\0" \ 770 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 771 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 772 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 773 "tftpflash=tftpboot $loadaddr $uboot && " \ 774 "protect off $ubootaddr +$filesize && " \ 775 "erase $ubootaddr +$filesize && " \ 776 "cp.b $loadaddr $ubootaddr $filesize && " \ 777 "protect on $ubootaddr +$filesize && " \ 778 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 779 "consoledev=ttyS0\0" \ 780 "ramdiskaddr=2000000\0" \ 781 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 782 "fdtaddr=c00000\0" \ 783 "fdtfile=t1040qds/t1040qds.dtb\0" \ 784 "bdev=sda3\0" 785 786 #define CONFIG_LINUX \ 787 "setenv bootargs root=/dev/ram rw " \ 788 "console=$consoledev,$baudrate $othbootargs;" \ 789 "setenv ramdiskaddr 0x02000000;" \ 790 "setenv fdtaddr 0x00c00000;" \ 791 "setenv loadaddr 0x1000000;" \ 792 "bootm $loadaddr $ramdiskaddr $fdtaddr" 793 794 #define CONFIG_HDBOOT \ 795 "setenv bootargs root=/dev/$bdev rw " \ 796 "console=$consoledev,$baudrate $othbootargs;" \ 797 "tftp $loadaddr $bootfile;" \ 798 "tftp $fdtaddr $fdtfile;" \ 799 "bootm $loadaddr - $fdtaddr" 800 801 #define CONFIG_NFSBOOTCOMMAND \ 802 "setenv bootargs root=/dev/nfs rw " \ 803 "nfsroot=$serverip:$rootpath " \ 804 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 805 "console=$consoledev,$baudrate $othbootargs;" \ 806 "tftp $loadaddr $bootfile;" \ 807 "tftp $fdtaddr $fdtfile;" \ 808 "bootm $loadaddr - $fdtaddr" 809 810 #define CONFIG_RAMBOOTCOMMAND \ 811 "setenv bootargs root=/dev/ram rw " \ 812 "console=$consoledev,$baudrate $othbootargs;" \ 813 "tftp $ramdiskaddr $ramdiskfile;" \ 814 "tftp $loadaddr $bootfile;" \ 815 "tftp $fdtaddr $fdtfile;" \ 816 "bootm $loadaddr $ramdiskaddr $fdtaddr" 817 818 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 819 820 #include <asm/fsl_secure_boot.h> 821 822 #endif /* __CONFIG_H */ 823