1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 #define CONFIG_T1040QDS 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 35 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 36 #endif 37 38 /* High Level Configuration Options */ 39 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 40 #define CONFIG_MP /* support multiple processors */ 41 42 /* support deep sleep */ 43 #define CONFIG_DEEP_SLEEP 44 #if defined(CONFIG_DEEP_SLEEP) 45 #define CONFIG_BOARD_EARLY_INIT_F 46 #endif 47 48 #ifndef CONFIG_SYS_TEXT_BASE 49 #define CONFIG_SYS_TEXT_BASE 0xeff40000 50 #endif 51 52 #ifndef CONFIG_RESET_VECTOR_ADDRESS 53 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 54 #endif 55 56 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 57 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 58 #define CONFIG_FSL_IFC /* Enable IFC Support */ 59 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 60 #define CONFIG_PCI_INDIRECT_BRIDGE 61 #define CONFIG_PCIE1 /* PCIE controller 1 */ 62 #define CONFIG_PCIE2 /* PCIE controller 2 */ 63 #define CONFIG_PCIE3 /* PCIE controller 3 */ 64 #define CONFIG_PCIE4 /* PCIE controller 4 */ 65 66 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 67 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 68 69 #define CONFIG_ENV_OVERWRITE 70 71 #ifdef CONFIG_SYS_NO_FLASH 72 #define CONFIG_ENV_IS_NOWHERE 73 #else 74 #define CONFIG_FLASH_CFI_DRIVER 75 #define CONFIG_SYS_FLASH_CFI 76 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 77 #endif 78 79 #ifndef CONFIG_SYS_NO_FLASH 80 #if defined(CONFIG_SPIFLASH) 81 #define CONFIG_SYS_EXTRA_ENV_RELOC 82 #define CONFIG_ENV_IS_IN_SPI_FLASH 83 #define CONFIG_ENV_SPI_BUS 0 84 #define CONFIG_ENV_SPI_CS 0 85 #define CONFIG_ENV_SPI_MAX_HZ 10000000 86 #define CONFIG_ENV_SPI_MODE 0 87 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 88 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 89 #define CONFIG_ENV_SECT_SIZE 0x10000 90 #elif defined(CONFIG_SDCARD) 91 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_ENV_IS_IN_MMC 93 #define CONFIG_SYS_MMC_ENV_DEV 0 94 #define CONFIG_ENV_SIZE 0x2000 95 #define CONFIG_ENV_OFFSET (512 * 1658) 96 #elif defined(CONFIG_NAND) 97 #define CONFIG_SYS_EXTRA_ENV_RELOC 98 #define CONFIG_ENV_IS_IN_NAND 99 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 100 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 101 #else 102 #define CONFIG_ENV_IS_IN_FLASH 103 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 104 #define CONFIG_ENV_SIZE 0x2000 105 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 106 #endif 107 #else /* CONFIG_SYS_NO_FLASH */ 108 #define CONFIG_ENV_SIZE 0x2000 109 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 110 #endif 111 112 #ifndef __ASSEMBLY__ 113 unsigned long get_board_sys_clk(void); 114 unsigned long get_board_ddr_clk(void); 115 #endif 116 117 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 118 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 119 120 /* 121 * These can be toggled for performance analysis, otherwise use default. 122 */ 123 #define CONFIG_SYS_CACHE_STASHING 124 #define CONFIG_BACKSIDE_L2_CACHE 125 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 126 #define CONFIG_BTB /* toggle branch predition */ 127 #define CONFIG_DDR_ECC 128 #ifdef CONFIG_DDR_ECC 129 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 130 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 131 #endif 132 133 #define CONFIG_ENABLE_36BIT_PHYS 134 135 #define CONFIG_ADDR_MAP 136 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 137 138 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 139 #define CONFIG_SYS_MEMTEST_END 0x00400000 140 #define CONFIG_SYS_ALT_MEMTEST 141 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 142 143 /* 144 * Config the L3 Cache as L3 SRAM 145 */ 146 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 147 148 #define CONFIG_SYS_DCSRBAR 0xf0000000 149 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 150 151 /* EEPROM */ 152 #define CONFIG_ID_EEPROM 153 #define CONFIG_SYS_I2C_EEPROM_NXID 154 #define CONFIG_SYS_EEPROM_BUS_NUM 0 155 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 156 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 157 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 158 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 159 160 /* 161 * DDR Setup 162 */ 163 #define CONFIG_VERY_BIG_RAM 164 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 165 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 166 167 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 168 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 169 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 170 171 #define CONFIG_DDR_SPD 172 #ifndef CONFIG_SYS_FSL_DDR4 173 #define CONFIG_SYS_FSL_DDR3 174 #endif 175 #define CONFIG_FSL_DDR_INTERACTIVE 176 177 #define CONFIG_SYS_SPD_BUS_NUM 0 178 #define SPD_EEPROM_ADDRESS 0x51 179 180 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 181 182 /* 183 * IFC Definitions 184 */ 185 #define CONFIG_SYS_FLASH_BASE 0xe0000000 186 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 187 188 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 189 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 190 + 0x8000000) | \ 191 CSPR_PORT_SIZE_16 | \ 192 CSPR_MSEL_NOR | \ 193 CSPR_V) 194 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 195 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 196 CSPR_PORT_SIZE_16 | \ 197 CSPR_MSEL_NOR | \ 198 CSPR_V) 199 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 200 201 /* 202 * TDM Definition 203 */ 204 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 205 206 /* NOR Flash Timing Params */ 207 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 208 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 209 FTIM0_NOR_TEADC(0x5) | \ 210 FTIM0_NOR_TEAHC(0x5)) 211 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 212 FTIM1_NOR_TRAD_NOR(0x1A) |\ 213 FTIM1_NOR_TSEQRAD_NOR(0x13)) 214 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 215 FTIM2_NOR_TCH(0x4) | \ 216 FTIM2_NOR_TWPH(0x0E) | \ 217 FTIM2_NOR_TWP(0x1c)) 218 #define CONFIG_SYS_NOR_FTIM3 0x0 219 220 #define CONFIG_SYS_FLASH_QUIET_TEST 221 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 222 223 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 224 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 225 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 226 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 227 228 #define CONFIG_SYS_FLASH_EMPTY_INFO 229 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 230 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 231 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 232 #define QIXIS_BASE 0xffdf0000 233 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 234 #define QIXIS_LBMAP_SWITCH 0x06 235 #define QIXIS_LBMAP_MASK 0x0f 236 #define QIXIS_LBMAP_SHIFT 0 237 #define QIXIS_LBMAP_DFLTBANK 0x00 238 #define QIXIS_LBMAP_ALTBANK 0x04 239 #define QIXIS_RST_CTL_RESET 0x31 240 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 241 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 242 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 243 #define QIXIS_RST_FORCE_MEM 0x01 244 245 #define CONFIG_SYS_CSPR3_EXT (0xf) 246 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 247 | CSPR_PORT_SIZE_8 \ 248 | CSPR_MSEL_GPCM \ 249 | CSPR_V) 250 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 251 #define CONFIG_SYS_CSOR3 0x0 252 /* QIXIS Timing parameters for IFC CS3 */ 253 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 254 FTIM0_GPCM_TEADC(0x0e) | \ 255 FTIM0_GPCM_TEAHC(0x0e)) 256 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 257 FTIM1_GPCM_TRAD(0x3f)) 258 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 259 FTIM2_GPCM_TCH(0x8) | \ 260 FTIM2_GPCM_TWP(0x1f)) 261 #define CONFIG_SYS_CS3_FTIM3 0x0 262 263 #define CONFIG_NAND_FSL_IFC 264 #define CONFIG_SYS_NAND_BASE 0xff800000 265 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 266 267 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 268 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 269 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 270 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 271 | CSPR_V) 272 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 273 274 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 275 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 276 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 277 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 278 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 279 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 280 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 281 282 #define CONFIG_SYS_NAND_ONFI_DETECTION 283 284 /* ONFI NAND Flash mode0 Timing Params */ 285 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 286 FTIM0_NAND_TWP(0x18) | \ 287 FTIM0_NAND_TWCHT(0x07) | \ 288 FTIM0_NAND_TWH(0x0a)) 289 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 290 FTIM1_NAND_TWBE(0x39) | \ 291 FTIM1_NAND_TRR(0x0e) | \ 292 FTIM1_NAND_TRP(0x18)) 293 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 294 FTIM2_NAND_TREH(0x0a) | \ 295 FTIM2_NAND_TWHRE(0x1e)) 296 #define CONFIG_SYS_NAND_FTIM3 0x0 297 298 #define CONFIG_SYS_NAND_DDR_LAW 11 299 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 300 #define CONFIG_SYS_MAX_NAND_DEVICE 1 301 #define CONFIG_CMD_NAND 302 303 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 304 305 #if defined(CONFIG_NAND) 306 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 307 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 308 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 309 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 310 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 311 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 312 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 313 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 314 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 315 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 316 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 317 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 318 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 319 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 320 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 321 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 322 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 323 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 324 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 325 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 326 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 327 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 328 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 329 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 330 #else 331 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 332 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 333 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 334 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 335 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 336 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 337 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 338 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 339 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 340 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 341 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 342 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 343 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 344 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 345 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 346 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 347 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 348 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 349 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 350 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 351 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 352 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 353 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 354 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 355 #endif 356 357 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 358 359 #if defined(CONFIG_RAMBOOT_PBL) 360 #define CONFIG_SYS_RAMBOOT 361 #endif 362 363 #define CONFIG_BOARD_EARLY_INIT_R 364 #define CONFIG_MISC_INIT_R 365 366 #define CONFIG_HWCONFIG 367 368 /* define to use L1 as initial stack */ 369 #define CONFIG_L1_INIT_RAM 370 #define CONFIG_SYS_INIT_RAM_LOCK 371 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 372 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 373 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 374 /* The assembler doesn't like typecast */ 375 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 376 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 377 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 378 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 379 380 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 381 GENERATED_GBL_DATA_SIZE) 382 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 383 384 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 385 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 386 387 /* Serial Port - controlled on board with jumper J8 388 * open - index 2 389 * shorted - index 1 390 */ 391 #define CONFIG_CONS_INDEX 1 392 #define CONFIG_SYS_NS16550_SERIAL 393 #define CONFIG_SYS_NS16550_REG_SIZE 1 394 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 395 396 #define CONFIG_SYS_BAUDRATE_TABLE \ 397 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 398 399 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 400 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 401 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 402 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 403 404 /* Video */ 405 #define CONFIG_FSL_DIU_FB 406 #ifdef CONFIG_FSL_DIU_FB 407 #define CONFIG_FSL_DIU_CH7301 408 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 409 #define CONFIG_CMD_BMP 410 #define CONFIG_VIDEO_LOGO 411 #define CONFIG_VIDEO_BMP_LOGO 412 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 413 /* 414 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 415 * disable empty flash sector detection, which is I/O-intensive. 416 */ 417 #undef CONFIG_SYS_FLASH_EMPTY_INFO 418 #endif 419 420 /* I2C */ 421 #define CONFIG_SYS_I2C 422 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 423 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 424 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 425 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 426 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 427 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 428 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 429 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 430 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 431 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 432 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 433 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 434 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 435 436 #define I2C_MUX_PCA_ADDR 0x77 437 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 438 439 /* I2C bus multiplexer */ 440 #define I2C_MUX_CH_DEFAULT 0x8 441 #define I2C_MUX_CH_DIU 0xC 442 443 /* LDI/DVI Encoder for display */ 444 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 445 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 446 447 /* 448 * RTC configuration 449 */ 450 #define RTC 451 #define CONFIG_RTC_DS3231 1 452 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 453 454 /* 455 * eSPI - Enhanced SPI 456 */ 457 #define CONFIG_SF_DEFAULT_SPEED 10000000 458 #define CONFIG_SF_DEFAULT_MODE 0 459 460 /* 461 * General PCI 462 * Memory space is mapped 1-1, but I/O space must start from 0. 463 */ 464 465 #ifdef CONFIG_PCI 466 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 467 #ifdef CONFIG_PCIE1 468 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 469 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 470 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 471 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 472 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 473 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 474 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 475 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 476 #endif 477 478 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 479 #ifdef CONFIG_PCIE2 480 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 481 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 482 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 483 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 484 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 485 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 486 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 487 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 488 #endif 489 490 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 491 #ifdef CONFIG_PCIE3 492 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 493 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 494 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 495 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 496 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 497 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 498 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 499 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 500 #endif 501 502 /* controller 4, Base address 203000 */ 503 #ifdef CONFIG_PCIE4 504 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 505 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 506 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 507 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 508 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 509 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 510 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 511 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 512 #endif 513 514 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 515 #define CONFIG_DOS_PARTITION 516 #endif /* CONFIG_PCI */ 517 518 /* SATA */ 519 #define CONFIG_FSL_SATA_V2 520 #ifdef CONFIG_FSL_SATA_V2 521 #define CONFIG_LIBATA 522 #define CONFIG_FSL_SATA 523 524 #define CONFIG_SYS_SATA_MAX_DEVICE 2 525 #define CONFIG_SATA1 526 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 527 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 528 #define CONFIG_SATA2 529 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 530 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 531 532 #define CONFIG_LBA48 533 #define CONFIG_CMD_SATA 534 #define CONFIG_DOS_PARTITION 535 #endif 536 537 /* 538 * USB 539 */ 540 #define CONFIG_HAS_FSL_DR_USB 541 542 #ifdef CONFIG_HAS_FSL_DR_USB 543 #define CONFIG_USB_EHCI 544 545 #ifdef CONFIG_USB_EHCI 546 #define CONFIG_USB_EHCI_FSL 547 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 548 #endif 549 #endif 550 551 #ifdef CONFIG_MMC 552 #define CONFIG_FSL_ESDHC 553 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 554 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 555 #define CONFIG_GENERIC_MMC 556 #define CONFIG_DOS_PARTITION 557 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 558 #endif 559 560 /* Qman/Bman */ 561 #ifndef CONFIG_NOBQFMAN 562 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 563 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 564 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 565 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 566 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 567 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 568 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 569 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 570 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 571 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 572 CONFIG_SYS_BMAN_CENA_SIZE) 573 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 574 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 575 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 576 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 577 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 578 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 579 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 580 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 581 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 582 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 583 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 584 CONFIG_SYS_QMAN_CENA_SIZE) 585 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 586 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 587 588 #define CONFIG_SYS_DPAA_FMAN 589 #define CONFIG_SYS_DPAA_PME 590 591 #define CONFIG_QE 592 #define CONFIG_U_QE 593 /* Default address of microcode for the Linux Fman driver */ 594 #if defined(CONFIG_SPIFLASH) 595 /* 596 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 597 * env, so we got 0x110000. 598 */ 599 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 600 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 601 #elif defined(CONFIG_SDCARD) 602 /* 603 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 604 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 605 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 606 */ 607 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 608 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 609 #elif defined(CONFIG_NAND) 610 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 611 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 612 #else 613 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 614 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 615 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 616 #endif 617 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 618 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 619 #endif /* CONFIG_NOBQFMAN */ 620 621 #ifdef CONFIG_SYS_DPAA_FMAN 622 #define CONFIG_FMAN_ENET 623 #define CONFIG_PHYLIB_10G 624 #define CONFIG_PHY_VITESSE 625 #define CONFIG_PHY_REALTEK 626 #define CONFIG_PHY_TERANETICS 627 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 628 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 629 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 630 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 631 #endif 632 633 #ifdef CONFIG_FMAN_ENET 634 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 635 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 636 637 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 638 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 639 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 640 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 641 642 #define CONFIG_MII /* MII PHY management */ 643 #define CONFIG_ETHPRIME "FM1@DTSEC1" 644 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 645 #endif 646 647 /* Enable VSC9953 L2 Switch driver */ 648 #define CONFIG_VSC9953 649 #define CONFIG_CMD_ETHSW 650 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 651 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 652 653 /* 654 * Dynamic MTD Partition support with mtdparts 655 */ 656 #ifndef CONFIG_SYS_NO_FLASH 657 #define CONFIG_MTD_DEVICE 658 #define CONFIG_MTD_PARTITIONS 659 #define CONFIG_CMD_MTDPARTS 660 #define CONFIG_FLASH_CFI_MTD 661 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 662 "spi0=spife110000.0" 663 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 664 "128k(dtb),96m(fs),-(user);"\ 665 "fff800000.flash:2m(uboot),9m(kernel),"\ 666 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 667 "2m(uboot),9m(kernel),128k(dtb),-(user)" 668 #endif 669 670 /* 671 * Environment 672 */ 673 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 674 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 675 676 /* 677 * Command line configuration. 678 */ 679 #define CONFIG_CMD_DATE 680 #define CONFIG_CMD_EEPROM 681 #define CONFIG_CMD_ERRATA 682 #define CONFIG_CMD_IRQ 683 #define CONFIG_CMD_REGINFO 684 685 #ifdef CONFIG_PCI 686 #define CONFIG_CMD_PCI 687 #endif 688 689 /* Hash command with SHA acceleration supported in hardware */ 690 #ifdef CONFIG_FSL_CAAM 691 #define CONFIG_CMD_HASH 692 #define CONFIG_SHA_HW_ACCEL 693 #endif 694 695 /* 696 * Miscellaneous configurable options 697 */ 698 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 699 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 700 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 701 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 702 #ifdef CONFIG_CMD_KGDB 703 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 704 #else 705 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 706 #endif 707 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 708 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 709 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 710 711 /* 712 * For booting Linux, the board info and command line data 713 * have to be in the first 64 MB of memory, since this is 714 * the maximum mapped by the Linux kernel during initialization. 715 */ 716 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 717 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 718 719 #ifdef CONFIG_CMD_KGDB 720 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 721 #endif 722 723 /* 724 * Environment Configuration 725 */ 726 #define CONFIG_ROOTPATH "/opt/nfsroot" 727 #define CONFIG_BOOTFILE "uImage" 728 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 729 730 /* default location for tftp and bootm */ 731 #define CONFIG_LOADADDR 1000000 732 733 734 #define CONFIG_BAUDRATE 115200 735 736 #define __USB_PHY_TYPE utmi 737 738 #define CONFIG_EXTRA_ENV_SETTINGS \ 739 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 740 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 741 "netdev=eth0\0" \ 742 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 743 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 744 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 745 "tftpflash=tftpboot $loadaddr $uboot && " \ 746 "protect off $ubootaddr +$filesize && " \ 747 "erase $ubootaddr +$filesize && " \ 748 "cp.b $loadaddr $ubootaddr $filesize && " \ 749 "protect on $ubootaddr +$filesize && " \ 750 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 751 "consoledev=ttyS0\0" \ 752 "ramdiskaddr=2000000\0" \ 753 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 754 "fdtaddr=1e00000\0" \ 755 "fdtfile=t1040qds/t1040qds.dtb\0" \ 756 "bdev=sda3\0" 757 758 #define CONFIG_LINUX \ 759 "setenv bootargs root=/dev/ram rw " \ 760 "console=$consoledev,$baudrate $othbootargs;" \ 761 "setenv ramdiskaddr 0x02000000;" \ 762 "setenv fdtaddr 0x00c00000;" \ 763 "setenv loadaddr 0x1000000;" \ 764 "bootm $loadaddr $ramdiskaddr $fdtaddr" 765 766 #define CONFIG_HDBOOT \ 767 "setenv bootargs root=/dev/$bdev rw " \ 768 "console=$consoledev,$baudrate $othbootargs;" \ 769 "tftp $loadaddr $bootfile;" \ 770 "tftp $fdtaddr $fdtfile;" \ 771 "bootm $loadaddr - $fdtaddr" 772 773 #define CONFIG_NFSBOOTCOMMAND \ 774 "setenv bootargs root=/dev/nfs rw " \ 775 "nfsroot=$serverip:$rootpath " \ 776 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 777 "console=$consoledev,$baudrate $othbootargs;" \ 778 "tftp $loadaddr $bootfile;" \ 779 "tftp $fdtaddr $fdtfile;" \ 780 "bootm $loadaddr - $fdtaddr" 781 782 #define CONFIG_RAMBOOTCOMMAND \ 783 "setenv bootargs root=/dev/ram rw " \ 784 "console=$consoledev,$baudrate $othbootargs;" \ 785 "tftp $ramdiskaddr $ramdiskfile;" \ 786 "tftp $loadaddr $bootfile;" \ 787 "tftp $fdtaddr $fdtfile;" \ 788 "bootm $loadaddr $ramdiskaddr $fdtaddr" 789 790 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 791 792 #include <asm/fsl_secure_boot.h> 793 794 #endif /* __CONFIG_H */ 795