1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 #define CONFIG_T1040QDS 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 35 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 36 #endif 37 38 /* High Level Configuration Options */ 39 #define CONFIG_BOOKE 40 #define CONFIG_E500 /* BOOKE e500 family */ 41 #define CONFIG_E500MC /* BOOKE e500mc family */ 42 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 43 #define CONFIG_MP /* support multiple processors */ 44 45 /* support deep sleep */ 46 #define CONFIG_DEEP_SLEEP 47 #if defined(CONFIG_DEEP_SLEEP) 48 #define CONFIG_BOARD_EARLY_INIT_F 49 #endif 50 51 #ifndef CONFIG_SYS_TEXT_BASE 52 #define CONFIG_SYS_TEXT_BASE 0xeff40000 53 #endif 54 55 #ifndef CONFIG_RESET_VECTOR_ADDRESS 56 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 57 #endif 58 59 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 60 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 61 #define CONFIG_FSL_IFC /* Enable IFC Support */ 62 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 63 #define CONFIG_PCI /* Enable PCI/PCIE */ 64 #define CONFIG_PCI_INDIRECT_BRIDGE 65 #define CONFIG_PCIE1 /* PCIE controller 1 */ 66 #define CONFIG_PCIE2 /* PCIE controller 2 */ 67 #define CONFIG_PCIE3 /* PCIE controller 3 */ 68 #define CONFIG_PCIE4 /* PCIE controller 4 */ 69 70 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 71 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 72 73 #define CONFIG_FSL_LAW /* Use common FSL init code */ 74 75 #define CONFIG_ENV_OVERWRITE 76 77 #ifdef CONFIG_SYS_NO_FLASH 78 #define CONFIG_ENV_IS_NOWHERE 79 #else 80 #define CONFIG_FLASH_CFI_DRIVER 81 #define CONFIG_SYS_FLASH_CFI 82 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 83 #endif 84 85 #ifndef CONFIG_SYS_NO_FLASH 86 #if defined(CONFIG_SPIFLASH) 87 #define CONFIG_SYS_EXTRA_ENV_RELOC 88 #define CONFIG_ENV_IS_IN_SPI_FLASH 89 #define CONFIG_ENV_SPI_BUS 0 90 #define CONFIG_ENV_SPI_CS 0 91 #define CONFIG_ENV_SPI_MAX_HZ 10000000 92 #define CONFIG_ENV_SPI_MODE 0 93 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 94 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 95 #define CONFIG_ENV_SECT_SIZE 0x10000 96 #elif defined(CONFIG_SDCARD) 97 #define CONFIG_SYS_EXTRA_ENV_RELOC 98 #define CONFIG_ENV_IS_IN_MMC 99 #define CONFIG_SYS_MMC_ENV_DEV 0 100 #define CONFIG_ENV_SIZE 0x2000 101 #define CONFIG_ENV_OFFSET (512 * 1658) 102 #elif defined(CONFIG_NAND) 103 #define CONFIG_SYS_EXTRA_ENV_RELOC 104 #define CONFIG_ENV_IS_IN_NAND 105 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 106 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 107 #else 108 #define CONFIG_ENV_IS_IN_FLASH 109 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 110 #define CONFIG_ENV_SIZE 0x2000 111 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 112 #endif 113 #else /* CONFIG_SYS_NO_FLASH */ 114 #define CONFIG_ENV_SIZE 0x2000 115 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 116 #endif 117 118 #ifndef __ASSEMBLY__ 119 unsigned long get_board_sys_clk(void); 120 unsigned long get_board_ddr_clk(void); 121 #endif 122 123 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 124 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 125 126 /* 127 * These can be toggled for performance analysis, otherwise use default. 128 */ 129 #define CONFIG_SYS_CACHE_STASHING 130 #define CONFIG_BACKSIDE_L2_CACHE 131 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 132 #define CONFIG_BTB /* toggle branch predition */ 133 #define CONFIG_DDR_ECC 134 #ifdef CONFIG_DDR_ECC 135 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 136 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 137 #endif 138 139 #define CONFIG_ENABLE_36BIT_PHYS 140 141 #define CONFIG_ADDR_MAP 142 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 143 144 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 145 #define CONFIG_SYS_MEMTEST_END 0x00400000 146 #define CONFIG_SYS_ALT_MEMTEST 147 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 148 149 /* 150 * Config the L3 Cache as L3 SRAM 151 */ 152 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 153 154 #define CONFIG_SYS_DCSRBAR 0xf0000000 155 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 156 157 /* EEPROM */ 158 #define CONFIG_ID_EEPROM 159 #define CONFIG_SYS_I2C_EEPROM_NXID 160 #define CONFIG_SYS_EEPROM_BUS_NUM 0 161 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 162 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 163 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 164 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 165 166 /* 167 * DDR Setup 168 */ 169 #define CONFIG_VERY_BIG_RAM 170 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 171 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 172 173 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 174 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 175 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 176 177 #define CONFIG_DDR_SPD 178 #ifndef CONFIG_SYS_FSL_DDR4 179 #define CONFIG_SYS_FSL_DDR3 180 #endif 181 #define CONFIG_FSL_DDR_INTERACTIVE 182 183 #define CONFIG_SYS_SPD_BUS_NUM 0 184 #define SPD_EEPROM_ADDRESS 0x51 185 186 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 187 188 /* 189 * IFC Definitions 190 */ 191 #define CONFIG_SYS_FLASH_BASE 0xe0000000 192 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 193 194 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 195 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 196 + 0x8000000) | \ 197 CSPR_PORT_SIZE_16 | \ 198 CSPR_MSEL_NOR | \ 199 CSPR_V) 200 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 201 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 202 CSPR_PORT_SIZE_16 | \ 203 CSPR_MSEL_NOR | \ 204 CSPR_V) 205 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 206 207 /* 208 * TDM Definition 209 */ 210 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 211 212 /* NOR Flash Timing Params */ 213 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 214 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 215 FTIM0_NOR_TEADC(0x5) | \ 216 FTIM0_NOR_TEAHC(0x5)) 217 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 218 FTIM1_NOR_TRAD_NOR(0x1A) |\ 219 FTIM1_NOR_TSEQRAD_NOR(0x13)) 220 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 221 FTIM2_NOR_TCH(0x4) | \ 222 FTIM2_NOR_TWPH(0x0E) | \ 223 FTIM2_NOR_TWP(0x1c)) 224 #define CONFIG_SYS_NOR_FTIM3 0x0 225 226 #define CONFIG_SYS_FLASH_QUIET_TEST 227 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 228 229 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 230 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 231 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 232 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 233 234 #define CONFIG_SYS_FLASH_EMPTY_INFO 235 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 236 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 237 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 238 #define QIXIS_BASE 0xffdf0000 239 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 240 #define QIXIS_LBMAP_SWITCH 0x06 241 #define QIXIS_LBMAP_MASK 0x0f 242 #define QIXIS_LBMAP_SHIFT 0 243 #define QIXIS_LBMAP_DFLTBANK 0x00 244 #define QIXIS_LBMAP_ALTBANK 0x04 245 #define QIXIS_RST_CTL_RESET 0x31 246 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 247 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 248 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 249 #define QIXIS_RST_FORCE_MEM 0x01 250 251 #define CONFIG_SYS_CSPR3_EXT (0xf) 252 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 253 | CSPR_PORT_SIZE_8 \ 254 | CSPR_MSEL_GPCM \ 255 | CSPR_V) 256 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 257 #define CONFIG_SYS_CSOR3 0x0 258 /* QIXIS Timing parameters for IFC CS3 */ 259 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 260 FTIM0_GPCM_TEADC(0x0e) | \ 261 FTIM0_GPCM_TEAHC(0x0e)) 262 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 263 FTIM1_GPCM_TRAD(0x3f)) 264 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 265 FTIM2_GPCM_TCH(0x8) | \ 266 FTIM2_GPCM_TWP(0x1f)) 267 #define CONFIG_SYS_CS3_FTIM3 0x0 268 269 #define CONFIG_NAND_FSL_IFC 270 #define CONFIG_SYS_NAND_BASE 0xff800000 271 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 272 273 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 274 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 275 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 276 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 277 | CSPR_V) 278 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 279 280 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 281 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 282 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 283 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 284 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 285 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 286 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 287 288 #define CONFIG_SYS_NAND_ONFI_DETECTION 289 290 /* ONFI NAND Flash mode0 Timing Params */ 291 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 292 FTIM0_NAND_TWP(0x18) | \ 293 FTIM0_NAND_TWCHT(0x07) | \ 294 FTIM0_NAND_TWH(0x0a)) 295 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 296 FTIM1_NAND_TWBE(0x39) | \ 297 FTIM1_NAND_TRR(0x0e) | \ 298 FTIM1_NAND_TRP(0x18)) 299 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 300 FTIM2_NAND_TREH(0x0a) | \ 301 FTIM2_NAND_TWHRE(0x1e)) 302 #define CONFIG_SYS_NAND_FTIM3 0x0 303 304 #define CONFIG_SYS_NAND_DDR_LAW 11 305 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 306 #define CONFIG_SYS_MAX_NAND_DEVICE 1 307 #define CONFIG_CMD_NAND 308 309 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 310 311 #if defined(CONFIG_NAND) 312 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 313 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 314 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 315 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 316 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 317 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 318 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 319 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 320 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 321 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 322 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 323 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 324 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 325 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 326 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 327 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 328 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 329 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 330 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 331 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 332 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 333 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 334 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 335 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 336 #else 337 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 338 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 339 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 340 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 341 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 342 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 343 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 344 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 345 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 346 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 347 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 348 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 349 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 350 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 351 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 352 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 353 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 354 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 355 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 356 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 357 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 358 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 359 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 360 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 361 #endif 362 363 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 364 365 #if defined(CONFIG_RAMBOOT_PBL) 366 #define CONFIG_SYS_RAMBOOT 367 #endif 368 369 #define CONFIG_BOARD_EARLY_INIT_R 370 #define CONFIG_MISC_INIT_R 371 372 #define CONFIG_HWCONFIG 373 374 /* define to use L1 as initial stack */ 375 #define CONFIG_L1_INIT_RAM 376 #define CONFIG_SYS_INIT_RAM_LOCK 377 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 378 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 379 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 380 /* The assembler doesn't like typecast */ 381 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 382 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 383 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 384 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 385 386 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 387 GENERATED_GBL_DATA_SIZE) 388 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 389 390 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 391 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 392 393 /* Serial Port - controlled on board with jumper J8 394 * open - index 2 395 * shorted - index 1 396 */ 397 #define CONFIG_CONS_INDEX 1 398 #define CONFIG_SYS_NS16550_SERIAL 399 #define CONFIG_SYS_NS16550_REG_SIZE 1 400 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 401 402 #define CONFIG_SYS_BAUDRATE_TABLE \ 403 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 404 405 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 406 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 407 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 408 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 409 410 /* Video */ 411 #define CONFIG_FSL_DIU_FB 412 #ifdef CONFIG_FSL_DIU_FB 413 #define CONFIG_FSL_DIU_CH7301 414 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 415 #define CONFIG_CMD_BMP 416 #define CONFIG_VIDEO_SW_CURSOR 417 #define CONFIG_VIDEO_LOGO 418 #define CONFIG_VIDEO_BMP_LOGO 419 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 420 /* 421 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 422 * disable empty flash sector detection, which is I/O-intensive. 423 */ 424 #undef CONFIG_SYS_FLASH_EMPTY_INFO 425 #endif 426 427 /* I2C */ 428 #define CONFIG_SYS_I2C 429 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 430 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 431 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 432 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 433 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 434 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 435 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 436 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 437 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 438 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 439 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 440 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 441 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 442 443 #define I2C_MUX_PCA_ADDR 0x77 444 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 445 446 /* I2C bus multiplexer */ 447 #define I2C_MUX_CH_DEFAULT 0x8 448 #define I2C_MUX_CH_DIU 0xC 449 450 /* LDI/DVI Encoder for display */ 451 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 452 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 453 454 /* 455 * RTC configuration 456 */ 457 #define RTC 458 #define CONFIG_RTC_DS3231 1 459 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 460 461 /* 462 * eSPI - Enhanced SPI 463 */ 464 #define CONFIG_SF_DEFAULT_SPEED 10000000 465 #define CONFIG_SF_DEFAULT_MODE 0 466 467 /* 468 * General PCI 469 * Memory space is mapped 1-1, but I/O space must start from 0. 470 */ 471 472 #ifdef CONFIG_PCI 473 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 474 #ifdef CONFIG_PCIE1 475 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 476 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 477 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 478 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 479 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 480 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 481 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 482 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 483 #endif 484 485 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 486 #ifdef CONFIG_PCIE2 487 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 488 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 489 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 490 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 491 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 492 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 493 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 494 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 495 #endif 496 497 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 498 #ifdef CONFIG_PCIE3 499 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 500 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 501 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 502 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 503 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 504 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 505 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 506 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 507 #endif 508 509 /* controller 4, Base address 203000 */ 510 #ifdef CONFIG_PCIE4 511 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 512 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 513 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 514 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 515 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 516 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 517 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 518 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 519 #endif 520 521 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 522 523 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 524 #define CONFIG_DOS_PARTITION 525 #endif /* CONFIG_PCI */ 526 527 /* SATA */ 528 #define CONFIG_FSL_SATA_V2 529 #ifdef CONFIG_FSL_SATA_V2 530 #define CONFIG_LIBATA 531 #define CONFIG_FSL_SATA 532 533 #define CONFIG_SYS_SATA_MAX_DEVICE 2 534 #define CONFIG_SATA1 535 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 536 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 537 #define CONFIG_SATA2 538 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 539 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 540 541 #define CONFIG_LBA48 542 #define CONFIG_CMD_SATA 543 #define CONFIG_DOS_PARTITION 544 #endif 545 546 /* 547 * USB 548 */ 549 #define CONFIG_HAS_FSL_DR_USB 550 551 #ifdef CONFIG_HAS_FSL_DR_USB 552 #define CONFIG_USB_EHCI 553 554 #ifdef CONFIG_USB_EHCI 555 #define CONFIG_USB_EHCI_FSL 556 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 557 #endif 558 #endif 559 560 #define CONFIG_MMC 561 562 #ifdef CONFIG_MMC 563 #define CONFIG_FSL_ESDHC 564 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 565 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 566 #define CONFIG_GENERIC_MMC 567 #define CONFIG_DOS_PARTITION 568 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 569 #endif 570 571 /* Qman/Bman */ 572 #ifndef CONFIG_NOBQFMAN 573 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 574 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 575 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 576 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 577 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 578 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 579 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 580 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 581 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 582 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 583 CONFIG_SYS_BMAN_CENA_SIZE) 584 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 585 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 586 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 587 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 588 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 589 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 590 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 591 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 592 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 593 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 594 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 595 CONFIG_SYS_QMAN_CENA_SIZE) 596 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 597 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 598 599 #define CONFIG_SYS_DPAA_FMAN 600 #define CONFIG_SYS_DPAA_PME 601 602 #define CONFIG_QE 603 #define CONFIG_U_QE 604 /* Default address of microcode for the Linux Fman driver */ 605 #if defined(CONFIG_SPIFLASH) 606 /* 607 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 608 * env, so we got 0x110000. 609 */ 610 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 611 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 612 #elif defined(CONFIG_SDCARD) 613 /* 614 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 615 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 616 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 617 */ 618 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 619 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 620 #elif defined(CONFIG_NAND) 621 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 622 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 623 #else 624 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 625 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 626 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 627 #endif 628 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 629 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 630 #endif /* CONFIG_NOBQFMAN */ 631 632 #ifdef CONFIG_SYS_DPAA_FMAN 633 #define CONFIG_FMAN_ENET 634 #define CONFIG_PHYLIB_10G 635 #define CONFIG_PHY_VITESSE 636 #define CONFIG_PHY_REALTEK 637 #define CONFIG_PHY_TERANETICS 638 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 639 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 640 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 641 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 642 #endif 643 644 #ifdef CONFIG_FMAN_ENET 645 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 646 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 647 648 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 649 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 650 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 651 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 652 653 #define CONFIG_MII /* MII PHY management */ 654 #define CONFIG_ETHPRIME "FM1@DTSEC1" 655 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 656 #endif 657 658 /* Enable VSC9953 L2 Switch driver */ 659 #define CONFIG_VSC9953 660 #define CONFIG_CMD_ETHSW 661 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 662 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 663 664 /* 665 * Dynamic MTD Partition support with mtdparts 666 */ 667 #ifndef CONFIG_SYS_NO_FLASH 668 #define CONFIG_MTD_DEVICE 669 #define CONFIG_MTD_PARTITIONS 670 #define CONFIG_CMD_MTDPARTS 671 #define CONFIG_FLASH_CFI_MTD 672 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 673 "spi0=spife110000.0" 674 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 675 "128k(dtb),96m(fs),-(user);"\ 676 "fff800000.flash:2m(uboot),9m(kernel),"\ 677 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 678 "2m(uboot),9m(kernel),128k(dtb),-(user)" 679 #endif 680 681 /* 682 * Environment 683 */ 684 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 685 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 686 687 /* 688 * Command line configuration. 689 */ 690 #define CONFIG_CMD_DATE 691 #define CONFIG_CMD_EEPROM 692 #define CONFIG_CMD_ERRATA 693 #define CONFIG_CMD_IRQ 694 #define CONFIG_CMD_REGINFO 695 696 #ifdef CONFIG_PCI 697 #define CONFIG_CMD_PCI 698 #endif 699 700 /* Hash command with SHA acceleration supported in hardware */ 701 #ifdef CONFIG_FSL_CAAM 702 #define CONFIG_CMD_HASH 703 #define CONFIG_SHA_HW_ACCEL 704 #endif 705 706 /* 707 * Miscellaneous configurable options 708 */ 709 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 710 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 711 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 712 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 713 #ifdef CONFIG_CMD_KGDB 714 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 715 #else 716 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 717 #endif 718 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 719 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 720 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 721 722 /* 723 * For booting Linux, the board info and command line data 724 * have to be in the first 64 MB of memory, since this is 725 * the maximum mapped by the Linux kernel during initialization. 726 */ 727 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 728 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 729 730 #ifdef CONFIG_CMD_KGDB 731 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 732 #endif 733 734 /* 735 * Environment Configuration 736 */ 737 #define CONFIG_ROOTPATH "/opt/nfsroot" 738 #define CONFIG_BOOTFILE "uImage" 739 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 740 741 /* default location for tftp and bootm */ 742 #define CONFIG_LOADADDR 1000000 743 744 745 #define CONFIG_BAUDRATE 115200 746 747 #define __USB_PHY_TYPE utmi 748 749 #define CONFIG_EXTRA_ENV_SETTINGS \ 750 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 751 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 752 "netdev=eth0\0" \ 753 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 754 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 755 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 756 "tftpflash=tftpboot $loadaddr $uboot && " \ 757 "protect off $ubootaddr +$filesize && " \ 758 "erase $ubootaddr +$filesize && " \ 759 "cp.b $loadaddr $ubootaddr $filesize && " \ 760 "protect on $ubootaddr +$filesize && " \ 761 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 762 "consoledev=ttyS0\0" \ 763 "ramdiskaddr=2000000\0" \ 764 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 765 "fdtaddr=1e00000\0" \ 766 "fdtfile=t1040qds/t1040qds.dtb\0" \ 767 "bdev=sda3\0" 768 769 #define CONFIG_LINUX \ 770 "setenv bootargs root=/dev/ram rw " \ 771 "console=$consoledev,$baudrate $othbootargs;" \ 772 "setenv ramdiskaddr 0x02000000;" \ 773 "setenv fdtaddr 0x00c00000;" \ 774 "setenv loadaddr 0x1000000;" \ 775 "bootm $loadaddr $ramdiskaddr $fdtaddr" 776 777 #define CONFIG_HDBOOT \ 778 "setenv bootargs root=/dev/$bdev rw " \ 779 "console=$consoledev,$baudrate $othbootargs;" \ 780 "tftp $loadaddr $bootfile;" \ 781 "tftp $fdtaddr $fdtfile;" \ 782 "bootm $loadaddr - $fdtaddr" 783 784 #define CONFIG_NFSBOOTCOMMAND \ 785 "setenv bootargs root=/dev/nfs rw " \ 786 "nfsroot=$serverip:$rootpath " \ 787 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 788 "console=$consoledev,$baudrate $othbootargs;" \ 789 "tftp $loadaddr $bootfile;" \ 790 "tftp $fdtaddr $fdtfile;" \ 791 "bootm $loadaddr - $fdtaddr" 792 793 #define CONFIG_RAMBOOTCOMMAND \ 794 "setenv bootargs root=/dev/ram rw " \ 795 "console=$consoledev,$baudrate $othbootargs;" \ 796 "tftp $ramdiskaddr $ramdiskfile;" \ 797 "tftp $loadaddr $bootfile;" \ 798 "tftp $fdtaddr $fdtfile;" \ 799 "bootm $loadaddr $ramdiskaddr $fdtaddr" 800 801 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 802 803 #include <asm/fsl_secure_boot.h> 804 805 #endif /* __CONFIG_H */ 806