1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #ifdef CONFIG_PHYS_64BIT 24 #define CONFIG_ADDR_MAP 1 25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 26 #endif 27 28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 29 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 30 #define CONFIG_FSL_IFC /* Enable IFC Support */ 31 32 #define CONFIG_FSL_LAW /* Use common FSL init code */ 33 #define CONFIG_ENV_OVERWRITE 34 35 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 36 37 /* support deep sleep */ 38 #ifdef CONFIG_PPC_T1024 39 #define CONFIG_DEEP_SLEEP 40 #endif 41 #if defined(CONFIG_DEEP_SLEEP) 42 #define CONFIG_SILENT_CONSOLE 43 #define CONFIG_BOARD_EARLY_INIT_F 44 #endif 45 46 #ifdef CONFIG_RAMBOOT_PBL 47 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 48 #if defined(CONFIG_T1024RDB) 49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg 50 #elif defined(CONFIG_T1023RDB) 51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg 52 #endif 53 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 54 #define CONFIG_SPL_ENV_SUPPORT 55 #define CONFIG_SPL_SERIAL_SUPPORT 56 #define CONFIG_SPL_FLUSH_IMAGE 57 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 58 #define CONFIG_SPL_LIBGENERIC_SUPPORT 59 #define CONFIG_SPL_LIBCOMMON_SUPPORT 60 #define CONFIG_SPL_I2C_SUPPORT 61 #define CONFIG_FSL_LAW /* Use common FSL init code */ 62 #define CONFIG_SYS_TEXT_BASE 0x30001000 63 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 64 #define CONFIG_SPL_PAD_TO 0x40000 65 #define CONFIG_SPL_MAX_SIZE 0x28000 66 #define RESET_VECTOR_OFFSET 0x27FFC 67 #define BOOT_PAGE_OFFSET 0x27000 68 #ifdef CONFIG_SPL_BUILD 69 #define CONFIG_SPL_SKIP_RELOCATE 70 #define CONFIG_SPL_COMMON_INIT_DDR 71 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 72 #define CONFIG_SYS_NO_FLASH 73 #endif 74 75 #ifdef CONFIG_NAND 76 #define CONFIG_SPL_NAND_SUPPORT 77 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 78 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 79 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 80 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 81 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 82 #define CONFIG_SPL_NAND_BOOT 83 #endif 84 85 #ifdef CONFIG_SPIFLASH 86 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 87 #define CONFIG_SPL_SPI_SUPPORT 88 #define CONFIG_SPL_SPI_FLASH_SUPPORT 89 #define CONFIG_SPL_SPI_FLASH_MINIMAL 90 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 94 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 95 #ifndef CONFIG_SPL_BUILD 96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 97 #endif 98 #define CONFIG_SPL_SPI_BOOT 99 #endif 100 101 #ifdef CONFIG_SDCARD 102 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 103 #define CONFIG_SPL_MMC_SUPPORT 104 #define CONFIG_SPL_MMC_MINIMAL 105 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 106 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 107 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 108 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 109 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 110 #ifndef CONFIG_SPL_BUILD 111 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 112 #endif 113 #define CONFIG_SPL_MMC_BOOT 114 #endif 115 116 #endif /* CONFIG_RAMBOOT_PBL */ 117 118 #ifndef CONFIG_SYS_TEXT_BASE 119 #define CONFIG_SYS_TEXT_BASE 0xeff40000 120 #endif 121 122 #ifndef CONFIG_RESET_VECTOR_ADDRESS 123 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 124 #endif 125 126 #ifndef CONFIG_SYS_NO_FLASH 127 #define CONFIG_FLASH_CFI_DRIVER 128 #define CONFIG_SYS_FLASH_CFI 129 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 130 #endif 131 132 /* PCIe Boot - Master */ 133 #define CONFIG_SRIO_PCIE_BOOT_MASTER 134 /* 135 * for slave u-boot IMAGE instored in master memory space, 136 * PHYS must be aligned based on the SIZE 137 */ 138 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 139 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 140 #ifdef CONFIG_PHYS_64BIT 141 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 142 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 143 #else 144 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 145 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 146 #endif 147 /* 148 * for slave UCODE and ENV instored in master memory space, 149 * PHYS must be aligned based on the SIZE 150 */ 151 #ifdef CONFIG_PHYS_64BIT 152 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 153 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 154 #else 155 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 156 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 157 #endif 158 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 159 /* slave core release by master*/ 160 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 161 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 162 163 /* PCIe Boot - Slave */ 164 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 165 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 166 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 167 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 168 /* Set 1M boot space for PCIe boot */ 169 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 170 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 171 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 172 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 173 #define CONFIG_SYS_NO_FLASH 174 #endif 175 176 #if defined(CONFIG_SPIFLASH) 177 #define CONFIG_SYS_EXTRA_ENV_RELOC 178 #define CONFIG_ENV_IS_IN_SPI_FLASH 179 #define CONFIG_ENV_SPI_BUS 0 180 #define CONFIG_ENV_SPI_CS 0 181 #define CONFIG_ENV_SPI_MAX_HZ 10000000 182 #define CONFIG_ENV_SPI_MODE 0 183 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 184 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 185 #if defined(CONFIG_T1024RDB) 186 #define CONFIG_ENV_SECT_SIZE 0x10000 187 #elif defined(CONFIG_T1023RDB) 188 #define CONFIG_ENV_SECT_SIZE 0x40000 189 #endif 190 #elif defined(CONFIG_SDCARD) 191 #define CONFIG_SYS_EXTRA_ENV_RELOC 192 #define CONFIG_ENV_IS_IN_MMC 193 #define CONFIG_SYS_MMC_ENV_DEV 0 194 #define CONFIG_ENV_SIZE 0x2000 195 #define CONFIG_ENV_OFFSET (512 * 0x800) 196 #elif defined(CONFIG_NAND) 197 #define CONFIG_SYS_EXTRA_ENV_RELOC 198 #define CONFIG_ENV_IS_IN_NAND 199 #define CONFIG_ENV_SIZE 0x2000 200 #if defined(CONFIG_T1024RDB) 201 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 202 #elif defined(CONFIG_T1023RDB) 203 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 204 #endif 205 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 206 #define CONFIG_ENV_IS_IN_REMOTE 207 #define CONFIG_ENV_ADDR 0xffe20000 208 #define CONFIG_ENV_SIZE 0x2000 209 #elif defined(CONFIG_ENV_IS_NOWHERE) 210 #define CONFIG_ENV_SIZE 0x2000 211 #else 212 #define CONFIG_ENV_IS_IN_FLASH 213 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 214 #define CONFIG_ENV_SIZE 0x2000 215 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 216 #endif 217 218 #ifndef __ASSEMBLY__ 219 unsigned long get_board_sys_clk(void); 220 unsigned long get_board_ddr_clk(void); 221 #endif 222 223 #define CONFIG_SYS_CLK_FREQ 100000000 224 #define CONFIG_DDR_CLK_FREQ 100000000 225 226 /* 227 * These can be toggled for performance analysis, otherwise use default. 228 */ 229 #define CONFIG_SYS_CACHE_STASHING 230 #define CONFIG_BACKSIDE_L2_CACHE 231 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 232 #define CONFIG_BTB /* toggle branch predition */ 233 #define CONFIG_DDR_ECC 234 #ifdef CONFIG_DDR_ECC 235 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 236 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 237 #endif 238 239 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 240 #define CONFIG_SYS_MEMTEST_END 0x00400000 241 #define CONFIG_SYS_ALT_MEMTEST 242 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 243 244 /* 245 * Config the L3 Cache as L3 SRAM 246 */ 247 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 248 #define CONFIG_SYS_L3_SIZE (256 << 10) 249 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 250 #ifdef CONFIG_RAMBOOT_PBL 251 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 252 #endif 253 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 254 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 255 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 256 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 257 258 #ifdef CONFIG_PHYS_64BIT 259 #define CONFIG_SYS_DCSRBAR 0xf0000000 260 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 261 #endif 262 263 /* EEPROM */ 264 #define CONFIG_ID_EEPROM 265 #define CONFIG_SYS_I2C_EEPROM_NXID 266 #define CONFIG_SYS_EEPROM_BUS_NUM 0 267 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 268 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 269 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 270 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 271 272 /* 273 * DDR Setup 274 */ 275 #define CONFIG_VERY_BIG_RAM 276 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 277 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 278 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 279 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 280 #define CONFIG_FSL_DDR_INTERACTIVE 281 #if defined(CONFIG_T1024RDB) 282 #define CONFIG_DDR_SPD 283 #define CONFIG_SYS_FSL_DDR3 284 #define CONFIG_SYS_SPD_BUS_NUM 0 285 #define SPD_EEPROM_ADDRESS 0x51 286 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 287 #elif defined(CONFIG_T1023RDB) 288 #define CONFIG_SYS_FSL_DDR4 289 #define CONFIG_SYS_DDR_RAW_TIMING 290 #define CONFIG_SYS_SDRAM_SIZE 2048 291 #endif 292 293 /* 294 * IFC Definitions 295 */ 296 #define CONFIG_SYS_FLASH_BASE 0xe8000000 297 #ifdef CONFIG_PHYS_64BIT 298 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 299 #else 300 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 301 #endif 302 303 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 304 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 305 CSPR_PORT_SIZE_16 | \ 306 CSPR_MSEL_NOR | \ 307 CSPR_V) 308 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 309 310 /* NOR Flash Timing Params */ 311 #if defined(CONFIG_T1024RDB) 312 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 313 #elif defined(CONFIG_T1023RDB) 314 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 315 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 316 #endif 317 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 318 FTIM0_NOR_TEADC(0x5) | \ 319 FTIM0_NOR_TEAHC(0x5)) 320 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 321 FTIM1_NOR_TRAD_NOR(0x1A) |\ 322 FTIM1_NOR_TSEQRAD_NOR(0x13)) 323 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 324 FTIM2_NOR_TCH(0x4) | \ 325 FTIM2_NOR_TWPH(0x0E) | \ 326 FTIM2_NOR_TWP(0x1c)) 327 #define CONFIG_SYS_NOR_FTIM3 0x0 328 329 #define CONFIG_SYS_FLASH_QUIET_TEST 330 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 331 332 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 333 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 334 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 335 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 336 337 #define CONFIG_SYS_FLASH_EMPTY_INFO 338 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 339 340 #ifdef CONFIG_T1024RDB 341 /* CPLD on IFC */ 342 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 343 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 344 #define CONFIG_SYS_CSPR2_EXT (0xf) 345 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 346 | CSPR_PORT_SIZE_8 \ 347 | CSPR_MSEL_GPCM \ 348 | CSPR_V) 349 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 350 #define CONFIG_SYS_CSOR2 0x0 351 352 /* CPLD Timing parameters for IFC CS2 */ 353 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 354 FTIM0_GPCM_TEADC(0x0e) | \ 355 FTIM0_GPCM_TEAHC(0x0e)) 356 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 357 FTIM1_GPCM_TRAD(0x1f)) 358 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 359 FTIM2_GPCM_TCH(0x8) | \ 360 FTIM2_GPCM_TWP(0x1f)) 361 #define CONFIG_SYS_CS2_FTIM3 0x0 362 #endif 363 364 /* NAND Flash on IFC */ 365 #define CONFIG_NAND_FSL_IFC 366 #define CONFIG_SYS_NAND_BASE 0xff800000 367 #ifdef CONFIG_PHYS_64BIT 368 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 369 #else 370 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 371 #endif 372 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 373 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 374 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 375 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 376 | CSPR_V) 377 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 378 379 #if defined(CONFIG_T1024RDB) 380 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 381 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 382 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 383 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 384 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 385 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 386 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 387 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 388 #elif defined(CONFIG_T1023RDB) 389 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 390 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 391 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 392 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 393 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 394 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 395 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 396 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 397 #endif 398 399 #define CONFIG_SYS_NAND_ONFI_DETECTION 400 /* ONFI NAND Flash mode0 Timing Params */ 401 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 402 FTIM0_NAND_TWP(0x18) | \ 403 FTIM0_NAND_TWCHT(0x07) | \ 404 FTIM0_NAND_TWH(0x0a)) 405 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 406 FTIM1_NAND_TWBE(0x39) | \ 407 FTIM1_NAND_TRR(0x0e) | \ 408 FTIM1_NAND_TRP(0x18)) 409 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 410 FTIM2_NAND_TREH(0x0a) | \ 411 FTIM2_NAND_TWHRE(0x1e)) 412 #define CONFIG_SYS_NAND_FTIM3 0x0 413 414 #define CONFIG_SYS_NAND_DDR_LAW 11 415 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 416 #define CONFIG_SYS_MAX_NAND_DEVICE 1 417 #define CONFIG_CMD_NAND 418 419 #if defined(CONFIG_NAND) 420 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 421 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 422 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 423 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 424 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 425 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 426 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 427 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 428 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 429 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 430 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 431 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 432 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 433 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 434 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 435 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 436 #else 437 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 438 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 439 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 440 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 441 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 442 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 443 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 444 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 445 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 446 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 447 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 448 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 449 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 450 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 451 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 452 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 453 #endif 454 455 #ifdef CONFIG_SPL_BUILD 456 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 457 #else 458 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 459 #endif 460 461 #if defined(CONFIG_RAMBOOT_PBL) 462 #define CONFIG_SYS_RAMBOOT 463 #endif 464 465 #define CONFIG_BOARD_EARLY_INIT_R 466 #define CONFIG_MISC_INIT_R 467 468 #define CONFIG_HWCONFIG 469 470 /* define to use L1 as initial stack */ 471 #define CONFIG_L1_INIT_RAM 472 #define CONFIG_SYS_INIT_RAM_LOCK 473 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 474 #ifdef CONFIG_PHYS_64BIT 475 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 476 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 477 /* The assembler doesn't like typecast */ 478 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 479 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 480 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 481 #else 482 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 483 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 484 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 485 #endif 486 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 487 488 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 489 GENERATED_GBL_DATA_SIZE) 490 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 491 492 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 493 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 494 495 /* Serial Port */ 496 #define CONFIG_CONS_INDEX 1 497 #define CONFIG_SYS_NS16550_SERIAL 498 #define CONFIG_SYS_NS16550_REG_SIZE 1 499 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 500 501 #define CONFIG_SYS_BAUDRATE_TABLE \ 502 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 503 504 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 505 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 506 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 507 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 508 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 509 510 /* Video */ 511 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 512 #ifdef CONFIG_FSL_DIU_FB 513 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 514 #define CONFIG_VIDEO 515 #define CONFIG_CMD_BMP 516 #define CONFIG_CFB_CONSOLE 517 #define CONFIG_VIDEO_SW_CURSOR 518 #define CONFIG_VGA_AS_SINGLE_DEVICE 519 #define CONFIG_VIDEO_LOGO 520 #define CONFIG_VIDEO_BMP_LOGO 521 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 522 /* 523 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 524 * disable empty flash sector detection, which is I/O-intensive. 525 */ 526 #undef CONFIG_SYS_FLASH_EMPTY_INFO 527 #endif 528 529 /* I2C */ 530 #define CONFIG_SYS_I2C 531 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 532 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 533 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 534 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 535 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 536 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 537 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 538 539 #define I2C_PCA6408_BUS_NUM 1 540 #define I2C_PCA6408_ADDR 0x20 541 542 /* I2C bus multiplexer */ 543 #define I2C_MUX_CH_DEFAULT 0x8 544 545 /* 546 * RTC configuration 547 */ 548 #define RTC 549 #define CONFIG_RTC_DS1337 1 550 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 551 552 /* 553 * eSPI - Enhanced SPI 554 */ 555 #define CONFIG_SPI_FLASH_BAR 556 #define CONFIG_SF_DEFAULT_SPEED 10000000 557 #define CONFIG_SF_DEFAULT_MODE 0 558 559 /* 560 * General PCIe 561 * Memory space is mapped 1-1, but I/O space must start from 0. 562 */ 563 #define CONFIG_PCI /* Enable PCI/PCIE */ 564 #define CONFIG_PCIE1 /* PCIE controller 1 */ 565 #define CONFIG_PCIE2 /* PCIE controller 2 */ 566 #define CONFIG_PCIE3 /* PCIE controller 3 */ 567 #ifdef CONFIG_PPC_T1040 568 #define CONFIG_PCIE4 /* PCIE controller 4 */ 569 #endif 570 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 571 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 572 #define CONFIG_PCI_INDIRECT_BRIDGE 573 574 #ifdef CONFIG_PCI 575 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 576 #ifdef CONFIG_PCIE1 577 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 578 #ifdef CONFIG_PHYS_64BIT 579 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 580 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 581 #else 582 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 583 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 584 #endif 585 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 586 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 587 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 588 #ifdef CONFIG_PHYS_64BIT 589 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 590 #else 591 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 592 #endif 593 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 594 #endif 595 596 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 597 #ifdef CONFIG_PCIE2 598 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 599 #ifdef CONFIG_PHYS_64BIT 600 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 601 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 602 #else 603 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 604 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 605 #endif 606 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 607 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 608 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 609 #ifdef CONFIG_PHYS_64BIT 610 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 611 #else 612 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 613 #endif 614 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 615 #endif 616 617 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 618 #ifdef CONFIG_PCIE3 619 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 620 #ifdef CONFIG_PHYS_64BIT 621 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 622 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 623 #else 624 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 625 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 626 #endif 627 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 628 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 629 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 630 #ifdef CONFIG_PHYS_64BIT 631 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 632 #else 633 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 634 #endif 635 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 636 #endif 637 638 /* controller 4, Base address 203000, to be removed */ 639 #ifdef CONFIG_PCIE4 640 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 641 #ifdef CONFIG_PHYS_64BIT 642 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 643 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 644 #else 645 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 646 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 647 #endif 648 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 649 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 650 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 651 #ifdef CONFIG_PHYS_64BIT 652 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 653 #else 654 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 655 #endif 656 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 657 #endif 658 659 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 660 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 661 #define CONFIG_DOS_PARTITION 662 #endif /* CONFIG_PCI */ 663 664 /* 665 * USB 666 */ 667 #define CONFIG_HAS_FSL_DR_USB 668 669 #ifdef CONFIG_HAS_FSL_DR_USB 670 #define CONFIG_USB_EHCI 671 #define CONFIG_USB_EHCI_FSL 672 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 673 #endif 674 675 /* 676 * SDHC 677 */ 678 #define CONFIG_MMC 679 #ifdef CONFIG_MMC 680 #define CONFIG_FSL_ESDHC 681 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 682 #define CONFIG_GENERIC_MMC 683 #define CONFIG_DOS_PARTITION 684 #endif 685 686 /* Qman/Bman */ 687 #ifndef CONFIG_NOBQFMAN 688 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 689 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 690 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 691 #ifdef CONFIG_PHYS_64BIT 692 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 693 #else 694 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 695 #endif 696 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 697 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 698 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 699 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 700 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 701 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 702 CONFIG_SYS_BMAN_CENA_SIZE) 703 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 704 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 705 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 706 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 707 #ifdef CONFIG_PHYS_64BIT 708 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 709 #else 710 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 711 #endif 712 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 713 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 714 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 715 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 716 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 717 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 718 CONFIG_SYS_QMAN_CENA_SIZE) 719 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 720 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 721 722 #define CONFIG_SYS_DPAA_FMAN 723 724 #ifdef CONFIG_T1024RDB 725 #define CONFIG_QE 726 #define CONFIG_U_QE 727 #endif 728 /* Default address of microcode for the Linux FMan driver */ 729 #if defined(CONFIG_SPIFLASH) 730 /* 731 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 732 * env, so we got 0x110000. 733 */ 734 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 735 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 736 #define CONFIG_SYS_QE_FW_ADDR 0x130000 737 #elif defined(CONFIG_SDCARD) 738 /* 739 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 740 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 741 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 742 */ 743 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 744 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 745 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 746 #elif defined(CONFIG_NAND) 747 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 748 #if defined(CONFIG_T1024RDB) 749 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 750 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 751 #elif defined(CONFIG_T1023RDB) 752 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 753 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 754 #endif 755 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 756 /* 757 * Slave has no ucode locally, it can fetch this from remote. When implementing 758 * in two corenet boards, slave's ucode could be stored in master's memory 759 * space, the address can be mapped from slave TLB->slave LAW-> 760 * slave SRIO or PCIE outbound window->master inbound window-> 761 * master LAW->the ucode address in master's memory space. 762 */ 763 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 764 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 765 #else 766 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 767 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 768 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 769 #endif 770 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 771 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 772 #endif /* CONFIG_NOBQFMAN */ 773 774 #ifdef CONFIG_SYS_DPAA_FMAN 775 #define CONFIG_FMAN_ENET 776 #define CONFIG_PHYLIB_10G 777 #define CONFIG_PHY_REALTEK 778 #define CONFIG_PHY_AQUANTIA 779 #if defined(CONFIG_T1024RDB) 780 #define RGMII_PHY1_ADDR 0x2 781 #define RGMII_PHY2_ADDR 0x6 782 #define SGMII_AQR_PHY_ADDR 0x2 783 #define FM1_10GEC1_PHY_ADDR 0x1 784 #elif defined(CONFIG_T1023RDB) 785 #define RGMII_PHY1_ADDR 0x1 786 #define SGMII_RTK_PHY_ADDR 0x3 787 #define SGMII_AQR_PHY_ADDR 0x2 788 #endif 789 #endif 790 791 #ifdef CONFIG_FMAN_ENET 792 #define CONFIG_MII /* MII PHY management */ 793 #define CONFIG_ETHPRIME "FM1@DTSEC4" 794 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 795 #endif 796 797 /* 798 * Dynamic MTD Partition support with mtdparts 799 */ 800 #ifndef CONFIG_SYS_NO_FLASH 801 #define CONFIG_MTD_DEVICE 802 #define CONFIG_MTD_PARTITIONS 803 #define CONFIG_CMD_MTDPARTS 804 #define CONFIG_FLASH_CFI_MTD 805 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 806 "spi0=spife110000.1" 807 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 808 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 809 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 810 "1m(uboot),5m(kernel),128k(dtb),-(user)" 811 #endif 812 813 /* 814 * Environment 815 */ 816 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 817 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 818 819 /* 820 * Command line configuration. 821 */ 822 #define CONFIG_CMD_DATE 823 #define CONFIG_CMD_EEPROM 824 #define CONFIG_CMD_ERRATA 825 #define CONFIG_CMD_IRQ 826 #define CONFIG_CMD_REGINFO 827 828 #ifdef CONFIG_PCI 829 #define CONFIG_CMD_PCI 830 #endif 831 832 /* 833 * Miscellaneous configurable options 834 */ 835 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 836 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 837 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 838 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 839 #ifdef CONFIG_CMD_KGDB 840 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 841 #else 842 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 843 #endif 844 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 845 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 846 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 847 848 /* 849 * For booting Linux, the board info and command line data 850 * have to be in the first 64 MB of memory, since this is 851 * the maximum mapped by the Linux kernel during initialization. 852 */ 853 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 854 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 855 856 #ifdef CONFIG_CMD_KGDB 857 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 858 #endif 859 860 /* 861 * Environment Configuration 862 */ 863 #define CONFIG_ROOTPATH "/opt/nfsroot" 864 #define CONFIG_BOOTFILE "uImage" 865 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 866 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 867 #define CONFIG_BAUDRATE 115200 868 #define __USB_PHY_TYPE utmi 869 870 #ifdef CONFIG_PPC_T1024 871 #define CONFIG_BOARDNAME t1024rdb 872 #define BANK_INTLV cs0_cs1 873 #else 874 #define CONFIG_BOARDNAME t1023rdb 875 #define BANK_INTLV null 876 #endif 877 878 #define CONFIG_EXTRA_ENV_SETTINGS \ 879 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 880 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 881 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 882 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 883 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 884 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 885 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 886 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 887 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 888 "netdev=eth0\0" \ 889 "tftpflash=tftpboot $loadaddr $uboot && " \ 890 "protect off $ubootaddr +$filesize && " \ 891 "erase $ubootaddr +$filesize && " \ 892 "cp.b $loadaddr $ubootaddr $filesize && " \ 893 "protect on $ubootaddr +$filesize && " \ 894 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 895 "consoledev=ttyS0\0" \ 896 "ramdiskaddr=2000000\0" \ 897 "fdtaddr=1e00000\0" \ 898 "bdev=sda3\0" 899 900 #define CONFIG_LINUX \ 901 "setenv bootargs root=/dev/ram rw " \ 902 "console=$consoledev,$baudrate $othbootargs;" \ 903 "setenv ramdiskaddr 0x02000000;" \ 904 "setenv fdtaddr 0x00c00000;" \ 905 "setenv loadaddr 0x1000000;" \ 906 "bootm $loadaddr $ramdiskaddr $fdtaddr" 907 908 #define CONFIG_NFSBOOTCOMMAND \ 909 "setenv bootargs root=/dev/nfs rw " \ 910 "nfsroot=$serverip:$rootpath " \ 911 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 912 "console=$consoledev,$baudrate $othbootargs;" \ 913 "tftp $loadaddr $bootfile;" \ 914 "tftp $fdtaddr $fdtfile;" \ 915 "bootm $loadaddr - $fdtaddr" 916 917 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 918 919 /* Hash command with SHA acceleration supported in hardware */ 920 #ifdef CONFIG_FSL_CAAM 921 #define CONFIG_CMD_HASH 922 #define CONFIG_SHA_HW_ACCEL 923 #endif 924 925 #include <asm/fsl_secure_boot.h> 926 927 #endif /* __T1024RDB_H */ 928