1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_PHYS_64BIT 22 #define CONFIG_ENABLE_36BIT_PHYS 23 24 #ifdef CONFIG_PHYS_64BIT 25 #define CONFIG_ADDR_MAP 1 26 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 27 #endif 28 29 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 30 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 31 #define CONFIG_FSL_IFC /* Enable IFC Support */ 32 33 #define CONFIG_FSL_LAW /* Use common FSL init code */ 34 #define CONFIG_ENV_OVERWRITE 35 36 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 37 38 /* support deep sleep */ 39 #ifdef CONFIG_PPC_T1024 40 #define CONFIG_DEEP_SLEEP 41 #endif 42 #if defined(CONFIG_DEEP_SLEEP) 43 #define CONFIG_SILENT_CONSOLE 44 #define CONFIG_BOARD_EARLY_INIT_F 45 #endif 46 47 #ifdef CONFIG_RAMBOOT_PBL 48 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 49 #if defined(CONFIG_T1024RDB) 50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg 51 #elif defined(CONFIG_T1023RDB) 52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg 53 #endif 54 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 55 #define CONFIG_SPL_ENV_SUPPORT 56 #define CONFIG_SPL_SERIAL_SUPPORT 57 #define CONFIG_SPL_FLUSH_IMAGE 58 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 59 #define CONFIG_SPL_LIBGENERIC_SUPPORT 60 #define CONFIG_SPL_LIBCOMMON_SUPPORT 61 #define CONFIG_SPL_I2C_SUPPORT 62 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 63 #define CONFIG_FSL_LAW /* Use common FSL init code */ 64 #define CONFIG_SYS_TEXT_BASE 0x30001000 65 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 66 #define CONFIG_SPL_PAD_TO 0x40000 67 #define CONFIG_SPL_MAX_SIZE 0x28000 68 #define RESET_VECTOR_OFFSET 0x27FFC 69 #define BOOT_PAGE_OFFSET 0x27000 70 #ifdef CONFIG_SPL_BUILD 71 #define CONFIG_SPL_SKIP_RELOCATE 72 #define CONFIG_SPL_COMMON_INIT_DDR 73 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 74 #define CONFIG_SYS_NO_FLASH 75 #endif 76 77 #ifdef CONFIG_NAND 78 #define CONFIG_SPL_NAND_SUPPORT 79 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 80 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 81 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 82 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 83 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 84 #define CONFIG_SPL_NAND_BOOT 85 #endif 86 87 #ifdef CONFIG_SPIFLASH 88 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 89 #define CONFIG_SPL_SPI_SUPPORT 90 #define CONFIG_SPL_SPI_FLASH_SUPPORT 91 #define CONFIG_SPL_SPI_FLASH_MINIMAL 92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 94 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 95 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 96 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 97 #ifndef CONFIG_SPL_BUILD 98 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 99 #endif 100 #define CONFIG_SPL_SPI_BOOT 101 #endif 102 103 #ifdef CONFIG_SDCARD 104 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 105 #define CONFIG_SPL_MMC_SUPPORT 106 #define CONFIG_SPL_MMC_MINIMAL 107 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 108 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 109 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 110 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 111 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 112 #ifndef CONFIG_SPL_BUILD 113 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 114 #endif 115 #define CONFIG_SPL_MMC_BOOT 116 #endif 117 118 #endif /* CONFIG_RAMBOOT_PBL */ 119 120 #ifndef CONFIG_SYS_TEXT_BASE 121 #define CONFIG_SYS_TEXT_BASE 0xeff40000 122 #endif 123 124 #ifndef CONFIG_RESET_VECTOR_ADDRESS 125 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 126 #endif 127 128 #ifndef CONFIG_SYS_NO_FLASH 129 #define CONFIG_FLASH_CFI_DRIVER 130 #define CONFIG_SYS_FLASH_CFI 131 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 132 #endif 133 134 /* PCIe Boot - Master */ 135 #define CONFIG_SRIO_PCIE_BOOT_MASTER 136 /* 137 * for slave u-boot IMAGE instored in master memory space, 138 * PHYS must be aligned based on the SIZE 139 */ 140 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 141 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 142 #ifdef CONFIG_PHYS_64BIT 143 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 144 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 145 #else 146 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 147 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 148 #endif 149 /* 150 * for slave UCODE and ENV instored in master memory space, 151 * PHYS must be aligned based on the SIZE 152 */ 153 #ifdef CONFIG_PHYS_64BIT 154 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 155 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 156 #else 157 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 158 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 159 #endif 160 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 161 /* slave core release by master*/ 162 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 163 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 164 165 /* PCIe Boot - Slave */ 166 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 167 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 168 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 169 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 170 /* Set 1M boot space for PCIe boot */ 171 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 172 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 173 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 174 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 175 #define CONFIG_SYS_NO_FLASH 176 #endif 177 178 #if defined(CONFIG_SPIFLASH) 179 #define CONFIG_SYS_EXTRA_ENV_RELOC 180 #define CONFIG_ENV_IS_IN_SPI_FLASH 181 #define CONFIG_ENV_SPI_BUS 0 182 #define CONFIG_ENV_SPI_CS 0 183 #define CONFIG_ENV_SPI_MAX_HZ 10000000 184 #define CONFIG_ENV_SPI_MODE 0 185 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 186 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 187 #if defined(CONFIG_T1024RDB) 188 #define CONFIG_ENV_SECT_SIZE 0x10000 189 #elif defined(CONFIG_T1023RDB) 190 #define CONFIG_ENV_SECT_SIZE 0x40000 191 #endif 192 #elif defined(CONFIG_SDCARD) 193 #define CONFIG_SYS_EXTRA_ENV_RELOC 194 #define CONFIG_ENV_IS_IN_MMC 195 #define CONFIG_SYS_MMC_ENV_DEV 0 196 #define CONFIG_ENV_SIZE 0x2000 197 #define CONFIG_ENV_OFFSET (512 * 0x800) 198 #elif defined(CONFIG_NAND) 199 #define CONFIG_SYS_EXTRA_ENV_RELOC 200 #define CONFIG_ENV_IS_IN_NAND 201 #define CONFIG_ENV_SIZE 0x2000 202 #if defined(CONFIG_T1024RDB) 203 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 204 #elif defined(CONFIG_T1023RDB) 205 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 206 #endif 207 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 208 #define CONFIG_ENV_IS_IN_REMOTE 209 #define CONFIG_ENV_ADDR 0xffe20000 210 #define CONFIG_ENV_SIZE 0x2000 211 #elif defined(CONFIG_ENV_IS_NOWHERE) 212 #define CONFIG_ENV_SIZE 0x2000 213 #else 214 #define CONFIG_ENV_IS_IN_FLASH 215 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 216 #define CONFIG_ENV_SIZE 0x2000 217 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 218 #endif 219 220 #ifndef __ASSEMBLY__ 221 unsigned long get_board_sys_clk(void); 222 unsigned long get_board_ddr_clk(void); 223 #endif 224 225 #define CONFIG_SYS_CLK_FREQ 100000000 226 #define CONFIG_DDR_CLK_FREQ 100000000 227 228 /* 229 * These can be toggled for performance analysis, otherwise use default. 230 */ 231 #define CONFIG_SYS_CACHE_STASHING 232 #define CONFIG_BACKSIDE_L2_CACHE 233 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 234 #define CONFIG_BTB /* toggle branch predition */ 235 #define CONFIG_DDR_ECC 236 #ifdef CONFIG_DDR_ECC 237 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 238 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 239 #endif 240 241 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 242 #define CONFIG_SYS_MEMTEST_END 0x00400000 243 #define CONFIG_SYS_ALT_MEMTEST 244 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 245 246 /* 247 * Config the L3 Cache as L3 SRAM 248 */ 249 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 250 #define CONFIG_SYS_L3_SIZE (256 << 10) 251 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 252 #ifdef CONFIG_RAMBOOT_PBL 253 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 254 #endif 255 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 256 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 257 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 258 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 259 260 #ifdef CONFIG_PHYS_64BIT 261 #define CONFIG_SYS_DCSRBAR 0xf0000000 262 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 263 #endif 264 265 /* EEPROM */ 266 #define CONFIG_ID_EEPROM 267 #define CONFIG_SYS_I2C_EEPROM_NXID 268 #define CONFIG_SYS_EEPROM_BUS_NUM 0 269 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 270 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 271 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 272 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 273 274 /* 275 * DDR Setup 276 */ 277 #define CONFIG_VERY_BIG_RAM 278 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 279 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 280 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 281 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 282 #define CONFIG_FSL_DDR_INTERACTIVE 283 #if defined(CONFIG_T1024RDB) 284 #define CONFIG_DDR_SPD 285 #define CONFIG_SYS_FSL_DDR3 286 #define CONFIG_SYS_SPD_BUS_NUM 0 287 #define SPD_EEPROM_ADDRESS 0x51 288 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 289 #elif defined(CONFIG_T1023RDB) 290 #define CONFIG_SYS_FSL_DDR4 291 #define CONFIG_SYS_DDR_RAW_TIMING 292 #define CONFIG_SYS_SDRAM_SIZE 2048 293 #endif 294 295 /* 296 * IFC Definitions 297 */ 298 #define CONFIG_SYS_FLASH_BASE 0xe8000000 299 #ifdef CONFIG_PHYS_64BIT 300 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 301 #else 302 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 303 #endif 304 305 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 306 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 307 CSPR_PORT_SIZE_16 | \ 308 CSPR_MSEL_NOR | \ 309 CSPR_V) 310 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 311 312 /* NOR Flash Timing Params */ 313 #if defined(CONFIG_T1024RDB) 314 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 315 #elif defined(CONFIG_T1023RDB) 316 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 317 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 318 #endif 319 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 320 FTIM0_NOR_TEADC(0x5) | \ 321 FTIM0_NOR_TEAHC(0x5)) 322 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 323 FTIM1_NOR_TRAD_NOR(0x1A) |\ 324 FTIM1_NOR_TSEQRAD_NOR(0x13)) 325 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 326 FTIM2_NOR_TCH(0x4) | \ 327 FTIM2_NOR_TWPH(0x0E) | \ 328 FTIM2_NOR_TWP(0x1c)) 329 #define CONFIG_SYS_NOR_FTIM3 0x0 330 331 #define CONFIG_SYS_FLASH_QUIET_TEST 332 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 333 334 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 335 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 336 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 337 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 338 339 #define CONFIG_SYS_FLASH_EMPTY_INFO 340 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 341 342 #ifdef CONFIG_T1024RDB 343 /* CPLD on IFC */ 344 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 345 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 346 #define CONFIG_SYS_CSPR2_EXT (0xf) 347 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 348 | CSPR_PORT_SIZE_8 \ 349 | CSPR_MSEL_GPCM \ 350 | CSPR_V) 351 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 352 #define CONFIG_SYS_CSOR2 0x0 353 354 /* CPLD Timing parameters for IFC CS2 */ 355 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 356 FTIM0_GPCM_TEADC(0x0e) | \ 357 FTIM0_GPCM_TEAHC(0x0e)) 358 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 359 FTIM1_GPCM_TRAD(0x1f)) 360 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 361 FTIM2_GPCM_TCH(0x8) | \ 362 FTIM2_GPCM_TWP(0x1f)) 363 #define CONFIG_SYS_CS2_FTIM3 0x0 364 #endif 365 366 /* NAND Flash on IFC */ 367 #define CONFIG_NAND_FSL_IFC 368 #define CONFIG_SYS_NAND_BASE 0xff800000 369 #ifdef CONFIG_PHYS_64BIT 370 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 371 #else 372 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 373 #endif 374 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 375 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 376 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 377 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 378 | CSPR_V) 379 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 380 381 #if defined(CONFIG_T1024RDB) 382 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 383 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 384 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 385 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 386 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 387 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 388 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 389 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 390 #elif defined(CONFIG_T1023RDB) 391 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 392 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 393 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 394 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 395 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 396 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 397 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 398 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 399 #endif 400 401 #define CONFIG_SYS_NAND_ONFI_DETECTION 402 /* ONFI NAND Flash mode0 Timing Params */ 403 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 404 FTIM0_NAND_TWP(0x18) | \ 405 FTIM0_NAND_TWCHT(0x07) | \ 406 FTIM0_NAND_TWH(0x0a)) 407 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 408 FTIM1_NAND_TWBE(0x39) | \ 409 FTIM1_NAND_TRR(0x0e) | \ 410 FTIM1_NAND_TRP(0x18)) 411 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 412 FTIM2_NAND_TREH(0x0a) | \ 413 FTIM2_NAND_TWHRE(0x1e)) 414 #define CONFIG_SYS_NAND_FTIM3 0x0 415 416 #define CONFIG_SYS_NAND_DDR_LAW 11 417 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 418 #define CONFIG_SYS_MAX_NAND_DEVICE 1 419 #define CONFIG_CMD_NAND 420 421 #if defined(CONFIG_NAND) 422 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 423 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 424 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 425 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 426 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 427 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 428 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 429 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 430 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 431 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 432 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 433 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 434 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 435 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 436 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 437 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 438 #else 439 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 440 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 441 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 442 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 443 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 444 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 445 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 446 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 447 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 448 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 449 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 450 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 451 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 452 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 453 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 454 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 455 #endif 456 457 #ifdef CONFIG_SPL_BUILD 458 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 459 #else 460 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 461 #endif 462 463 #if defined(CONFIG_RAMBOOT_PBL) 464 #define CONFIG_SYS_RAMBOOT 465 #endif 466 467 #define CONFIG_BOARD_EARLY_INIT_R 468 #define CONFIG_MISC_INIT_R 469 470 #define CONFIG_HWCONFIG 471 472 /* define to use L1 as initial stack */ 473 #define CONFIG_L1_INIT_RAM 474 #define CONFIG_SYS_INIT_RAM_LOCK 475 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 476 #ifdef CONFIG_PHYS_64BIT 477 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 478 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 479 /* The assembler doesn't like typecast */ 480 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 481 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 482 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 483 #else 484 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 485 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 486 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 487 #endif 488 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 489 490 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 491 GENERATED_GBL_DATA_SIZE) 492 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 493 494 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 495 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 496 497 /* Serial Port */ 498 #define CONFIG_CONS_INDEX 1 499 #define CONFIG_SYS_NS16550_SERIAL 500 #define CONFIG_SYS_NS16550_REG_SIZE 1 501 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 502 503 #define CONFIG_SYS_BAUDRATE_TABLE \ 504 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 505 506 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 507 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 508 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 509 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 510 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 511 512 /* Video */ 513 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 514 #ifdef CONFIG_FSL_DIU_FB 515 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 516 #define CONFIG_VIDEO 517 #define CONFIG_CMD_BMP 518 #define CONFIG_CFB_CONSOLE 519 #define CONFIG_VIDEO_SW_CURSOR 520 #define CONFIG_VGA_AS_SINGLE_DEVICE 521 #define CONFIG_VIDEO_LOGO 522 #define CONFIG_VIDEO_BMP_LOGO 523 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 524 /* 525 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 526 * disable empty flash sector detection, which is I/O-intensive. 527 */ 528 #undef CONFIG_SYS_FLASH_EMPTY_INFO 529 #endif 530 531 /* I2C */ 532 #define CONFIG_SYS_I2C 533 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 534 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 535 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 536 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 537 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 538 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 539 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 540 541 #define I2C_PCA6408_BUS_NUM 1 542 #define I2C_PCA6408_ADDR 0x20 543 544 /* I2C bus multiplexer */ 545 #define I2C_MUX_CH_DEFAULT 0x8 546 547 /* 548 * RTC configuration 549 */ 550 #define RTC 551 #define CONFIG_RTC_DS1337 1 552 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 553 554 /* 555 * eSPI - Enhanced SPI 556 */ 557 #define CONFIG_SPI_FLASH_BAR 558 #define CONFIG_SF_DEFAULT_SPEED 10000000 559 #define CONFIG_SF_DEFAULT_MODE 0 560 561 /* 562 * General PCIe 563 * Memory space is mapped 1-1, but I/O space must start from 0. 564 */ 565 #define CONFIG_PCI /* Enable PCI/PCIE */ 566 #define CONFIG_PCIE1 /* PCIE controler 1 */ 567 #define CONFIG_PCIE2 /* PCIE controler 2 */ 568 #define CONFIG_PCIE3 /* PCIE controler 3 */ 569 #ifdef CONFIG_PPC_T1040 570 #define CONFIG_PCIE4 /* PCIE controler 4 */ 571 #endif 572 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 573 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 574 #define CONFIG_PCI_INDIRECT_BRIDGE 575 576 #ifdef CONFIG_PCI 577 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 578 #ifdef CONFIG_PCIE1 579 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 580 #ifdef CONFIG_PHYS_64BIT 581 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 582 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 583 #else 584 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 585 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 586 #endif 587 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 588 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 589 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 590 #ifdef CONFIG_PHYS_64BIT 591 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 592 #else 593 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 594 #endif 595 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 596 #endif 597 598 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 599 #ifdef CONFIG_PCIE2 600 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 601 #ifdef CONFIG_PHYS_64BIT 602 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 603 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 604 #else 605 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 606 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 607 #endif 608 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 609 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 610 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 611 #ifdef CONFIG_PHYS_64BIT 612 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 613 #else 614 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 615 #endif 616 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 617 #endif 618 619 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 620 #ifdef CONFIG_PCIE3 621 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 622 #ifdef CONFIG_PHYS_64BIT 623 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 624 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 625 #else 626 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 627 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 628 #endif 629 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 630 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 631 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 632 #ifdef CONFIG_PHYS_64BIT 633 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 634 #else 635 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 636 #endif 637 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 638 #endif 639 640 /* controller 4, Base address 203000, to be removed */ 641 #ifdef CONFIG_PCIE4 642 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 643 #ifdef CONFIG_PHYS_64BIT 644 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 645 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 646 #else 647 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 648 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 649 #endif 650 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 651 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 652 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 653 #ifdef CONFIG_PHYS_64BIT 654 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 655 #else 656 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 657 #endif 658 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 659 #endif 660 661 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 662 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 663 #define CONFIG_DOS_PARTITION 664 #endif /* CONFIG_PCI */ 665 666 /* 667 * USB 668 */ 669 #define CONFIG_HAS_FSL_DR_USB 670 671 #ifdef CONFIG_HAS_FSL_DR_USB 672 #define CONFIG_USB_EHCI 673 #define CONFIG_USB_STORAGE 674 #define CONFIG_USB_EHCI_FSL 675 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 676 #define CONFIG_CMD_EXT2 677 #endif 678 679 /* 680 * SDHC 681 */ 682 #define CONFIG_MMC 683 #ifdef CONFIG_MMC 684 #define CONFIG_FSL_ESDHC 685 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 686 #define CONFIG_CMD_MMC 687 #define CONFIG_GENERIC_MMC 688 #define CONFIG_CMD_EXT2 689 #define CONFIG_CMD_FAT 690 #define CONFIG_DOS_PARTITION 691 #endif 692 693 /* Qman/Bman */ 694 #ifndef CONFIG_NOBQFMAN 695 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 696 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 697 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 698 #ifdef CONFIG_PHYS_64BIT 699 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 700 #else 701 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 702 #endif 703 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 704 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 705 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 706 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 707 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 708 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 709 CONFIG_SYS_BMAN_CENA_SIZE) 710 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 711 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 712 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 713 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 714 #ifdef CONFIG_PHYS_64BIT 715 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 716 #else 717 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 718 #endif 719 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 720 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 721 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 722 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 723 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 724 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 725 CONFIG_SYS_QMAN_CENA_SIZE) 726 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 727 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 728 729 #define CONFIG_SYS_DPAA_FMAN 730 731 #ifdef CONFIG_T1024RDB 732 #define CONFIG_QE 733 #define CONFIG_U_QE 734 #endif 735 /* Default address of microcode for the Linux FMan driver */ 736 #if defined(CONFIG_SPIFLASH) 737 /* 738 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 739 * env, so we got 0x110000. 740 */ 741 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 742 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 743 #define CONFIG_SYS_QE_FW_ADDR 0x130000 744 #elif defined(CONFIG_SDCARD) 745 /* 746 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 747 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 748 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 749 */ 750 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 751 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 752 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 753 #elif defined(CONFIG_NAND) 754 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 755 #if defined(CONFIG_T1024RDB) 756 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 757 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 758 #elif defined(CONFIG_T1023RDB) 759 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 760 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 761 #endif 762 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 763 /* 764 * Slave has no ucode locally, it can fetch this from remote. When implementing 765 * in two corenet boards, slave's ucode could be stored in master's memory 766 * space, the address can be mapped from slave TLB->slave LAW-> 767 * slave SRIO or PCIE outbound window->master inbound window-> 768 * master LAW->the ucode address in master's memory space. 769 */ 770 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 771 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 772 #else 773 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 774 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 775 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 776 #endif 777 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 778 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 779 #endif /* CONFIG_NOBQFMAN */ 780 781 #ifdef CONFIG_SYS_DPAA_FMAN 782 #define CONFIG_FMAN_ENET 783 #define CONFIG_PHYLIB_10G 784 #define CONFIG_PHY_REALTEK 785 #define CONFIG_PHY_AQUANTIA 786 #if defined(CONFIG_T1024RDB) 787 #define RGMII_PHY1_ADDR 0x2 788 #define RGMII_PHY2_ADDR 0x6 789 #define SGMII_AQR_PHY_ADDR 0x2 790 #define FM1_10GEC1_PHY_ADDR 0x1 791 #elif defined(CONFIG_T1023RDB) 792 #define RGMII_PHY1_ADDR 0x1 793 #define SGMII_RTK_PHY_ADDR 0x3 794 #define SGMII_AQR_PHY_ADDR 0x2 795 #endif 796 #endif 797 798 #ifdef CONFIG_FMAN_ENET 799 #define CONFIG_MII /* MII PHY management */ 800 #define CONFIG_ETHPRIME "FM1@DTSEC4" 801 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 802 #endif 803 804 /* 805 * Dynamic MTD Partition support with mtdparts 806 */ 807 #ifndef CONFIG_SYS_NO_FLASH 808 #define CONFIG_MTD_DEVICE 809 #define CONFIG_MTD_PARTITIONS 810 #define CONFIG_CMD_MTDPARTS 811 #define CONFIG_FLASH_CFI_MTD 812 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 813 "spi0=spife110000.1" 814 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 815 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 816 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 817 "1m(uboot),5m(kernel),128k(dtb),-(user)" 818 #endif 819 820 /* 821 * Environment 822 */ 823 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 824 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 825 826 /* 827 * Command line configuration. 828 */ 829 #define CONFIG_CMD_DATE 830 #define CONFIG_CMD_EEPROM 831 #define CONFIG_CMD_ERRATA 832 #define CONFIG_CMD_GREPENV 833 #define CONFIG_CMD_IRQ 834 #define CONFIG_CMD_MII 835 #define CONFIG_CMD_REGINFO 836 837 #ifdef CONFIG_PCI 838 #define CONFIG_CMD_PCI 839 #endif 840 841 /* 842 * Miscellaneous configurable options 843 */ 844 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 845 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 846 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 847 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 848 #ifdef CONFIG_CMD_KGDB 849 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 850 #else 851 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 852 #endif 853 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 854 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 855 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 856 857 /* 858 * For booting Linux, the board info and command line data 859 * have to be in the first 64 MB of memory, since this is 860 * the maximum mapped by the Linux kernel during initialization. 861 */ 862 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 863 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 864 865 #ifdef CONFIG_CMD_KGDB 866 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 867 #endif 868 869 /* 870 * Environment Configuration 871 */ 872 #define CONFIG_ROOTPATH "/opt/nfsroot" 873 #define CONFIG_BOOTFILE "uImage" 874 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 875 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 876 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 877 #define CONFIG_BAUDRATE 115200 878 #define __USB_PHY_TYPE utmi 879 880 #ifdef CONFIG_PPC_T1024 881 #define CONFIG_BOARDNAME t1024rdb 882 #define BANK_INTLV cs0_cs1 883 #else 884 #define CONFIG_BOARDNAME t1023rdb 885 #define BANK_INTLV null 886 #endif 887 888 #define CONFIG_EXTRA_ENV_SETTINGS \ 889 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 890 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 891 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 892 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 893 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 894 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 895 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 896 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 897 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 898 "netdev=eth0\0" \ 899 "tftpflash=tftpboot $loadaddr $uboot && " \ 900 "protect off $ubootaddr +$filesize && " \ 901 "erase $ubootaddr +$filesize && " \ 902 "cp.b $loadaddr $ubootaddr $filesize && " \ 903 "protect on $ubootaddr +$filesize && " \ 904 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 905 "consoledev=ttyS0\0" \ 906 "ramdiskaddr=2000000\0" \ 907 "fdtaddr=c00000\0" \ 908 "bdev=sda3\0" 909 910 #define CONFIG_LINUX \ 911 "setenv bootargs root=/dev/ram rw " \ 912 "console=$consoledev,$baudrate $othbootargs;" \ 913 "setenv ramdiskaddr 0x02000000;" \ 914 "setenv fdtaddr 0x00c00000;" \ 915 "setenv loadaddr 0x1000000;" \ 916 "bootm $loadaddr $ramdiskaddr $fdtaddr" 917 918 #define CONFIG_NFSBOOTCOMMAND \ 919 "setenv bootargs root=/dev/nfs rw " \ 920 "nfsroot=$serverip:$rootpath " \ 921 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 922 "console=$consoledev,$baudrate $othbootargs;" \ 923 "tftp $loadaddr $bootfile;" \ 924 "tftp $fdtaddr $fdtfile;" \ 925 "bootm $loadaddr - $fdtaddr" 926 927 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 928 929 /* Hash command with SHA acceleration supported in hardware */ 930 #ifdef CONFIG_FSL_CAAM 931 #define CONFIG_CMD_HASH 932 #define CONFIG_SHA_HW_ACCEL 933 #endif 934 935 #include <asm/fsl_secure_boot.h> 936 937 #endif /* __T1024RDB_H */ 938