1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #ifdef CONFIG_PHYS_64BIT 24 #define CONFIG_ADDR_MAP 1 25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 26 #endif 27 28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 29 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 30 #define CONFIG_FSL_IFC /* Enable IFC Support */ 31 32 #define CONFIG_FSL_LAW /* Use common FSL init code */ 33 #define CONFIG_ENV_OVERWRITE 34 35 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 36 37 /* support deep sleep */ 38 #ifdef CONFIG_PPC_T1024 39 #define CONFIG_DEEP_SLEEP 40 #endif 41 #if defined(CONFIG_DEEP_SLEEP) 42 #define CONFIG_SILENT_CONSOLE 43 #define CONFIG_BOARD_EARLY_INIT_F 44 #endif 45 46 #ifdef CONFIG_RAMBOOT_PBL 47 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 48 #if defined(CONFIG_T1024RDB) 49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg 50 #elif defined(CONFIG_T1023RDB) 51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg 52 #endif 53 #define CONFIG_SPL_SERIAL_SUPPORT 54 #define CONFIG_SPL_FLUSH_IMAGE 55 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 56 #define CONFIG_FSL_LAW /* Use common FSL init code */ 57 #define CONFIG_SYS_TEXT_BASE 0x30001000 58 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 59 #define CONFIG_SPL_PAD_TO 0x40000 60 #define CONFIG_SPL_MAX_SIZE 0x28000 61 #define RESET_VECTOR_OFFSET 0x27FFC 62 #define BOOT_PAGE_OFFSET 0x27000 63 #ifdef CONFIG_SPL_BUILD 64 #define CONFIG_SPL_SKIP_RELOCATE 65 #define CONFIG_SPL_COMMON_INIT_DDR 66 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 67 #define CONFIG_SYS_NO_FLASH 68 #endif 69 70 #ifdef CONFIG_NAND 71 #define CONFIG_SPL_NAND_SUPPORT 72 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 73 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 74 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 75 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 76 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 77 #define CONFIG_SPL_NAND_BOOT 78 #endif 79 80 #ifdef CONFIG_SPIFLASH 81 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 82 #define CONFIG_SPL_SPI_SUPPORT 83 #define CONFIG_SPL_SPI_FLASH_SUPPORT 84 #define CONFIG_SPL_SPI_FLASH_MINIMAL 85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 89 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 90 #ifndef CONFIG_SPL_BUILD 91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 92 #endif 93 #define CONFIG_SPL_SPI_BOOT 94 #endif 95 96 #ifdef CONFIG_SDCARD 97 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 98 #define CONFIG_SPL_MMC_MINIMAL 99 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 100 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 101 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 102 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 103 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 104 #ifndef CONFIG_SPL_BUILD 105 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 106 #endif 107 #define CONFIG_SPL_MMC_BOOT 108 #endif 109 110 #endif /* CONFIG_RAMBOOT_PBL */ 111 112 #ifndef CONFIG_SYS_TEXT_BASE 113 #define CONFIG_SYS_TEXT_BASE 0xeff40000 114 #endif 115 116 #ifndef CONFIG_RESET_VECTOR_ADDRESS 117 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 118 #endif 119 120 #ifndef CONFIG_SYS_NO_FLASH 121 #define CONFIG_FLASH_CFI_DRIVER 122 #define CONFIG_SYS_FLASH_CFI 123 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 124 #endif 125 126 /* PCIe Boot - Master */ 127 #define CONFIG_SRIO_PCIE_BOOT_MASTER 128 /* 129 * for slave u-boot IMAGE instored in master memory space, 130 * PHYS must be aligned based on the SIZE 131 */ 132 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 133 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 134 #ifdef CONFIG_PHYS_64BIT 135 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 136 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 137 #else 138 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 139 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 140 #endif 141 /* 142 * for slave UCODE and ENV instored in master memory space, 143 * PHYS must be aligned based on the SIZE 144 */ 145 #ifdef CONFIG_PHYS_64BIT 146 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 147 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 148 #else 149 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 150 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 151 #endif 152 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 153 /* slave core release by master*/ 154 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 155 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 156 157 /* PCIe Boot - Slave */ 158 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 159 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 160 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 161 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 162 /* Set 1M boot space for PCIe boot */ 163 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 164 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 165 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 166 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 167 #define CONFIG_SYS_NO_FLASH 168 #endif 169 170 #if defined(CONFIG_SPIFLASH) 171 #define CONFIG_SYS_EXTRA_ENV_RELOC 172 #define CONFIG_ENV_IS_IN_SPI_FLASH 173 #define CONFIG_ENV_SPI_BUS 0 174 #define CONFIG_ENV_SPI_CS 0 175 #define CONFIG_ENV_SPI_MAX_HZ 10000000 176 #define CONFIG_ENV_SPI_MODE 0 177 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 178 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 179 #if defined(CONFIG_T1024RDB) 180 #define CONFIG_ENV_SECT_SIZE 0x10000 181 #elif defined(CONFIG_T1023RDB) 182 #define CONFIG_ENV_SECT_SIZE 0x40000 183 #endif 184 #elif defined(CONFIG_SDCARD) 185 #define CONFIG_SYS_EXTRA_ENV_RELOC 186 #define CONFIG_ENV_IS_IN_MMC 187 #define CONFIG_SYS_MMC_ENV_DEV 0 188 #define CONFIG_ENV_SIZE 0x2000 189 #define CONFIG_ENV_OFFSET (512 * 0x800) 190 #elif defined(CONFIG_NAND) 191 #define CONFIG_SYS_EXTRA_ENV_RELOC 192 #define CONFIG_ENV_IS_IN_NAND 193 #define CONFIG_ENV_SIZE 0x2000 194 #if defined(CONFIG_T1024RDB) 195 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 196 #elif defined(CONFIG_T1023RDB) 197 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 198 #endif 199 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 200 #define CONFIG_ENV_IS_IN_REMOTE 201 #define CONFIG_ENV_ADDR 0xffe20000 202 #define CONFIG_ENV_SIZE 0x2000 203 #elif defined(CONFIG_ENV_IS_NOWHERE) 204 #define CONFIG_ENV_SIZE 0x2000 205 #else 206 #define CONFIG_ENV_IS_IN_FLASH 207 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 208 #define CONFIG_ENV_SIZE 0x2000 209 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 210 #endif 211 212 #ifndef __ASSEMBLY__ 213 unsigned long get_board_sys_clk(void); 214 unsigned long get_board_ddr_clk(void); 215 #endif 216 217 #define CONFIG_SYS_CLK_FREQ 100000000 218 #define CONFIG_DDR_CLK_FREQ 100000000 219 220 /* 221 * These can be toggled for performance analysis, otherwise use default. 222 */ 223 #define CONFIG_SYS_CACHE_STASHING 224 #define CONFIG_BACKSIDE_L2_CACHE 225 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 226 #define CONFIG_BTB /* toggle branch predition */ 227 #define CONFIG_DDR_ECC 228 #ifdef CONFIG_DDR_ECC 229 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 230 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 231 #endif 232 233 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 234 #define CONFIG_SYS_MEMTEST_END 0x00400000 235 #define CONFIG_SYS_ALT_MEMTEST 236 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 237 238 /* 239 * Config the L3 Cache as L3 SRAM 240 */ 241 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 242 #define CONFIG_SYS_L3_SIZE (256 << 10) 243 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 244 #ifdef CONFIG_RAMBOOT_PBL 245 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 246 #endif 247 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 248 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 249 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 250 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 251 252 #ifdef CONFIG_PHYS_64BIT 253 #define CONFIG_SYS_DCSRBAR 0xf0000000 254 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 255 #endif 256 257 /* EEPROM */ 258 #define CONFIG_ID_EEPROM 259 #define CONFIG_SYS_I2C_EEPROM_NXID 260 #define CONFIG_SYS_EEPROM_BUS_NUM 0 261 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 262 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 263 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 264 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 265 266 /* 267 * DDR Setup 268 */ 269 #define CONFIG_VERY_BIG_RAM 270 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 271 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 272 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 273 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 274 #define CONFIG_FSL_DDR_INTERACTIVE 275 #if defined(CONFIG_T1024RDB) 276 #define CONFIG_DDR_SPD 277 #define CONFIG_SYS_FSL_DDR3 278 #define CONFIG_SYS_SPD_BUS_NUM 0 279 #define SPD_EEPROM_ADDRESS 0x51 280 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 281 #elif defined(CONFIG_T1023RDB) 282 #define CONFIG_SYS_FSL_DDR4 283 #define CONFIG_SYS_DDR_RAW_TIMING 284 #define CONFIG_SYS_SDRAM_SIZE 2048 285 #endif 286 287 /* 288 * IFC Definitions 289 */ 290 #define CONFIG_SYS_FLASH_BASE 0xe8000000 291 #ifdef CONFIG_PHYS_64BIT 292 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 293 #else 294 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 295 #endif 296 297 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 298 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 299 CSPR_PORT_SIZE_16 | \ 300 CSPR_MSEL_NOR | \ 301 CSPR_V) 302 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 303 304 /* NOR Flash Timing Params */ 305 #if defined(CONFIG_T1024RDB) 306 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 307 #elif defined(CONFIG_T1023RDB) 308 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 309 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 310 #endif 311 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 312 FTIM0_NOR_TEADC(0x5) | \ 313 FTIM0_NOR_TEAHC(0x5)) 314 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 315 FTIM1_NOR_TRAD_NOR(0x1A) |\ 316 FTIM1_NOR_TSEQRAD_NOR(0x13)) 317 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 318 FTIM2_NOR_TCH(0x4) | \ 319 FTIM2_NOR_TWPH(0x0E) | \ 320 FTIM2_NOR_TWP(0x1c)) 321 #define CONFIG_SYS_NOR_FTIM3 0x0 322 323 #define CONFIG_SYS_FLASH_QUIET_TEST 324 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 325 326 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 327 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 328 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 329 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 330 331 #define CONFIG_SYS_FLASH_EMPTY_INFO 332 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 333 334 #ifdef CONFIG_T1024RDB 335 /* CPLD on IFC */ 336 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 337 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 338 #define CONFIG_SYS_CSPR2_EXT (0xf) 339 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 340 | CSPR_PORT_SIZE_8 \ 341 | CSPR_MSEL_GPCM \ 342 | CSPR_V) 343 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 344 #define CONFIG_SYS_CSOR2 0x0 345 346 /* CPLD Timing parameters for IFC CS2 */ 347 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 348 FTIM0_GPCM_TEADC(0x0e) | \ 349 FTIM0_GPCM_TEAHC(0x0e)) 350 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 351 FTIM1_GPCM_TRAD(0x1f)) 352 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 353 FTIM2_GPCM_TCH(0x8) | \ 354 FTIM2_GPCM_TWP(0x1f)) 355 #define CONFIG_SYS_CS2_FTIM3 0x0 356 #endif 357 358 /* NAND Flash on IFC */ 359 #define CONFIG_NAND_FSL_IFC 360 #define CONFIG_SYS_NAND_BASE 0xff800000 361 #ifdef CONFIG_PHYS_64BIT 362 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 363 #else 364 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 365 #endif 366 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 367 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 368 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 369 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 370 | CSPR_V) 371 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 372 373 #if defined(CONFIG_T1024RDB) 374 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 375 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 376 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 377 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 378 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 379 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 380 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 381 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 382 #elif defined(CONFIG_T1023RDB) 383 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 384 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 385 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 386 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 387 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 388 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 389 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 390 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 391 #endif 392 393 #define CONFIG_SYS_NAND_ONFI_DETECTION 394 /* ONFI NAND Flash mode0 Timing Params */ 395 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 396 FTIM0_NAND_TWP(0x18) | \ 397 FTIM0_NAND_TWCHT(0x07) | \ 398 FTIM0_NAND_TWH(0x0a)) 399 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 400 FTIM1_NAND_TWBE(0x39) | \ 401 FTIM1_NAND_TRR(0x0e) | \ 402 FTIM1_NAND_TRP(0x18)) 403 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 404 FTIM2_NAND_TREH(0x0a) | \ 405 FTIM2_NAND_TWHRE(0x1e)) 406 #define CONFIG_SYS_NAND_FTIM3 0x0 407 408 #define CONFIG_SYS_NAND_DDR_LAW 11 409 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 410 #define CONFIG_SYS_MAX_NAND_DEVICE 1 411 #define CONFIG_CMD_NAND 412 413 #if defined(CONFIG_NAND) 414 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 415 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 416 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 417 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 418 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 419 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 420 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 421 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 422 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 423 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 424 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 425 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 426 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 427 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 428 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 429 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 430 #else 431 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 432 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 433 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 434 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 435 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 436 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 437 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 438 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 439 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 440 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 441 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 442 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 443 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 444 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 445 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 446 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 447 #endif 448 449 #ifdef CONFIG_SPL_BUILD 450 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 451 #else 452 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 453 #endif 454 455 #if defined(CONFIG_RAMBOOT_PBL) 456 #define CONFIG_SYS_RAMBOOT 457 #endif 458 459 #define CONFIG_BOARD_EARLY_INIT_R 460 #define CONFIG_MISC_INIT_R 461 462 #define CONFIG_HWCONFIG 463 464 /* define to use L1 as initial stack */ 465 #define CONFIG_L1_INIT_RAM 466 #define CONFIG_SYS_INIT_RAM_LOCK 467 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 468 #ifdef CONFIG_PHYS_64BIT 469 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 471 /* The assembler doesn't like typecast */ 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 473 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 474 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 475 #else 476 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 477 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 478 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 479 #endif 480 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 481 482 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 483 GENERATED_GBL_DATA_SIZE) 484 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 485 486 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 487 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 488 489 /* Serial Port */ 490 #define CONFIG_CONS_INDEX 1 491 #define CONFIG_SYS_NS16550_SERIAL 492 #define CONFIG_SYS_NS16550_REG_SIZE 1 493 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 494 495 #define CONFIG_SYS_BAUDRATE_TABLE \ 496 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 497 498 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 499 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 500 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 501 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 502 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 503 504 /* Video */ 505 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 506 #ifdef CONFIG_FSL_DIU_FB 507 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 508 #define CONFIG_VIDEO 509 #define CONFIG_CMD_BMP 510 #define CONFIG_CFB_CONSOLE 511 #define CONFIG_VIDEO_SW_CURSOR 512 #define CONFIG_VGA_AS_SINGLE_DEVICE 513 #define CONFIG_VIDEO_LOGO 514 #define CONFIG_VIDEO_BMP_LOGO 515 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 516 /* 517 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 518 * disable empty flash sector detection, which is I/O-intensive. 519 */ 520 #undef CONFIG_SYS_FLASH_EMPTY_INFO 521 #endif 522 523 /* I2C */ 524 #define CONFIG_SYS_I2C 525 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 526 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 527 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 528 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 529 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 530 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 531 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 532 533 #define I2C_PCA6408_BUS_NUM 1 534 #define I2C_PCA6408_ADDR 0x20 535 536 /* I2C bus multiplexer */ 537 #define I2C_MUX_CH_DEFAULT 0x8 538 539 /* 540 * RTC configuration 541 */ 542 #define RTC 543 #define CONFIG_RTC_DS1337 1 544 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 545 546 /* 547 * eSPI - Enhanced SPI 548 */ 549 #define CONFIG_SPI_FLASH_BAR 550 #define CONFIG_SF_DEFAULT_SPEED 10000000 551 #define CONFIG_SF_DEFAULT_MODE 0 552 553 /* 554 * General PCIe 555 * Memory space is mapped 1-1, but I/O space must start from 0. 556 */ 557 #define CONFIG_PCI /* Enable PCI/PCIE */ 558 #define CONFIG_PCIE1 /* PCIE controller 1 */ 559 #define CONFIG_PCIE2 /* PCIE controller 2 */ 560 #define CONFIG_PCIE3 /* PCIE controller 3 */ 561 #ifdef CONFIG_PPC_T1040 562 #define CONFIG_PCIE4 /* PCIE controller 4 */ 563 #endif 564 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 565 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 566 #define CONFIG_PCI_INDIRECT_BRIDGE 567 568 #ifdef CONFIG_PCI 569 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 570 #ifdef CONFIG_PCIE1 571 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 572 #ifdef CONFIG_PHYS_64BIT 573 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 574 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 575 #else 576 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 577 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 578 #endif 579 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 580 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 581 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 582 #ifdef CONFIG_PHYS_64BIT 583 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 584 #else 585 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 586 #endif 587 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 588 #endif 589 590 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 591 #ifdef CONFIG_PCIE2 592 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 593 #ifdef CONFIG_PHYS_64BIT 594 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 595 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 596 #else 597 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 598 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 599 #endif 600 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 601 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 602 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 603 #ifdef CONFIG_PHYS_64BIT 604 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 605 #else 606 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 607 #endif 608 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 609 #endif 610 611 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 612 #ifdef CONFIG_PCIE3 613 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 614 #ifdef CONFIG_PHYS_64BIT 615 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 616 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 617 #else 618 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 619 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 620 #endif 621 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 622 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 623 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 624 #ifdef CONFIG_PHYS_64BIT 625 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 626 #else 627 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 628 #endif 629 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 630 #endif 631 632 /* controller 4, Base address 203000, to be removed */ 633 #ifdef CONFIG_PCIE4 634 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 635 #ifdef CONFIG_PHYS_64BIT 636 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 637 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 638 #else 639 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 640 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 641 #endif 642 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 643 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 644 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 645 #ifdef CONFIG_PHYS_64BIT 646 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 647 #else 648 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 649 #endif 650 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 651 #endif 652 653 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 654 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 655 #define CONFIG_DOS_PARTITION 656 #endif /* CONFIG_PCI */ 657 658 /* 659 * USB 660 */ 661 #define CONFIG_HAS_FSL_DR_USB 662 663 #ifdef CONFIG_HAS_FSL_DR_USB 664 #define CONFIG_USB_EHCI 665 #define CONFIG_USB_EHCI_FSL 666 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 667 #endif 668 669 /* 670 * SDHC 671 */ 672 #define CONFIG_MMC 673 #ifdef CONFIG_MMC 674 #define CONFIG_FSL_ESDHC 675 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 676 #define CONFIG_GENERIC_MMC 677 #define CONFIG_DOS_PARTITION 678 #endif 679 680 /* Qman/Bman */ 681 #ifndef CONFIG_NOBQFMAN 682 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 683 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 684 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 685 #ifdef CONFIG_PHYS_64BIT 686 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 687 #else 688 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 689 #endif 690 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 691 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 692 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 693 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 694 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 695 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 696 CONFIG_SYS_BMAN_CENA_SIZE) 697 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 698 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 699 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 700 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 701 #ifdef CONFIG_PHYS_64BIT 702 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 703 #else 704 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 705 #endif 706 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 707 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 708 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 709 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 710 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 711 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 712 CONFIG_SYS_QMAN_CENA_SIZE) 713 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 714 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 715 716 #define CONFIG_SYS_DPAA_FMAN 717 718 #ifdef CONFIG_T1024RDB 719 #define CONFIG_QE 720 #define CONFIG_U_QE 721 #endif 722 /* Default address of microcode for the Linux FMan driver */ 723 #if defined(CONFIG_SPIFLASH) 724 /* 725 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 726 * env, so we got 0x110000. 727 */ 728 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 729 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 730 #define CONFIG_SYS_QE_FW_ADDR 0x130000 731 #elif defined(CONFIG_SDCARD) 732 /* 733 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 734 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 735 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 736 */ 737 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 738 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 739 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 740 #elif defined(CONFIG_NAND) 741 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 742 #if defined(CONFIG_T1024RDB) 743 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 744 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 745 #elif defined(CONFIG_T1023RDB) 746 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 747 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 748 #endif 749 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 750 /* 751 * Slave has no ucode locally, it can fetch this from remote. When implementing 752 * in two corenet boards, slave's ucode could be stored in master's memory 753 * space, the address can be mapped from slave TLB->slave LAW-> 754 * slave SRIO or PCIE outbound window->master inbound window-> 755 * master LAW->the ucode address in master's memory space. 756 */ 757 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 758 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 759 #else 760 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 761 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 762 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 763 #endif 764 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 765 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 766 #endif /* CONFIG_NOBQFMAN */ 767 768 #ifdef CONFIG_SYS_DPAA_FMAN 769 #define CONFIG_FMAN_ENET 770 #define CONFIG_PHYLIB_10G 771 #define CONFIG_PHY_REALTEK 772 #define CONFIG_PHY_AQUANTIA 773 #if defined(CONFIG_T1024RDB) 774 #define RGMII_PHY1_ADDR 0x2 775 #define RGMII_PHY2_ADDR 0x6 776 #define SGMII_AQR_PHY_ADDR 0x2 777 #define FM1_10GEC1_PHY_ADDR 0x1 778 #elif defined(CONFIG_T1023RDB) 779 #define RGMII_PHY1_ADDR 0x1 780 #define SGMII_RTK_PHY_ADDR 0x3 781 #define SGMII_AQR_PHY_ADDR 0x2 782 #endif 783 #endif 784 785 #ifdef CONFIG_FMAN_ENET 786 #define CONFIG_MII /* MII PHY management */ 787 #define CONFIG_ETHPRIME "FM1@DTSEC4" 788 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 789 #endif 790 791 /* 792 * Dynamic MTD Partition support with mtdparts 793 */ 794 #ifndef CONFIG_SYS_NO_FLASH 795 #define CONFIG_MTD_DEVICE 796 #define CONFIG_MTD_PARTITIONS 797 #define CONFIG_CMD_MTDPARTS 798 #define CONFIG_FLASH_CFI_MTD 799 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 800 "spi0=spife110000.1" 801 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 802 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 803 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 804 "1m(uboot),5m(kernel),128k(dtb),-(user)" 805 #endif 806 807 /* 808 * Environment 809 */ 810 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 811 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 812 813 /* 814 * Command line configuration. 815 */ 816 #define CONFIG_CMD_DATE 817 #define CONFIG_CMD_EEPROM 818 #define CONFIG_CMD_ERRATA 819 #define CONFIG_CMD_IRQ 820 #define CONFIG_CMD_REGINFO 821 822 #ifdef CONFIG_PCI 823 #define CONFIG_CMD_PCI 824 #endif 825 826 /* 827 * Miscellaneous configurable options 828 */ 829 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 830 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 831 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 832 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 833 #ifdef CONFIG_CMD_KGDB 834 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 835 #else 836 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 837 #endif 838 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 839 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 840 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 841 842 /* 843 * For booting Linux, the board info and command line data 844 * have to be in the first 64 MB of memory, since this is 845 * the maximum mapped by the Linux kernel during initialization. 846 */ 847 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 848 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 849 850 #ifdef CONFIG_CMD_KGDB 851 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 852 #endif 853 854 /* 855 * Environment Configuration 856 */ 857 #define CONFIG_ROOTPATH "/opt/nfsroot" 858 #define CONFIG_BOOTFILE "uImage" 859 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 860 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 861 #define CONFIG_BAUDRATE 115200 862 #define __USB_PHY_TYPE utmi 863 864 #ifdef CONFIG_PPC_T1024 865 #define CONFIG_BOARDNAME t1024rdb 866 #define BANK_INTLV cs0_cs1 867 #else 868 #define CONFIG_BOARDNAME t1023rdb 869 #define BANK_INTLV null 870 #endif 871 872 #define CONFIG_EXTRA_ENV_SETTINGS \ 873 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 874 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 875 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 876 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 877 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 878 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 879 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 880 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 881 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 882 "netdev=eth0\0" \ 883 "tftpflash=tftpboot $loadaddr $uboot && " \ 884 "protect off $ubootaddr +$filesize && " \ 885 "erase $ubootaddr +$filesize && " \ 886 "cp.b $loadaddr $ubootaddr $filesize && " \ 887 "protect on $ubootaddr +$filesize && " \ 888 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 889 "consoledev=ttyS0\0" \ 890 "ramdiskaddr=2000000\0" \ 891 "fdtaddr=1e00000\0" \ 892 "bdev=sda3\0" 893 894 #define CONFIG_LINUX \ 895 "setenv bootargs root=/dev/ram rw " \ 896 "console=$consoledev,$baudrate $othbootargs;" \ 897 "setenv ramdiskaddr 0x02000000;" \ 898 "setenv fdtaddr 0x00c00000;" \ 899 "setenv loadaddr 0x1000000;" \ 900 "bootm $loadaddr $ramdiskaddr $fdtaddr" 901 902 #define CONFIG_NFSBOOTCOMMAND \ 903 "setenv bootargs root=/dev/nfs rw " \ 904 "nfsroot=$serverip:$rootpath " \ 905 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 906 "console=$consoledev,$baudrate $othbootargs;" \ 907 "tftp $loadaddr $bootfile;" \ 908 "tftp $fdtaddr $fdtfile;" \ 909 "bootm $loadaddr - $fdtaddr" 910 911 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 912 913 /* Hash command with SHA acceleration supported in hardware */ 914 #ifdef CONFIG_FSL_CAAM 915 #define CONFIG_CMD_HASH 916 #define CONFIG_SHA_HW_ACCEL 917 #endif 918 919 #include <asm/fsl_secure_boot.h> 920 921 #endif /* __T1024RDB_H */ 922