1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_PHYS_64BIT 22 #define CONFIG_ENABLE_36BIT_PHYS 23 24 #ifdef CONFIG_PHYS_64BIT 25 #define CONFIG_ADDR_MAP 1 26 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 27 #endif 28 29 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 30 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 31 #define CONFIG_FSL_IFC /* Enable IFC Support */ 32 33 #define CONFIG_FSL_LAW /* Use common FSL init code */ 34 #define CONFIG_ENV_OVERWRITE 35 36 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 37 38 /* support deep sleep */ 39 #ifdef CONFIG_PPC_T1024 40 #define CONFIG_DEEP_SLEEP 41 #endif 42 #if defined(CONFIG_DEEP_SLEEP) 43 #define CONFIG_SILENT_CONSOLE 44 #define CONFIG_BOARD_EARLY_INIT_F 45 #endif 46 47 #ifdef CONFIG_RAMBOOT_PBL 48 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 49 #if defined(CONFIG_T1024RDB) 50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg 51 #elif defined(CONFIG_T1023RDB) 52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg 53 #endif 54 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 55 #define CONFIG_SPL_ENV_SUPPORT 56 #define CONFIG_SPL_SERIAL_SUPPORT 57 #define CONFIG_SPL_FLUSH_IMAGE 58 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 59 #define CONFIG_SPL_LIBGENERIC_SUPPORT 60 #define CONFIG_SPL_LIBCOMMON_SUPPORT 61 #define CONFIG_SPL_I2C_SUPPORT 62 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 63 #define CONFIG_FSL_LAW /* Use common FSL init code */ 64 #define CONFIG_SYS_TEXT_BASE 0x30001000 65 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 66 #define CONFIG_SPL_PAD_TO 0x40000 67 #define CONFIG_SPL_MAX_SIZE 0x28000 68 #define RESET_VECTOR_OFFSET 0x27FFC 69 #define BOOT_PAGE_OFFSET 0x27000 70 #ifdef CONFIG_SPL_BUILD 71 #define CONFIG_SPL_SKIP_RELOCATE 72 #define CONFIG_SPL_COMMON_INIT_DDR 73 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 74 #define CONFIG_SYS_NO_FLASH 75 #endif 76 77 #ifdef CONFIG_NAND 78 #define CONFIG_SPL_NAND_SUPPORT 79 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 80 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 81 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 82 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 83 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 84 #define CONFIG_SPL_NAND_BOOT 85 #endif 86 87 #ifdef CONFIG_SPIFLASH 88 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 89 #define CONFIG_SPL_SPI_SUPPORT 90 #define CONFIG_SPL_SPI_FLASH_SUPPORT 91 #define CONFIG_SPL_SPI_FLASH_MINIMAL 92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 94 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 95 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 96 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 97 #ifndef CONFIG_SPL_BUILD 98 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 99 #endif 100 #define CONFIG_SPL_SPI_BOOT 101 #endif 102 103 #ifdef CONFIG_SDCARD 104 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 105 #define CONFIG_SPL_MMC_SUPPORT 106 #define CONFIG_SPL_MMC_MINIMAL 107 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 108 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 109 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 110 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 111 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 112 #ifndef CONFIG_SPL_BUILD 113 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 114 #endif 115 #define CONFIG_SPL_MMC_BOOT 116 #endif 117 118 #endif /* CONFIG_RAMBOOT_PBL */ 119 120 #ifndef CONFIG_SYS_TEXT_BASE 121 #define CONFIG_SYS_TEXT_BASE 0xeff40000 122 #endif 123 124 #ifndef CONFIG_RESET_VECTOR_ADDRESS 125 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 126 #endif 127 128 #ifndef CONFIG_SYS_NO_FLASH 129 #define CONFIG_FLASH_CFI_DRIVER 130 #define CONFIG_SYS_FLASH_CFI 131 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 132 #endif 133 134 /* PCIe Boot - Master */ 135 #define CONFIG_SRIO_PCIE_BOOT_MASTER 136 /* 137 * for slave u-boot IMAGE instored in master memory space, 138 * PHYS must be aligned based on the SIZE 139 */ 140 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 141 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 142 #ifdef CONFIG_PHYS_64BIT 143 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 144 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 145 #else 146 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 147 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 148 #endif 149 /* 150 * for slave UCODE and ENV instored in master memory space, 151 * PHYS must be aligned based on the SIZE 152 */ 153 #ifdef CONFIG_PHYS_64BIT 154 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 155 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 156 #else 157 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 158 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 159 #endif 160 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 161 /* slave core release by master*/ 162 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 163 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 164 165 /* PCIe Boot - Slave */ 166 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 167 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 168 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 169 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 170 /* Set 1M boot space for PCIe boot */ 171 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 172 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 173 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 174 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 175 #define CONFIG_SYS_NO_FLASH 176 #endif 177 178 #if defined(CONFIG_SPIFLASH) 179 #define CONFIG_SYS_EXTRA_ENV_RELOC 180 #define CONFIG_ENV_IS_IN_SPI_FLASH 181 #define CONFIG_ENV_SPI_BUS 0 182 #define CONFIG_ENV_SPI_CS 0 183 #define CONFIG_ENV_SPI_MAX_HZ 10000000 184 #define CONFIG_ENV_SPI_MODE 0 185 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 186 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 187 #if defined(CONFIG_T1024RDB) 188 #define CONFIG_ENV_SECT_SIZE 0x10000 189 #elif defined(CONFIG_T1023RDB) 190 #define CONFIG_ENV_SECT_SIZE 0x40000 191 #endif 192 #elif defined(CONFIG_SDCARD) 193 #define CONFIG_SYS_EXTRA_ENV_RELOC 194 #define CONFIG_ENV_IS_IN_MMC 195 #define CONFIG_SYS_MMC_ENV_DEV 0 196 #define CONFIG_ENV_SIZE 0x2000 197 #define CONFIG_ENV_OFFSET (512 * 0x800) 198 #elif defined(CONFIG_NAND) 199 #define CONFIG_SYS_EXTRA_ENV_RELOC 200 #define CONFIG_ENV_IS_IN_NAND 201 #define CONFIG_ENV_SIZE 0x2000 202 #if defined(CONFIG_T1024RDB) 203 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 204 #elif defined(CONFIG_T1023RDB) 205 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 206 #endif 207 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 208 #define CONFIG_ENV_IS_IN_REMOTE 209 #define CONFIG_ENV_ADDR 0xffe20000 210 #define CONFIG_ENV_SIZE 0x2000 211 #elif defined(CONFIG_ENV_IS_NOWHERE) 212 #define CONFIG_ENV_SIZE 0x2000 213 #else 214 #define CONFIG_ENV_IS_IN_FLASH 215 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 216 #define CONFIG_ENV_SIZE 0x2000 217 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 218 #endif 219 220 221 #ifndef __ASSEMBLY__ 222 unsigned long get_board_sys_clk(void); 223 unsigned long get_board_ddr_clk(void); 224 #endif 225 226 #define CONFIG_SYS_CLK_FREQ 100000000 227 #define CONFIG_DDR_CLK_FREQ 100000000 228 229 /* 230 * These can be toggled for performance analysis, otherwise use default. 231 */ 232 #define CONFIG_SYS_CACHE_STASHING 233 #define CONFIG_BACKSIDE_L2_CACHE 234 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 235 #define CONFIG_BTB /* toggle branch predition */ 236 #define CONFIG_DDR_ECC 237 #ifdef CONFIG_DDR_ECC 238 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 239 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 240 #endif 241 242 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 243 #define CONFIG_SYS_MEMTEST_END 0x00400000 244 #define CONFIG_SYS_ALT_MEMTEST 245 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 246 247 /* 248 * Config the L3 Cache as L3 SRAM 249 */ 250 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 251 #define CONFIG_SYS_L3_SIZE (256 << 10) 252 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 253 #ifdef CONFIG_RAMBOOT_PBL 254 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 255 #endif 256 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 257 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 258 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 259 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 260 261 #ifdef CONFIG_PHYS_64BIT 262 #define CONFIG_SYS_DCSRBAR 0xf0000000 263 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 264 #endif 265 266 /* EEPROM */ 267 #define CONFIG_ID_EEPROM 268 #define CONFIG_SYS_I2C_EEPROM_NXID 269 #define CONFIG_SYS_EEPROM_BUS_NUM 0 270 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 271 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 272 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 273 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 274 275 /* 276 * DDR Setup 277 */ 278 #define CONFIG_VERY_BIG_RAM 279 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 280 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 281 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 282 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 283 #define CONFIG_FSL_DDR_INTERACTIVE 284 #if defined(CONFIG_T1024RDB) 285 #define CONFIG_DDR_SPD 286 #define CONFIG_SYS_FSL_DDR3 287 #define CONFIG_SYS_SPD_BUS_NUM 0 288 #define SPD_EEPROM_ADDRESS 0x51 289 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 290 #elif defined(CONFIG_T1023RDB) 291 #define CONFIG_SYS_FSL_DDR4 292 #define CONFIG_SYS_DDR_RAW_TIMING 293 #define CONFIG_SYS_SDRAM_SIZE 2048 294 #endif 295 296 /* 297 * IFC Definitions 298 */ 299 #define CONFIG_SYS_FLASH_BASE 0xe8000000 300 #ifdef CONFIG_PHYS_64BIT 301 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 302 #else 303 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 304 #endif 305 306 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 307 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 308 CSPR_PORT_SIZE_16 | \ 309 CSPR_MSEL_NOR | \ 310 CSPR_V) 311 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 312 313 /* NOR Flash Timing Params */ 314 #if defined(CONFIG_T1024RDB) 315 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 316 #elif defined(CONFIG_T1023RDB) 317 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 318 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 319 #endif 320 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 321 FTIM0_NOR_TEADC(0x5) | \ 322 FTIM0_NOR_TEAHC(0x5)) 323 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 324 FTIM1_NOR_TRAD_NOR(0x1A) |\ 325 FTIM1_NOR_TSEQRAD_NOR(0x13)) 326 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 327 FTIM2_NOR_TCH(0x4) | \ 328 FTIM2_NOR_TWPH(0x0E) | \ 329 FTIM2_NOR_TWP(0x1c)) 330 #define CONFIG_SYS_NOR_FTIM3 0x0 331 332 #define CONFIG_SYS_FLASH_QUIET_TEST 333 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 334 335 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 336 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 337 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 338 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 339 340 #define CONFIG_SYS_FLASH_EMPTY_INFO 341 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 342 343 #ifdef CONFIG_T1024RDB 344 /* CPLD on IFC */ 345 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 346 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 347 #define CONFIG_SYS_CSPR2_EXT (0xf) 348 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 349 | CSPR_PORT_SIZE_8 \ 350 | CSPR_MSEL_GPCM \ 351 | CSPR_V) 352 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 353 #define CONFIG_SYS_CSOR2 0x0 354 355 /* CPLD Timing parameters for IFC CS2 */ 356 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 357 FTIM0_GPCM_TEADC(0x0e) | \ 358 FTIM0_GPCM_TEAHC(0x0e)) 359 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 360 FTIM1_GPCM_TRAD(0x1f)) 361 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 362 FTIM2_GPCM_TCH(0x8) | \ 363 FTIM2_GPCM_TWP(0x1f)) 364 #define CONFIG_SYS_CS2_FTIM3 0x0 365 #endif 366 367 /* NAND Flash on IFC */ 368 #define CONFIG_NAND_FSL_IFC 369 #define CONFIG_SYS_NAND_BASE 0xff800000 370 #ifdef CONFIG_PHYS_64BIT 371 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 372 #else 373 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 374 #endif 375 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 376 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 377 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 378 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 379 | CSPR_V) 380 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 381 382 #if defined(CONFIG_T1024RDB) 383 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 384 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 385 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 386 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 387 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 388 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 389 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 390 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 391 #elif defined(CONFIG_T1023RDB) 392 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 393 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 394 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 395 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 396 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 397 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 398 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 399 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 400 #endif 401 402 #define CONFIG_SYS_NAND_ONFI_DETECTION 403 /* ONFI NAND Flash mode0 Timing Params */ 404 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 405 FTIM0_NAND_TWP(0x18) | \ 406 FTIM0_NAND_TWCHT(0x07) | \ 407 FTIM0_NAND_TWH(0x0a)) 408 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 409 FTIM1_NAND_TWBE(0x39) | \ 410 FTIM1_NAND_TRR(0x0e) | \ 411 FTIM1_NAND_TRP(0x18)) 412 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 413 FTIM2_NAND_TREH(0x0a) | \ 414 FTIM2_NAND_TWHRE(0x1e)) 415 #define CONFIG_SYS_NAND_FTIM3 0x0 416 417 #define CONFIG_SYS_NAND_DDR_LAW 11 418 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 419 #define CONFIG_SYS_MAX_NAND_DEVICE 1 420 #define CONFIG_CMD_NAND 421 422 #if defined(CONFIG_NAND) 423 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 424 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 425 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 426 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 427 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 428 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 429 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 430 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 431 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 432 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 433 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 434 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 435 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 436 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 437 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 438 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 439 #else 440 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 441 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 442 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 443 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 444 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 445 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 446 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 447 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 448 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 449 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 450 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 451 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 452 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 453 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 454 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 455 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 456 #endif 457 458 #ifdef CONFIG_SPL_BUILD 459 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 460 #else 461 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 462 #endif 463 464 #if defined(CONFIG_RAMBOOT_PBL) 465 #define CONFIG_SYS_RAMBOOT 466 #endif 467 468 #define CONFIG_BOARD_EARLY_INIT_R 469 #define CONFIG_MISC_INIT_R 470 471 #define CONFIG_HWCONFIG 472 473 /* define to use L1 as initial stack */ 474 #define CONFIG_L1_INIT_RAM 475 #define CONFIG_SYS_INIT_RAM_LOCK 476 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 477 #ifdef CONFIG_PHYS_64BIT 478 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 479 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 480 /* The assembler doesn't like typecast */ 481 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 482 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 483 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 484 #else 485 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 486 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 487 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 488 #endif 489 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 490 491 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 492 GENERATED_GBL_DATA_SIZE) 493 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 494 495 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 496 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 497 498 /* Serial Port */ 499 #define CONFIG_CONS_INDEX 1 500 #define CONFIG_SYS_NS16550_SERIAL 501 #define CONFIG_SYS_NS16550_REG_SIZE 1 502 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 503 504 #define CONFIG_SYS_BAUDRATE_TABLE \ 505 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 506 507 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 508 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 509 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 510 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 511 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 512 513 /* Video */ 514 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 515 #ifdef CONFIG_FSL_DIU_FB 516 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 517 #define CONFIG_VIDEO 518 #define CONFIG_CMD_BMP 519 #define CONFIG_CFB_CONSOLE 520 #define CONFIG_VIDEO_SW_CURSOR 521 #define CONFIG_VGA_AS_SINGLE_DEVICE 522 #define CONFIG_VIDEO_LOGO 523 #define CONFIG_VIDEO_BMP_LOGO 524 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 525 /* 526 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 527 * disable empty flash sector detection, which is I/O-intensive. 528 */ 529 #undef CONFIG_SYS_FLASH_EMPTY_INFO 530 #endif 531 532 /* I2C */ 533 #define CONFIG_SYS_I2C 534 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 535 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 536 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 537 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 538 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 539 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 540 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 541 542 #define I2C_PCA6408_BUS_NUM 1 543 #define I2C_PCA6408_ADDR 0x20 544 545 /* I2C bus multiplexer */ 546 #define I2C_MUX_CH_DEFAULT 0x8 547 548 /* 549 * RTC configuration 550 */ 551 #define RTC 552 #define CONFIG_RTC_DS1337 1 553 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 554 555 /* 556 * eSPI - Enhanced SPI 557 */ 558 #define CONFIG_SPI_FLASH_BAR 559 #define CONFIG_SF_DEFAULT_SPEED 10000000 560 #define CONFIG_SF_DEFAULT_MODE 0 561 562 /* 563 * General PCIe 564 * Memory space is mapped 1-1, but I/O space must start from 0. 565 */ 566 #define CONFIG_PCI /* Enable PCI/PCIE */ 567 #define CONFIG_PCIE1 /* PCIE controler 1 */ 568 #define CONFIG_PCIE2 /* PCIE controler 2 */ 569 #define CONFIG_PCIE3 /* PCIE controler 3 */ 570 #ifdef CONFIG_PPC_T1040 571 #define CONFIG_PCIE4 /* PCIE controler 4 */ 572 #endif 573 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 574 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 575 #define CONFIG_PCI_INDIRECT_BRIDGE 576 577 #ifdef CONFIG_PCI 578 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 579 #ifdef CONFIG_PCIE1 580 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 581 #ifdef CONFIG_PHYS_64BIT 582 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 583 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 584 #else 585 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 586 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 587 #endif 588 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 589 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 590 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 591 #ifdef CONFIG_PHYS_64BIT 592 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 593 #else 594 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 595 #endif 596 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 597 #endif 598 599 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 600 #ifdef CONFIG_PCIE2 601 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 602 #ifdef CONFIG_PHYS_64BIT 603 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 604 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 605 #else 606 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 607 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 608 #endif 609 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 610 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 611 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 612 #ifdef CONFIG_PHYS_64BIT 613 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 614 #else 615 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 616 #endif 617 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 618 #endif 619 620 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 621 #ifdef CONFIG_PCIE3 622 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 623 #ifdef CONFIG_PHYS_64BIT 624 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 625 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 626 #else 627 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 628 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 629 #endif 630 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 631 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 632 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 633 #ifdef CONFIG_PHYS_64BIT 634 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 635 #else 636 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 637 #endif 638 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 639 #endif 640 641 /* controller 4, Base address 203000, to be removed */ 642 #ifdef CONFIG_PCIE4 643 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 644 #ifdef CONFIG_PHYS_64BIT 645 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 646 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 647 #else 648 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 649 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 650 #endif 651 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 652 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 653 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 654 #ifdef CONFIG_PHYS_64BIT 655 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 656 #else 657 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 658 #endif 659 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 660 #endif 661 662 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 663 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 664 #define CONFIG_DOS_PARTITION 665 #endif /* CONFIG_PCI */ 666 667 /* 668 * USB 669 */ 670 #define CONFIG_HAS_FSL_DR_USB 671 672 #ifdef CONFIG_HAS_FSL_DR_USB 673 #define CONFIG_USB_EHCI 674 #define CONFIG_USB_STORAGE 675 #define CONFIG_USB_EHCI_FSL 676 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 677 #define CONFIG_CMD_EXT2 678 #endif 679 680 /* 681 * SDHC 682 */ 683 #define CONFIG_MMC 684 #ifdef CONFIG_MMC 685 #define CONFIG_FSL_ESDHC 686 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 687 #define CONFIG_CMD_MMC 688 #define CONFIG_GENERIC_MMC 689 #define CONFIG_CMD_EXT2 690 #define CONFIG_CMD_FAT 691 #define CONFIG_DOS_PARTITION 692 #endif 693 694 /* Qman/Bman */ 695 #ifndef CONFIG_NOBQFMAN 696 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 697 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 698 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 699 #ifdef CONFIG_PHYS_64BIT 700 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 701 #else 702 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 703 #endif 704 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 705 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 706 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 707 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 708 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 709 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 710 CONFIG_SYS_BMAN_CENA_SIZE) 711 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 712 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 713 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 714 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 715 #ifdef CONFIG_PHYS_64BIT 716 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 717 #else 718 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 719 #endif 720 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 721 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 722 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 723 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 724 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 725 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 726 CONFIG_SYS_QMAN_CENA_SIZE) 727 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 728 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 729 730 #define CONFIG_SYS_DPAA_FMAN 731 732 #ifdef CONFIG_T1024RDB 733 #define CONFIG_QE 734 #define CONFIG_U_QE 735 #endif 736 /* Default address of microcode for the Linux FMan driver */ 737 #if defined(CONFIG_SPIFLASH) 738 /* 739 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 740 * env, so we got 0x110000. 741 */ 742 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 743 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 744 #define CONFIG_SYS_QE_FW_ADDR 0x130000 745 #elif defined(CONFIG_SDCARD) 746 /* 747 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 748 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 749 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 750 */ 751 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 752 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 753 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 754 #elif defined(CONFIG_NAND) 755 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 756 #if defined(CONFIG_T1024RDB) 757 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 758 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 759 #elif defined(CONFIG_T1023RDB) 760 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 761 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 762 #endif 763 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 764 /* 765 * Slave has no ucode locally, it can fetch this from remote. When implementing 766 * in two corenet boards, slave's ucode could be stored in master's memory 767 * space, the address can be mapped from slave TLB->slave LAW-> 768 * slave SRIO or PCIE outbound window->master inbound window-> 769 * master LAW->the ucode address in master's memory space. 770 */ 771 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 772 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 773 #else 774 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 775 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 776 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 777 #endif 778 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 779 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 780 #endif /* CONFIG_NOBQFMAN */ 781 782 #ifdef CONFIG_SYS_DPAA_FMAN 783 #define CONFIG_FMAN_ENET 784 #define CONFIG_PHYLIB_10G 785 #define CONFIG_PHY_REALTEK 786 #define CONFIG_PHY_AQUANTIA 787 #if defined(CONFIG_T1024RDB) 788 #define RGMII_PHY1_ADDR 0x2 789 #define RGMII_PHY2_ADDR 0x6 790 #define SGMII_AQR_PHY_ADDR 0x2 791 #define FM1_10GEC1_PHY_ADDR 0x1 792 #elif defined(CONFIG_T1023RDB) 793 #define RGMII_PHY1_ADDR 0x1 794 #define SGMII_RTK_PHY_ADDR 0x3 795 #define SGMII_AQR_PHY_ADDR 0x2 796 #endif 797 #endif 798 799 #ifdef CONFIG_FMAN_ENET 800 #define CONFIG_MII /* MII PHY management */ 801 #define CONFIG_ETHPRIME "FM1@DTSEC4" 802 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 803 #endif 804 805 /* 806 * Dynamic MTD Partition support with mtdparts 807 */ 808 #ifndef CONFIG_SYS_NO_FLASH 809 #define CONFIG_MTD_DEVICE 810 #define CONFIG_MTD_PARTITIONS 811 #define CONFIG_CMD_MTDPARTS 812 #define CONFIG_FLASH_CFI_MTD 813 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 814 "spi0=spife110000.1" 815 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 816 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 817 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 818 "1m(uboot),5m(kernel),128k(dtb),-(user)" 819 #endif 820 821 /* 822 * Environment 823 */ 824 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 825 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 826 827 /* 828 * Command line configuration. 829 */ 830 #define CONFIG_CMD_DATE 831 #define CONFIG_CMD_EEPROM 832 #define CONFIG_CMD_ERRATA 833 #define CONFIG_CMD_GREPENV 834 #define CONFIG_CMD_IRQ 835 #define CONFIG_CMD_MII 836 #define CONFIG_CMD_REGINFO 837 838 #ifdef CONFIG_PCI 839 #define CONFIG_CMD_PCI 840 #endif 841 842 /* 843 * Miscellaneous configurable options 844 */ 845 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 846 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 847 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 848 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 849 #ifdef CONFIG_CMD_KGDB 850 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 851 #else 852 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 853 #endif 854 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 855 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 856 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 857 858 /* 859 * For booting Linux, the board info and command line data 860 * have to be in the first 64 MB of memory, since this is 861 * the maximum mapped by the Linux kernel during initialization. 862 */ 863 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 864 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 865 866 #ifdef CONFIG_CMD_KGDB 867 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 868 #endif 869 870 /* 871 * Environment Configuration 872 */ 873 #define CONFIG_ROOTPATH "/opt/nfsroot" 874 #define CONFIG_BOOTFILE "uImage" 875 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 876 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 877 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 878 #define CONFIG_BAUDRATE 115200 879 #define __USB_PHY_TYPE utmi 880 881 #ifdef CONFIG_PPC_T1024 882 #define CONFIG_BOARDNAME t1024rdb 883 #define BANK_INTLV cs0_cs1 884 #else 885 #define CONFIG_BOARDNAME t1023rdb 886 #define BANK_INTLV null 887 #endif 888 889 #define CONFIG_EXTRA_ENV_SETTINGS \ 890 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 891 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 892 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 893 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 894 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 895 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 896 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 897 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 898 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 899 "netdev=eth0\0" \ 900 "tftpflash=tftpboot $loadaddr $uboot && " \ 901 "protect off $ubootaddr +$filesize && " \ 902 "erase $ubootaddr +$filesize && " \ 903 "cp.b $loadaddr $ubootaddr $filesize && " \ 904 "protect on $ubootaddr +$filesize && " \ 905 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 906 "consoledev=ttyS0\0" \ 907 "ramdiskaddr=2000000\0" \ 908 "fdtaddr=c00000\0" \ 909 "bdev=sda3\0" 910 911 #define CONFIG_LINUX \ 912 "setenv bootargs root=/dev/ram rw " \ 913 "console=$consoledev,$baudrate $othbootargs;" \ 914 "setenv ramdiskaddr 0x02000000;" \ 915 "setenv fdtaddr 0x00c00000;" \ 916 "setenv loadaddr 0x1000000;" \ 917 "bootm $loadaddr $ramdiskaddr $fdtaddr" 918 919 920 #define CONFIG_NFSBOOTCOMMAND \ 921 "setenv bootargs root=/dev/nfs rw " \ 922 "nfsroot=$serverip:$rootpath " \ 923 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 924 "console=$consoledev,$baudrate $othbootargs;" \ 925 "tftp $loadaddr $bootfile;" \ 926 "tftp $fdtaddr $fdtfile;" \ 927 "bootm $loadaddr - $fdtaddr" 928 929 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 930 931 /* Hash command with SHA acceleration supported in hardware */ 932 #ifdef CONFIG_FSL_CAAM 933 #define CONFIG_CMD_HASH 934 #define CONFIG_SHA_HW_ACCEL 935 #endif 936 937 #include <asm/fsl_secure_boot.h> 938 939 #endif /* __T1024RDB_H */ 940