1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_PHYS_64BIT 22 #define CONFIG_ENABLE_36BIT_PHYS 23 24 #ifdef CONFIG_PHYS_64BIT 25 #define CONFIG_ADDR_MAP 1 26 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 27 #endif 28 29 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 30 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 31 #define CONFIG_FSL_IFC /* Enable IFC Support */ 32 33 #define CONFIG_FSL_LAW /* Use common FSL init code */ 34 #define CONFIG_ENV_OVERWRITE 35 36 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 37 38 /* support deep sleep */ 39 #ifdef CONFIG_PPC_T1024 40 #define CONFIG_DEEP_SLEEP 41 #endif 42 #if defined(CONFIG_DEEP_SLEEP) 43 #define CONFIG_SILENT_CONSOLE 44 #define CONFIG_BOARD_EARLY_INIT_F 45 #endif 46 47 #ifdef CONFIG_RAMBOOT_PBL 48 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 49 #if defined(CONFIG_T1024RDB) 50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg 51 #elif defined(CONFIG_T1023RDB) 52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg 53 #endif 54 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 55 #define CONFIG_SPL_ENV_SUPPORT 56 #define CONFIG_SPL_SERIAL_SUPPORT 57 #define CONFIG_SPL_FLUSH_IMAGE 58 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 59 #define CONFIG_SPL_LIBGENERIC_SUPPORT 60 #define CONFIG_SPL_LIBCOMMON_SUPPORT 61 #define CONFIG_SPL_I2C_SUPPORT 62 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 63 #define CONFIG_FSL_LAW /* Use common FSL init code */ 64 #define CONFIG_SYS_TEXT_BASE 0x30001000 65 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 66 #define CONFIG_SPL_PAD_TO 0x40000 67 #define CONFIG_SPL_MAX_SIZE 0x28000 68 #define RESET_VECTOR_OFFSET 0x27FFC 69 #define BOOT_PAGE_OFFSET 0x27000 70 #ifdef CONFIG_SPL_BUILD 71 #define CONFIG_SPL_SKIP_RELOCATE 72 #define CONFIG_SPL_COMMON_INIT_DDR 73 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 74 #define CONFIG_SYS_NO_FLASH 75 #endif 76 77 #ifdef CONFIG_NAND 78 #define CONFIG_SPL_NAND_SUPPORT 79 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 80 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 81 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 82 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 83 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 84 #define CONFIG_SPL_NAND_BOOT 85 #endif 86 87 #ifdef CONFIG_SPIFLASH 88 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 89 #define CONFIG_SPL_SPI_SUPPORT 90 #define CONFIG_SPL_SPI_FLASH_SUPPORT 91 #define CONFIG_SPL_SPI_FLASH_MINIMAL 92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 94 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 95 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 96 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 97 #ifndef CONFIG_SPL_BUILD 98 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 99 #endif 100 #define CONFIG_SPL_SPI_BOOT 101 #endif 102 103 #ifdef CONFIG_SDCARD 104 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 105 #define CONFIG_SPL_MMC_SUPPORT 106 #define CONFIG_SPL_MMC_MINIMAL 107 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 108 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 109 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 110 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 111 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 112 #ifndef CONFIG_SPL_BUILD 113 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 114 #endif 115 #define CONFIG_SPL_MMC_BOOT 116 #endif 117 118 #endif /* CONFIG_RAMBOOT_PBL */ 119 120 #ifndef CONFIG_SYS_TEXT_BASE 121 #define CONFIG_SYS_TEXT_BASE 0xeff40000 122 #endif 123 124 #ifndef CONFIG_RESET_VECTOR_ADDRESS 125 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 126 #endif 127 128 #ifndef CONFIG_SYS_NO_FLASH 129 #define CONFIG_FLASH_CFI_DRIVER 130 #define CONFIG_SYS_FLASH_CFI 131 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 132 #endif 133 134 /* PCIe Boot - Master */ 135 #define CONFIG_SRIO_PCIE_BOOT_MASTER 136 /* 137 * for slave u-boot IMAGE instored in master memory space, 138 * PHYS must be aligned based on the SIZE 139 */ 140 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 141 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 142 #ifdef CONFIG_PHYS_64BIT 143 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 144 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 145 #else 146 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 147 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 148 #endif 149 /* 150 * for slave UCODE and ENV instored in master memory space, 151 * PHYS must be aligned based on the SIZE 152 */ 153 #ifdef CONFIG_PHYS_64BIT 154 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 155 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 156 #else 157 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 158 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 159 #endif 160 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 161 /* slave core release by master*/ 162 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 163 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 164 165 /* PCIe Boot - Slave */ 166 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 167 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 168 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 169 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 170 /* Set 1M boot space for PCIe boot */ 171 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 172 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 173 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 174 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 175 #define CONFIG_SYS_NO_FLASH 176 #endif 177 178 #if defined(CONFIG_SPIFLASH) 179 #define CONFIG_SYS_EXTRA_ENV_RELOC 180 #define CONFIG_ENV_IS_IN_SPI_FLASH 181 #define CONFIG_ENV_SPI_BUS 0 182 #define CONFIG_ENV_SPI_CS 0 183 #define CONFIG_ENV_SPI_MAX_HZ 10000000 184 #define CONFIG_ENV_SPI_MODE 0 185 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 186 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 187 #if defined(CONFIG_T1024RDB) 188 #define CONFIG_ENV_SECT_SIZE 0x10000 189 #elif defined(CONFIG_T1023RDB) 190 #define CONFIG_ENV_SECT_SIZE 0x40000 191 #endif 192 #elif defined(CONFIG_SDCARD) 193 #define CONFIG_SYS_EXTRA_ENV_RELOC 194 #define CONFIG_ENV_IS_IN_MMC 195 #define CONFIG_SYS_MMC_ENV_DEV 0 196 #define CONFIG_ENV_SIZE 0x2000 197 #define CONFIG_ENV_OFFSET (512 * 0x800) 198 #elif defined(CONFIG_NAND) 199 #define CONFIG_SYS_EXTRA_ENV_RELOC 200 #define CONFIG_ENV_IS_IN_NAND 201 #define CONFIG_ENV_SIZE 0x2000 202 #if defined(CONFIG_T1024RDB) 203 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 204 #elif defined(CONFIG_T1023RDB) 205 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 206 #endif 207 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 208 #define CONFIG_ENV_IS_IN_REMOTE 209 #define CONFIG_ENV_ADDR 0xffe20000 210 #define CONFIG_ENV_SIZE 0x2000 211 #elif defined(CONFIG_ENV_IS_NOWHERE) 212 #define CONFIG_ENV_SIZE 0x2000 213 #else 214 #define CONFIG_ENV_IS_IN_FLASH 215 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 216 #define CONFIG_ENV_SIZE 0x2000 217 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 218 #endif 219 220 221 #ifndef __ASSEMBLY__ 222 unsigned long get_board_sys_clk(void); 223 unsigned long get_board_ddr_clk(void); 224 #endif 225 226 #define CONFIG_SYS_CLK_FREQ 100000000 227 #define CONFIG_DDR_CLK_FREQ 100000000 228 229 /* 230 * These can be toggled for performance analysis, otherwise use default. 231 */ 232 #define CONFIG_SYS_CACHE_STASHING 233 #define CONFIG_BACKSIDE_L2_CACHE 234 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 235 #define CONFIG_BTB /* toggle branch predition */ 236 #define CONFIG_DDR_ECC 237 #ifdef CONFIG_DDR_ECC 238 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 239 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 240 #endif 241 242 #define CONFIG_CMD_MEMTEST 243 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 244 #define CONFIG_SYS_MEMTEST_END 0x00400000 245 #define CONFIG_SYS_ALT_MEMTEST 246 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 247 248 /* 249 * Config the L3 Cache as L3 SRAM 250 */ 251 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 252 #define CONFIG_SYS_L3_SIZE (256 << 10) 253 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 254 #ifdef CONFIG_RAMBOOT_PBL 255 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 256 #endif 257 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 258 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 259 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 260 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 261 262 #ifdef CONFIG_PHYS_64BIT 263 #define CONFIG_SYS_DCSRBAR 0xf0000000 264 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 265 #endif 266 267 /* EEPROM */ 268 #define CONFIG_ID_EEPROM 269 #define CONFIG_SYS_I2C_EEPROM_NXID 270 #define CONFIG_SYS_EEPROM_BUS_NUM 0 271 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 272 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 273 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 274 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 275 276 /* 277 * DDR Setup 278 */ 279 #define CONFIG_VERY_BIG_RAM 280 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 281 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 282 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 283 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 284 #define CONFIG_FSL_DDR_INTERACTIVE 285 #if defined(CONFIG_T1024RDB) 286 #define CONFIG_DDR_SPD 287 #define CONFIG_SYS_FSL_DDR3 288 #define CONFIG_SYS_SPD_BUS_NUM 0 289 #define SPD_EEPROM_ADDRESS 0x51 290 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 291 #elif defined(CONFIG_T1023RDB) 292 #define CONFIG_SYS_FSL_DDR4 293 #define CONFIG_SYS_DDR_RAW_TIMING 294 #define CONFIG_SYS_SDRAM_SIZE 2048 295 #endif 296 297 /* 298 * IFC Definitions 299 */ 300 #define CONFIG_SYS_FLASH_BASE 0xe8000000 301 #ifdef CONFIG_PHYS_64BIT 302 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 303 #else 304 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 305 #endif 306 307 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 308 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 309 CSPR_PORT_SIZE_16 | \ 310 CSPR_MSEL_NOR | \ 311 CSPR_V) 312 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 313 314 /* NOR Flash Timing Params */ 315 #if defined(CONFIG_T1024RDB) 316 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 317 #elif defined(CONFIG_T1023RDB) 318 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 319 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 320 #endif 321 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 322 FTIM0_NOR_TEADC(0x5) | \ 323 FTIM0_NOR_TEAHC(0x5)) 324 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 325 FTIM1_NOR_TRAD_NOR(0x1A) |\ 326 FTIM1_NOR_TSEQRAD_NOR(0x13)) 327 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 328 FTIM2_NOR_TCH(0x4) | \ 329 FTIM2_NOR_TWPH(0x0E) | \ 330 FTIM2_NOR_TWP(0x1c)) 331 #define CONFIG_SYS_NOR_FTIM3 0x0 332 333 #define CONFIG_SYS_FLASH_QUIET_TEST 334 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 335 336 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 337 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 338 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 339 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 340 341 #define CONFIG_SYS_FLASH_EMPTY_INFO 342 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 343 344 #ifdef CONFIG_T1024RDB 345 /* CPLD on IFC */ 346 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 347 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 348 #define CONFIG_SYS_CSPR2_EXT (0xf) 349 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 350 | CSPR_PORT_SIZE_8 \ 351 | CSPR_MSEL_GPCM \ 352 | CSPR_V) 353 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 354 #define CONFIG_SYS_CSOR2 0x0 355 356 /* CPLD Timing parameters for IFC CS2 */ 357 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 358 FTIM0_GPCM_TEADC(0x0e) | \ 359 FTIM0_GPCM_TEAHC(0x0e)) 360 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 361 FTIM1_GPCM_TRAD(0x1f)) 362 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 363 FTIM2_GPCM_TCH(0x8) | \ 364 FTIM2_GPCM_TWP(0x1f)) 365 #define CONFIG_SYS_CS2_FTIM3 0x0 366 #endif 367 368 /* NAND Flash on IFC */ 369 #define CONFIG_NAND_FSL_IFC 370 #define CONFIG_SYS_NAND_BASE 0xff800000 371 #ifdef CONFIG_PHYS_64BIT 372 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 373 #else 374 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 375 #endif 376 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 377 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 378 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 379 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 380 | CSPR_V) 381 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 382 383 #if defined(CONFIG_T1024RDB) 384 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 385 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 386 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 387 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 388 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 389 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 390 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 391 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 392 #elif defined(CONFIG_T1023RDB) 393 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 394 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 395 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 396 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 397 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 398 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 399 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 400 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 401 #endif 402 403 #define CONFIG_SYS_NAND_ONFI_DETECTION 404 /* ONFI NAND Flash mode0 Timing Params */ 405 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 406 FTIM0_NAND_TWP(0x18) | \ 407 FTIM0_NAND_TWCHT(0x07) | \ 408 FTIM0_NAND_TWH(0x0a)) 409 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 410 FTIM1_NAND_TWBE(0x39) | \ 411 FTIM1_NAND_TRR(0x0e) | \ 412 FTIM1_NAND_TRP(0x18)) 413 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 414 FTIM2_NAND_TREH(0x0a) | \ 415 FTIM2_NAND_TWHRE(0x1e)) 416 #define CONFIG_SYS_NAND_FTIM3 0x0 417 418 #define CONFIG_SYS_NAND_DDR_LAW 11 419 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 420 #define CONFIG_SYS_MAX_NAND_DEVICE 1 421 #define CONFIG_CMD_NAND 422 423 #if defined(CONFIG_NAND) 424 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 425 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 426 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 427 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 428 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 429 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 430 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 431 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 432 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 433 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 434 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 435 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 436 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 437 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 438 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 439 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 440 #else 441 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 442 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 443 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 444 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 445 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 446 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 447 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 448 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 449 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 450 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 451 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 452 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 453 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 454 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 455 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 456 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 457 #endif 458 459 #ifdef CONFIG_SPL_BUILD 460 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 461 #else 462 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 463 #endif 464 465 #if defined(CONFIG_RAMBOOT_PBL) 466 #define CONFIG_SYS_RAMBOOT 467 #endif 468 469 #define CONFIG_BOARD_EARLY_INIT_R 470 #define CONFIG_MISC_INIT_R 471 472 #define CONFIG_HWCONFIG 473 474 /* define to use L1 as initial stack */ 475 #define CONFIG_L1_INIT_RAM 476 #define CONFIG_SYS_INIT_RAM_LOCK 477 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 478 #ifdef CONFIG_PHYS_64BIT 479 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 480 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 481 /* The assembler doesn't like typecast */ 482 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 483 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 484 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 485 #else 486 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 487 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 488 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 489 #endif 490 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 491 492 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 493 GENERATED_GBL_DATA_SIZE) 494 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 495 496 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 497 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 498 499 /* Serial Port */ 500 #define CONFIG_CONS_INDEX 1 501 #define CONFIG_SYS_NS16550_SERIAL 502 #define CONFIG_SYS_NS16550_REG_SIZE 1 503 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 504 505 #define CONFIG_SYS_BAUDRATE_TABLE \ 506 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 507 508 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 509 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 510 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 511 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 512 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 513 514 /* Use the HUSH parser */ 515 #define CONFIG_SYS_HUSH_PARSER 516 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 517 518 /* Video */ 519 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 520 #ifdef CONFIG_FSL_DIU_FB 521 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 522 #define CONFIG_VIDEO 523 #define CONFIG_CMD_BMP 524 #define CONFIG_CFB_CONSOLE 525 #define CONFIG_VIDEO_SW_CURSOR 526 #define CONFIG_VGA_AS_SINGLE_DEVICE 527 #define CONFIG_VIDEO_LOGO 528 #define CONFIG_VIDEO_BMP_LOGO 529 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 530 /* 531 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 532 * disable empty flash sector detection, which is I/O-intensive. 533 */ 534 #undef CONFIG_SYS_FLASH_EMPTY_INFO 535 #endif 536 537 /* pass open firmware flat tree */ 538 #define CONFIG_OF_BOARD_SETUP 539 #define CONFIG_OF_STDOUT_VIA_ALIAS 540 541 /* new uImage format support */ 542 #define CONFIG_FIT 543 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 544 545 /* I2C */ 546 #define CONFIG_SYS_I2C 547 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 548 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 549 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 550 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 551 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 552 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 553 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 554 555 #define I2C_PCA6408_BUS_NUM 1 556 #define I2C_PCA6408_ADDR 0x20 557 558 /* I2C bus multiplexer */ 559 #define I2C_MUX_CH_DEFAULT 0x8 560 561 /* 562 * RTC configuration 563 */ 564 #define RTC 565 #define CONFIG_RTC_DS1337 1 566 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 567 568 /* 569 * eSPI - Enhanced SPI 570 */ 571 #if defined(CONFIG_T1024RDB) 572 #elif defined(CONFIG_T1023RDB) 573 #endif 574 #define CONFIG_CMD_SF 575 #define CONFIG_SPI_FLASH_BAR 576 #define CONFIG_SF_DEFAULT_SPEED 10000000 577 #define CONFIG_SF_DEFAULT_MODE 0 578 579 /* 580 * General PCIe 581 * Memory space is mapped 1-1, but I/O space must start from 0. 582 */ 583 #define CONFIG_PCI /* Enable PCI/PCIE */ 584 #define CONFIG_PCIE1 /* PCIE controler 1 */ 585 #define CONFIG_PCIE2 /* PCIE controler 2 */ 586 #define CONFIG_PCIE3 /* PCIE controler 3 */ 587 #ifdef CONFIG_PPC_T1040 588 #define CONFIG_PCIE4 /* PCIE controler 4 */ 589 #endif 590 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 591 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 592 #define CONFIG_PCI_INDIRECT_BRIDGE 593 594 #ifdef CONFIG_PCI 595 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 596 #ifdef CONFIG_PCIE1 597 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 598 #ifdef CONFIG_PHYS_64BIT 599 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 600 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 601 #else 602 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 603 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 604 #endif 605 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 606 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 607 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 608 #ifdef CONFIG_PHYS_64BIT 609 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 610 #else 611 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 612 #endif 613 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 614 #endif 615 616 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 617 #ifdef CONFIG_PCIE2 618 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 619 #ifdef CONFIG_PHYS_64BIT 620 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 621 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 622 #else 623 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 624 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 625 #endif 626 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 627 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 628 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 629 #ifdef CONFIG_PHYS_64BIT 630 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 631 #else 632 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 633 #endif 634 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 635 #endif 636 637 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 638 #ifdef CONFIG_PCIE3 639 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 640 #ifdef CONFIG_PHYS_64BIT 641 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 642 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 643 #else 644 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 645 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 646 #endif 647 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 648 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 649 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 650 #ifdef CONFIG_PHYS_64BIT 651 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 652 #else 653 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 654 #endif 655 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 656 #endif 657 658 /* controller 4, Base address 203000, to be removed */ 659 #ifdef CONFIG_PCIE4 660 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 661 #ifdef CONFIG_PHYS_64BIT 662 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 663 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 664 #else 665 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 666 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 667 #endif 668 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 669 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 670 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 671 #ifdef CONFIG_PHYS_64BIT 672 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 673 #else 674 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 675 #endif 676 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 677 #endif 678 679 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 680 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 681 #define CONFIG_DOS_PARTITION 682 #endif /* CONFIG_PCI */ 683 684 /* 685 * USB 686 */ 687 #define CONFIG_HAS_FSL_DR_USB 688 689 #ifdef CONFIG_HAS_FSL_DR_USB 690 #define CONFIG_USB_EHCI 691 #define CONFIG_CMD_USB 692 #define CONFIG_USB_STORAGE 693 #define CONFIG_USB_EHCI_FSL 694 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 695 #define CONFIG_CMD_EXT2 696 #endif 697 698 /* 699 * SDHC 700 */ 701 #define CONFIG_MMC 702 #ifdef CONFIG_MMC 703 #define CONFIG_FSL_ESDHC 704 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 705 #define CONFIG_CMD_MMC 706 #define CONFIG_GENERIC_MMC 707 #define CONFIG_CMD_EXT2 708 #define CONFIG_CMD_FAT 709 #define CONFIG_DOS_PARTITION 710 #endif 711 712 /* Qman/Bman */ 713 #ifndef CONFIG_NOBQFMAN 714 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 715 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 716 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 717 #ifdef CONFIG_PHYS_64BIT 718 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 719 #else 720 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 721 #endif 722 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 723 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 724 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 725 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 726 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 727 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 728 CONFIG_SYS_BMAN_CENA_SIZE) 729 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 730 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 731 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 732 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 733 #ifdef CONFIG_PHYS_64BIT 734 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 735 #else 736 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 737 #endif 738 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 739 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 740 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 741 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 742 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 743 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 744 CONFIG_SYS_QMAN_CENA_SIZE) 745 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 746 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 747 748 #define CONFIG_SYS_DPAA_FMAN 749 750 #ifdef CONFIG_T1024RDB 751 #define CONFIG_QE 752 #define CONFIG_U_QE 753 #endif 754 /* Default address of microcode for the Linux FMan driver */ 755 #if defined(CONFIG_SPIFLASH) 756 /* 757 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 758 * env, so we got 0x110000. 759 */ 760 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 761 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 762 #define CONFIG_SYS_QE_FW_ADDR 0x130000 763 #elif defined(CONFIG_SDCARD) 764 /* 765 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 766 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 767 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 768 */ 769 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 770 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 771 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 772 #elif defined(CONFIG_NAND) 773 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 774 #if defined(CONFIG_T1024RDB) 775 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 776 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 777 #elif defined(CONFIG_T1023RDB) 778 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 779 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 780 #endif 781 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 782 /* 783 * Slave has no ucode locally, it can fetch this from remote. When implementing 784 * in two corenet boards, slave's ucode could be stored in master's memory 785 * space, the address can be mapped from slave TLB->slave LAW-> 786 * slave SRIO or PCIE outbound window->master inbound window-> 787 * master LAW->the ucode address in master's memory space. 788 */ 789 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 790 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 791 #else 792 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 793 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 794 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 795 #endif 796 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 797 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 798 #endif /* CONFIG_NOBQFMAN */ 799 800 #ifdef CONFIG_SYS_DPAA_FMAN 801 #define CONFIG_FMAN_ENET 802 #define CONFIG_PHYLIB_10G 803 #define CONFIG_PHY_REALTEK 804 #define CONFIG_PHY_AQUANTIA 805 #if defined(CONFIG_T1024RDB) 806 #define RGMII_PHY1_ADDR 0x2 807 #define RGMII_PHY2_ADDR 0x6 808 #define SGMII_AQR_PHY_ADDR 0x2 809 #define FM1_10GEC1_PHY_ADDR 0x1 810 #elif defined(CONFIG_T1023RDB) 811 #define RGMII_PHY1_ADDR 0x1 812 #define SGMII_RTK_PHY_ADDR 0x3 813 #define SGMII_AQR_PHY_ADDR 0x2 814 #endif 815 #endif 816 817 #ifdef CONFIG_FMAN_ENET 818 #define CONFIG_MII /* MII PHY management */ 819 #define CONFIG_ETHPRIME "FM1@DTSEC4" 820 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 821 #endif 822 823 /* 824 * Dynamic MTD Partition support with mtdparts 825 */ 826 #ifndef CONFIG_SYS_NO_FLASH 827 #define CONFIG_MTD_DEVICE 828 #define CONFIG_MTD_PARTITIONS 829 #define CONFIG_CMD_MTDPARTS 830 #define CONFIG_FLASH_CFI_MTD 831 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 832 "spi0=spife110000.1" 833 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 834 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 835 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 836 "1m(uboot),5m(kernel),128k(dtb),-(user)" 837 #endif 838 839 /* 840 * Environment 841 */ 842 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 843 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 844 845 /* 846 * Command line configuration. 847 */ 848 #define CONFIG_CMD_DATE 849 #define CONFIG_CMD_DHCP 850 #define CONFIG_CMD_EEPROM 851 #define CONFIG_CMD_ERRATA 852 #define CONFIG_CMD_GREPENV 853 #define CONFIG_CMD_IRQ 854 #define CONFIG_CMD_I2C 855 #define CONFIG_CMD_MII 856 #define CONFIG_CMD_PING 857 #define CONFIG_CMD_REGINFO 858 859 #ifdef CONFIG_PCI 860 #define CONFIG_CMD_PCI 861 #endif 862 863 /* 864 * Miscellaneous configurable options 865 */ 866 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 867 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 868 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 869 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 870 #ifdef CONFIG_CMD_KGDB 871 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 872 #else 873 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 874 #endif 875 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 876 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 877 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 878 879 /* 880 * For booting Linux, the board info and command line data 881 * have to be in the first 64 MB of memory, since this is 882 * the maximum mapped by the Linux kernel during initialization. 883 */ 884 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 885 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 886 887 #ifdef CONFIG_CMD_KGDB 888 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 889 #endif 890 891 /* 892 * Environment Configuration 893 */ 894 #define CONFIG_ROOTPATH "/opt/nfsroot" 895 #define CONFIG_BOOTFILE "uImage" 896 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 897 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 898 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 899 #define CONFIG_BAUDRATE 115200 900 #define __USB_PHY_TYPE utmi 901 902 #ifdef CONFIG_PPC_T1024 903 #define CONFIG_BOARDNAME t1024rdb 904 #define BANK_INTLV cs0_cs1 905 #else 906 #define CONFIG_BOARDNAME t1023rdb 907 #define BANK_INTLV null 908 #endif 909 910 #define CONFIG_EXTRA_ENV_SETTINGS \ 911 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 912 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 913 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 914 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 915 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 916 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 917 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 918 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 919 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 920 "netdev=eth0\0" \ 921 "tftpflash=tftpboot $loadaddr $uboot && " \ 922 "protect off $ubootaddr +$filesize && " \ 923 "erase $ubootaddr +$filesize && " \ 924 "cp.b $loadaddr $ubootaddr $filesize && " \ 925 "protect on $ubootaddr +$filesize && " \ 926 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 927 "consoledev=ttyS0\0" \ 928 "ramdiskaddr=2000000\0" \ 929 "fdtaddr=c00000\0" \ 930 "bdev=sda3\0" 931 932 #define CONFIG_LINUX \ 933 "setenv bootargs root=/dev/ram rw " \ 934 "console=$consoledev,$baudrate $othbootargs;" \ 935 "setenv ramdiskaddr 0x02000000;" \ 936 "setenv fdtaddr 0x00c00000;" \ 937 "setenv loadaddr 0x1000000;" \ 938 "bootm $loadaddr $ramdiskaddr $fdtaddr" 939 940 941 #define CONFIG_NFSBOOTCOMMAND \ 942 "setenv bootargs root=/dev/nfs rw " \ 943 "nfsroot=$serverip:$rootpath " \ 944 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 945 "console=$consoledev,$baudrate $othbootargs;" \ 946 "tftp $loadaddr $bootfile;" \ 947 "tftp $fdtaddr $fdtfile;" \ 948 "bootm $loadaddr - $fdtaddr" 949 950 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 951 952 /* Hash command with SHA acceleration supported in hardware */ 953 #ifdef CONFIG_FSL_CAAM 954 #define CONFIG_CMD_HASH 955 #define CONFIG_SHA_HW_ACCEL 956 #endif 957 958 #include <asm/fsl_secure_boot.h> 959 960 #endif /* __T1024RDB_H */ 961