1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #ifdef CONFIG_PHYS_64BIT 24 #define CONFIG_ADDR_MAP 1 25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 26 #endif 27 28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 29 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 30 #define CONFIG_FSL_IFC /* Enable IFC Support */ 31 32 #define CONFIG_FSL_LAW /* Use common FSL init code */ 33 #define CONFIG_ENV_OVERWRITE 34 35 #define CONFIG_DEEP_SLEEP 36 #if defined(CONFIG_DEEP_SLEEP) 37 #define CONFIG_SILENT_CONSOLE 38 #define CONFIG_BOARD_EARLY_INIT_F 39 #endif 40 41 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 42 43 #ifdef CONFIG_RAMBOOT_PBL 44 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg 46 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 47 #define CONFIG_SPL_ENV_SUPPORT 48 #define CONFIG_SPL_SERIAL_SUPPORT 49 #define CONFIG_SPL_FLUSH_IMAGE 50 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 51 #define CONFIG_SPL_LIBGENERIC_SUPPORT 52 #define CONFIG_SPL_LIBCOMMON_SUPPORT 53 #define CONFIG_SPL_I2C_SUPPORT 54 #define CONFIG_FSL_LAW /* Use common FSL init code */ 55 #define CONFIG_SYS_TEXT_BASE 0x00201000 56 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 57 #define CONFIG_SPL_PAD_TO 0x40000 58 #define CONFIG_SPL_MAX_SIZE 0x28000 59 #define RESET_VECTOR_OFFSET 0x27FFC 60 #define BOOT_PAGE_OFFSET 0x27000 61 #ifdef CONFIG_SPL_BUILD 62 #define CONFIG_SPL_SKIP_RELOCATE 63 #define CONFIG_SPL_COMMON_INIT_DDR 64 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 65 #define CONFIG_SYS_NO_FLASH 66 #endif 67 68 #ifdef CONFIG_NAND 69 #define CONFIG_SPL_NAND_SUPPORT 70 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 71 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 72 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 73 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 74 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 75 #define CONFIG_SPL_NAND_BOOT 76 #endif 77 78 #ifdef CONFIG_SPIFLASH 79 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 80 #define CONFIG_SPL_SPI_SUPPORT 81 #define CONFIG_SPL_SPI_FLASH_SUPPORT 82 #define CONFIG_SPL_SPI_FLASH_MINIMAL 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 87 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 88 #ifndef CONFIG_SPL_BUILD 89 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 90 #endif 91 #define CONFIG_SPL_SPI_BOOT 92 #endif 93 94 #ifdef CONFIG_SDCARD 95 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 96 #define CONFIG_SPL_MMC_SUPPORT 97 #define CONFIG_SPL_MMC_MINIMAL 98 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 99 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 100 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 101 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 102 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 103 #ifndef CONFIG_SPL_BUILD 104 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 105 #endif 106 #define CONFIG_SPL_MMC_BOOT 107 #endif 108 109 #endif /* CONFIG_RAMBOOT_PBL */ 110 111 #ifndef CONFIG_SYS_TEXT_BASE 112 #define CONFIG_SYS_TEXT_BASE 0xeff40000 113 #endif 114 115 #ifndef CONFIG_RESET_VECTOR_ADDRESS 116 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 117 #endif 118 119 #ifndef CONFIG_SYS_NO_FLASH 120 #define CONFIG_FLASH_CFI_DRIVER 121 #define CONFIG_SYS_FLASH_CFI 122 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 123 #endif 124 125 /* PCIe Boot - Master */ 126 #define CONFIG_SRIO_PCIE_BOOT_MASTER 127 /* 128 * for slave u-boot IMAGE instored in master memory space, 129 * PHYS must be aligned based on the SIZE 130 */ 131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 132 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 133 #ifdef CONFIG_PHYS_64BIT 134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 135 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 136 #else 137 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 138 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 139 #endif 140 /* 141 * for slave UCODE and ENV instored in master memory space, 142 * PHYS must be aligned based on the SIZE 143 */ 144 #ifdef CONFIG_PHYS_64BIT 145 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 146 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 147 #else 148 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 149 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 150 #endif 151 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 152 /* slave core release by master*/ 153 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 154 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 155 156 /* PCIe Boot - Slave */ 157 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 158 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 159 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 160 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 161 /* Set 1M boot space for PCIe boot */ 162 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 163 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 164 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 165 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 166 #define CONFIG_SYS_NO_FLASH 167 #endif 168 169 #if defined(CONFIG_SPIFLASH) 170 #define CONFIG_SYS_EXTRA_ENV_RELOC 171 #define CONFIG_ENV_IS_IN_SPI_FLASH 172 #define CONFIG_ENV_SPI_BUS 0 173 #define CONFIG_ENV_SPI_CS 0 174 #define CONFIG_ENV_SPI_MAX_HZ 10000000 175 #define CONFIG_ENV_SPI_MODE 0 176 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 177 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 178 #define CONFIG_ENV_SECT_SIZE 0x10000 179 #elif defined(CONFIG_SDCARD) 180 #define CONFIG_SYS_EXTRA_ENV_RELOC 181 #define CONFIG_ENV_IS_IN_MMC 182 #define CONFIG_SYS_MMC_ENV_DEV 0 183 #define CONFIG_ENV_SIZE 0x2000 184 #define CONFIG_ENV_OFFSET (512 * 0x800) 185 #elif defined(CONFIG_NAND) 186 #define CONFIG_SYS_EXTRA_ENV_RELOC 187 #define CONFIG_ENV_IS_IN_NAND 188 #define CONFIG_ENV_SIZE 0x2000 189 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 190 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 191 #define CONFIG_ENV_IS_IN_REMOTE 192 #define CONFIG_ENV_ADDR 0xffe20000 193 #define CONFIG_ENV_SIZE 0x2000 194 #elif defined(CONFIG_ENV_IS_NOWHERE) 195 #define CONFIG_ENV_SIZE 0x2000 196 #else 197 #define CONFIG_ENV_IS_IN_FLASH 198 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 199 #define CONFIG_ENV_SIZE 0x2000 200 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 201 #endif 202 203 #ifndef __ASSEMBLY__ 204 unsigned long get_board_sys_clk(void); 205 unsigned long get_board_ddr_clk(void); 206 #endif 207 208 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 209 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 210 211 /* 212 * These can be toggled for performance analysis, otherwise use default. 213 */ 214 #define CONFIG_SYS_CACHE_STASHING 215 #define CONFIG_BACKSIDE_L2_CACHE 216 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 217 #define CONFIG_BTB /* toggle branch predition */ 218 #define CONFIG_DDR_ECC 219 #ifdef CONFIG_DDR_ECC 220 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 221 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 222 #endif 223 224 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 225 #define CONFIG_SYS_MEMTEST_END 0x00400000 226 #define CONFIG_SYS_ALT_MEMTEST 227 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 228 229 /* 230 * Config the L3 Cache as L3 SRAM 231 */ 232 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 233 #define CONFIG_SYS_L3_SIZE (256 << 10) 234 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 235 #ifdef CONFIG_RAMBOOT_PBL 236 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 237 #endif 238 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 239 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 240 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 241 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 242 243 #ifdef CONFIG_PHYS_64BIT 244 #define CONFIG_SYS_DCSRBAR 0xf0000000 245 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 246 #endif 247 248 /* EEPROM */ 249 #define CONFIG_ID_EEPROM 250 #define CONFIG_SYS_I2C_EEPROM_NXID 251 #define CONFIG_SYS_EEPROM_BUS_NUM 0 252 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 253 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 254 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 255 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 256 257 /* 258 * DDR Setup 259 */ 260 #define CONFIG_VERY_BIG_RAM 261 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 262 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 263 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 264 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 265 #define CONFIG_DDR_SPD 266 #ifndef CONFIG_SYS_FSL_DDR4 267 #define CONFIG_SYS_FSL_DDR3 268 #endif 269 270 #define CONFIG_SYS_SPD_BUS_NUM 0 271 #define SPD_EEPROM_ADDRESS 0x51 272 273 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 274 275 /* 276 * IFC Definitions 277 */ 278 #define CONFIG_SYS_FLASH_BASE 0xe0000000 279 #ifdef CONFIG_PHYS_64BIT 280 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 281 #else 282 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 283 #endif 284 285 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 286 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 287 + 0x8000000) | \ 288 CSPR_PORT_SIZE_16 | \ 289 CSPR_MSEL_NOR | \ 290 CSPR_V) 291 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 292 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 293 CSPR_PORT_SIZE_16 | \ 294 CSPR_MSEL_NOR | \ 295 CSPR_V) 296 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 297 /* NOR Flash Timing Params */ 298 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 299 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 300 FTIM0_NOR_TEADC(0x5) | \ 301 FTIM0_NOR_TEAHC(0x5)) 302 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 303 FTIM1_NOR_TRAD_NOR(0x1A) |\ 304 FTIM1_NOR_TSEQRAD_NOR(0x13)) 305 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 306 FTIM2_NOR_TCH(0x4) | \ 307 FTIM2_NOR_TWPH(0x0E) | \ 308 FTIM2_NOR_TWP(0x1c)) 309 #define CONFIG_SYS_NOR_FTIM3 0x0 310 311 #define CONFIG_SYS_FLASH_QUIET_TEST 312 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 313 314 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 315 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 316 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 317 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 318 319 #define CONFIG_SYS_FLASH_EMPTY_INFO 320 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 321 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 322 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 323 #define QIXIS_BASE 0xffdf0000 324 #ifdef CONFIG_PHYS_64BIT 325 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 326 #else 327 #define QIXIS_BASE_PHYS QIXIS_BASE 328 #endif 329 #define QIXIS_LBMAP_SWITCH 0x06 330 #define QIXIS_LBMAP_MASK 0x0f 331 #define QIXIS_LBMAP_SHIFT 0 332 #define QIXIS_LBMAP_DFLTBANK 0x00 333 #define QIXIS_LBMAP_ALTBANK 0x04 334 #define QIXIS_RST_CTL_RESET 0x31 335 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 336 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 337 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 338 #define QIXIS_RST_FORCE_MEM 0x01 339 340 #define CONFIG_SYS_CSPR3_EXT (0xf) 341 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 342 | CSPR_PORT_SIZE_8 \ 343 | CSPR_MSEL_GPCM \ 344 | CSPR_V) 345 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 346 #define CONFIG_SYS_CSOR3 0x0 347 /* QIXIS Timing parameters for IFC CS3 */ 348 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 349 FTIM0_GPCM_TEADC(0x0e) | \ 350 FTIM0_GPCM_TEAHC(0x0e)) 351 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 352 FTIM1_GPCM_TRAD(0x3f)) 353 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 354 FTIM2_GPCM_TCH(0x8) | \ 355 FTIM2_GPCM_TWP(0x1f)) 356 #define CONFIG_SYS_CS3_FTIM3 0x0 357 358 #define CONFIG_NAND_FSL_IFC 359 #define CONFIG_SYS_NAND_BASE 0xff800000 360 #ifdef CONFIG_PHYS_64BIT 361 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 362 #else 363 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 364 #endif 365 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 366 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 367 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 368 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 369 | CSPR_V) 370 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 371 372 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 373 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 374 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 375 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 376 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 377 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 378 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 379 380 #define CONFIG_SYS_NAND_ONFI_DETECTION 381 382 /* ONFI NAND Flash mode0 Timing Params */ 383 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 384 FTIM0_NAND_TWP(0x18) | \ 385 FTIM0_NAND_TWCHT(0x07) | \ 386 FTIM0_NAND_TWH(0x0a)) 387 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 388 FTIM1_NAND_TWBE(0x39) | \ 389 FTIM1_NAND_TRR(0x0e) | \ 390 FTIM1_NAND_TRP(0x18)) 391 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 392 FTIM2_NAND_TREH(0x0a) | \ 393 FTIM2_NAND_TWHRE(0x1e)) 394 #define CONFIG_SYS_NAND_FTIM3 0x0 395 396 #define CONFIG_SYS_NAND_DDR_LAW 11 397 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 398 #define CONFIG_SYS_MAX_NAND_DEVICE 1 399 #define CONFIG_CMD_NAND 400 401 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 402 403 #if defined(CONFIG_NAND) 404 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 405 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 406 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 407 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 408 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 409 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 410 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 411 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 412 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 413 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 414 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 415 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 416 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 417 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 418 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 419 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 420 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 421 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 422 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 423 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 424 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 425 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 426 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 427 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 428 #else 429 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 430 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 431 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 432 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 433 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 434 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 435 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 436 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 437 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 438 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 439 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 440 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 441 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 442 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 443 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 444 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 445 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 446 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 447 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 448 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 449 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 450 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 451 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 452 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 453 #endif 454 455 #ifdef CONFIG_SPL_BUILD 456 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 457 #else 458 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 459 #endif 460 461 #if defined(CONFIG_RAMBOOT_PBL) 462 #define CONFIG_SYS_RAMBOOT 463 #endif 464 465 #define CONFIG_BOARD_EARLY_INIT_R 466 #define CONFIG_MISC_INIT_R 467 468 #define CONFIG_HWCONFIG 469 470 /* define to use L1 as initial stack */ 471 #define CONFIG_L1_INIT_RAM 472 #define CONFIG_SYS_INIT_RAM_LOCK 473 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 474 #ifdef CONFIG_PHYS_64BIT 475 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 476 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 477 /* The assembler doesn't like typecast */ 478 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 479 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 480 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 481 #else 482 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 483 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 484 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 485 #endif 486 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 487 488 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 489 GENERATED_GBL_DATA_SIZE) 490 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 491 492 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 493 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 494 495 /* Serial Port */ 496 #define CONFIG_CONS_INDEX 1 497 #define CONFIG_SYS_NS16550_SERIAL 498 #define CONFIG_SYS_NS16550_REG_SIZE 1 499 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 500 501 #define CONFIG_SYS_BAUDRATE_TABLE \ 502 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 503 504 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 505 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 506 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 507 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 508 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 509 510 /* Video */ 511 #ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */ 512 #define CONFIG_FSL_DIU_FB 513 #ifdef CONFIG_FSL_DIU_FB 514 #define CONFIG_FSL_DIU_CH7301 515 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 516 #define CONFIG_VIDEO 517 #define CONFIG_CMD_BMP 518 #define CONFIG_CFB_CONSOLE 519 #define CONFIG_VIDEO_SW_CURSOR 520 #define CONFIG_VGA_AS_SINGLE_DEVICE 521 #define CONFIG_VIDEO_LOGO 522 #define CONFIG_VIDEO_BMP_LOGO 523 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 524 /* 525 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 526 * disable empty flash sector detection, which is I/O-intensive. 527 */ 528 #undef CONFIG_SYS_FLASH_EMPTY_INFO 529 #endif 530 #endif 531 532 /* I2C */ 533 #define CONFIG_SYS_I2C 534 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 535 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 536 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 537 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 538 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 539 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 540 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 541 542 #define I2C_MUX_PCA_ADDR 0x77 543 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 544 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 545 #define I2C_RETIMER_ADDR 0x18 546 547 /* I2C bus multiplexer */ 548 #define I2C_MUX_CH_DEFAULT 0x8 549 #define I2C_MUX_CH_DIU 0xC 550 #define I2C_MUX_CH5 0xD 551 #define I2C_MUX_CH7 0xF 552 553 /* LDI/DVI Encoder for display */ 554 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 555 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 556 557 /* 558 * RTC configuration 559 */ 560 #define RTC 561 #define CONFIG_RTC_DS3231 1 562 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 563 564 /* 565 * eSPI - Enhanced SPI 566 */ 567 #ifndef CONFIG_SPL_BUILD 568 #endif 569 #define CONFIG_SPI_FLASH_BAR 570 #define CONFIG_SF_DEFAULT_SPEED 10000000 571 #define CONFIG_SF_DEFAULT_MODE 0 572 573 /* 574 * General PCIe 575 * Memory space is mapped 1-1, but I/O space must start from 0. 576 */ 577 #define CONFIG_PCI /* Enable PCI/PCIE */ 578 #define CONFIG_PCIE1 /* PCIE controller 1 */ 579 #define CONFIG_PCIE2 /* PCIE controller 2 */ 580 #define CONFIG_PCIE3 /* PCIE controller 3 */ 581 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 582 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 583 #define CONFIG_PCI_INDIRECT_BRIDGE 584 585 #ifdef CONFIG_PCI 586 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 587 #ifdef CONFIG_PCIE1 588 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 589 #ifdef CONFIG_PHYS_64BIT 590 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 591 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 592 #else 593 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 594 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 595 #endif 596 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 597 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 598 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 599 #ifdef CONFIG_PHYS_64BIT 600 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 601 #else 602 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 603 #endif 604 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 605 #endif 606 607 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 608 #ifdef CONFIG_PCIE2 609 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 610 #ifdef CONFIG_PHYS_64BIT 611 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 612 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 613 #else 614 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 615 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 616 #endif 617 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 618 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 619 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 620 #ifdef CONFIG_PHYS_64BIT 621 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 622 #else 623 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 624 #endif 625 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 626 #endif 627 628 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 629 #ifdef CONFIG_PCIE3 630 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 631 #ifdef CONFIG_PHYS_64BIT 632 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 633 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 634 #else 635 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 636 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 637 #endif 638 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 639 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 640 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 641 #ifdef CONFIG_PHYS_64BIT 642 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 643 #else 644 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 645 #endif 646 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 647 #endif 648 649 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 650 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 651 #define CONFIG_DOS_PARTITION 652 #endif /* CONFIG_PCI */ 653 654 /* 655 *SATA 656 */ 657 #define CONFIG_FSL_SATA_V2 658 #ifdef CONFIG_FSL_SATA_V2 659 #define CONFIG_LIBATA 660 #define CONFIG_FSL_SATA 661 #define CONFIG_SYS_SATA_MAX_DEVICE 1 662 #define CONFIG_SATA1 663 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 664 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 665 #define CONFIG_LBA48 666 #define CONFIG_CMD_SATA 667 #define CONFIG_DOS_PARTITION 668 #endif 669 670 /* 671 * USB 672 */ 673 #define CONFIG_HAS_FSL_DR_USB 674 675 #ifdef CONFIG_HAS_FSL_DR_USB 676 #define CONFIG_USB_EHCI 677 #define CONFIG_USB_EHCI_FSL 678 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 679 #endif 680 681 /* 682 * SDHC 683 */ 684 #define CONFIG_MMC 685 #ifdef CONFIG_MMC 686 #define CONFIG_FSL_ESDHC 687 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 688 #define CONFIG_GENERIC_MMC 689 #define CONFIG_DOS_PARTITION 690 #endif 691 692 /* Qman/Bman */ 693 #ifndef CONFIG_NOBQFMAN 694 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 695 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 696 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 697 #ifdef CONFIG_PHYS_64BIT 698 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 699 #else 700 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 701 #endif 702 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 703 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 704 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 705 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 706 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 707 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 708 CONFIG_SYS_BMAN_CENA_SIZE) 709 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 710 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 711 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 712 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 713 #ifdef CONFIG_PHYS_64BIT 714 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 715 #else 716 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 717 #endif 718 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 719 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 720 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 721 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 722 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 723 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 724 CONFIG_SYS_QMAN_CENA_SIZE) 725 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 726 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 727 728 #define CONFIG_SYS_DPAA_FMAN 729 730 #define CONFIG_QE 731 #define CONFIG_U_QE 732 /* Default address of microcode for the Linux FMan driver */ 733 #if defined(CONFIG_SPIFLASH) 734 /* 735 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 736 * env, so we got 0x110000. 737 */ 738 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 739 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 740 #define CONFIG_SYS_QE_FW_ADDR 0x130000 741 #elif defined(CONFIG_SDCARD) 742 /* 743 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 744 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 745 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 746 */ 747 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 748 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 749 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 750 #elif defined(CONFIG_NAND) 751 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 752 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 753 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 754 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 755 /* 756 * Slave has no ucode locally, it can fetch this from remote. When implementing 757 * in two corenet boards, slave's ucode could be stored in master's memory 758 * space, the address can be mapped from slave TLB->slave LAW-> 759 * slave SRIO or PCIE outbound window->master inbound window-> 760 * master LAW->the ucode address in master's memory space. 761 */ 762 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 763 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 764 #else 765 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 766 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 767 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 768 #endif 769 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 770 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 771 #endif /* CONFIG_NOBQFMAN */ 772 773 #ifdef CONFIG_SYS_DPAA_FMAN 774 #define CONFIG_FMAN_ENET 775 #define CONFIG_PHYLIB_10G 776 #define CONFIG_PHY_VITESSE 777 #define CONFIG_PHY_REALTEK 778 #define CONFIG_PHY_TERANETICS 779 #define RGMII_PHY1_ADDR 0x1 780 #define RGMII_PHY2_ADDR 0x2 781 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 782 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 783 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 784 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 785 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 786 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 787 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 788 #endif 789 790 #ifdef CONFIG_FMAN_ENET 791 #define CONFIG_MII /* MII PHY management */ 792 #define CONFIG_ETHPRIME "FM1@DTSEC4" 793 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 794 #endif 795 796 /* 797 * Dynamic MTD Partition support with mtdparts 798 */ 799 #ifndef CONFIG_SYS_NO_FLASH 800 #define CONFIG_MTD_DEVICE 801 #define CONFIG_MTD_PARTITIONS 802 #define CONFIG_CMD_MTDPARTS 803 #define CONFIG_FLASH_CFI_MTD 804 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 805 "spi0=spife110000.0" 806 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 807 "128k(dtb),96m(fs),-(user);"\ 808 "fff800000.flash:2m(uboot),9m(kernel),"\ 809 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 810 "2m(uboot),9m(kernel),128k(dtb),-(user)" 811 #endif 812 813 /* 814 * Environment 815 */ 816 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 817 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 818 819 /* 820 * Command line configuration. 821 */ 822 #define CONFIG_CMD_DATE 823 #define CONFIG_CMD_EEPROM 824 #define CONFIG_CMD_ERRATA 825 #define CONFIG_CMD_IRQ 826 #define CONFIG_CMD_REGINFO 827 828 #ifdef CONFIG_PCI 829 #define CONFIG_CMD_PCI 830 #endif 831 832 /* 833 * Miscellaneous configurable options 834 */ 835 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 836 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 837 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 838 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 839 #ifdef CONFIG_CMD_KGDB 840 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 841 #else 842 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 843 #endif 844 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 845 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 846 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 847 848 /* 849 * For booting Linux, the board info and command line data 850 * have to be in the first 64 MB of memory, since this is 851 * the maximum mapped by the Linux kernel during initialization. 852 */ 853 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 854 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 855 856 #ifdef CONFIG_CMD_KGDB 857 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 858 #endif 859 860 /* 861 * Environment Configuration 862 */ 863 #define CONFIG_ROOTPATH "/opt/nfsroot" 864 #define CONFIG_BOOTFILE "uImage" 865 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 866 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 867 #define CONFIG_BAUDRATE 115200 868 #define __USB_PHY_TYPE utmi 869 870 #define CONFIG_EXTRA_ENV_SETTINGS \ 871 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 872 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 873 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 874 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 875 "fdtfile=t1024qds/t1024qds.dtb\0" \ 876 "netdev=eth0\0" \ 877 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 878 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 879 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 880 "tftpflash=tftpboot $loadaddr $uboot && " \ 881 "protect off $ubootaddr +$filesize && " \ 882 "erase $ubootaddr +$filesize && " \ 883 "cp.b $loadaddr $ubootaddr $filesize && " \ 884 "protect on $ubootaddr +$filesize && " \ 885 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 886 "consoledev=ttyS0\0" \ 887 "ramdiskaddr=2000000\0" \ 888 "fdtaddr=d00000\0" \ 889 "bdev=sda3\0" 890 891 #define CONFIG_LINUX \ 892 "setenv bootargs root=/dev/ram rw " \ 893 "console=$consoledev,$baudrate $othbootargs;" \ 894 "setenv ramdiskaddr 0x02000000;" \ 895 "setenv fdtaddr 0x00c00000;" \ 896 "setenv loadaddr 0x1000000;" \ 897 "bootm $loadaddr $ramdiskaddr $fdtaddr" 898 899 #define CONFIG_NFSBOOTCOMMAND \ 900 "setenv bootargs root=/dev/nfs rw " \ 901 "nfsroot=$serverip:$rootpath " \ 902 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 903 "console=$consoledev,$baudrate $othbootargs;" \ 904 "tftp $loadaddr $bootfile;" \ 905 "tftp $fdtaddr $fdtfile;" \ 906 "bootm $loadaddr - $fdtaddr" 907 908 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 909 910 /* Hash command with SHA acceleration supported in hardware */ 911 #ifdef CONFIG_FSL_CAAM 912 #define CONFIG_CMD_HASH 913 #define CONFIG_SHA_HW_ACCEL 914 #endif 915 916 #include <asm/fsl_secure_boot.h> 917 918 #endif /* __T1024QDS_H */ 919