1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #ifdef CONFIG_PHYS_64BIT 24 #define CONFIG_ADDR_MAP 1 25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 26 #endif 27 28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 29 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 30 #define CONFIG_FSL_IFC /* Enable IFC Support */ 31 32 #define CONFIG_FSL_LAW /* Use common FSL init code */ 33 #define CONFIG_ENV_OVERWRITE 34 35 #define CONFIG_DEEP_SLEEP 36 #if defined(CONFIG_DEEP_SLEEP) 37 #define CONFIG_SILENT_CONSOLE 38 #define CONFIG_BOARD_EARLY_INIT_F 39 #endif 40 41 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 42 43 #ifdef CONFIG_RAMBOOT_PBL 44 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg 46 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 47 #define CONFIG_SPL_SERIAL_SUPPORT 48 #define CONFIG_SPL_FLUSH_IMAGE 49 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 50 #define CONFIG_SPL_LIBGENERIC_SUPPORT 51 #define CONFIG_SPL_LIBCOMMON_SUPPORT 52 #define CONFIG_SPL_I2C_SUPPORT 53 #define CONFIG_FSL_LAW /* Use common FSL init code */ 54 #define CONFIG_SYS_TEXT_BASE 0x00201000 55 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 56 #define CONFIG_SPL_PAD_TO 0x40000 57 #define CONFIG_SPL_MAX_SIZE 0x28000 58 #define RESET_VECTOR_OFFSET 0x27FFC 59 #define BOOT_PAGE_OFFSET 0x27000 60 #ifdef CONFIG_SPL_BUILD 61 #define CONFIG_SPL_SKIP_RELOCATE 62 #define CONFIG_SPL_COMMON_INIT_DDR 63 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 64 #define CONFIG_SYS_NO_FLASH 65 #endif 66 67 #ifdef CONFIG_NAND 68 #define CONFIG_SPL_NAND_SUPPORT 69 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 70 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 71 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 72 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 73 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 74 #define CONFIG_SPL_NAND_BOOT 75 #endif 76 77 #ifdef CONFIG_SPIFLASH 78 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 79 #define CONFIG_SPL_SPI_SUPPORT 80 #define CONFIG_SPL_SPI_FLASH_SUPPORT 81 #define CONFIG_SPL_SPI_FLASH_MINIMAL 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 86 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 87 #ifndef CONFIG_SPL_BUILD 88 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 89 #endif 90 #define CONFIG_SPL_SPI_BOOT 91 #endif 92 93 #ifdef CONFIG_SDCARD 94 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 95 #define CONFIG_SPL_MMC_SUPPORT 96 #define CONFIG_SPL_MMC_MINIMAL 97 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 98 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 99 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 100 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 101 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 102 #ifndef CONFIG_SPL_BUILD 103 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 104 #endif 105 #define CONFIG_SPL_MMC_BOOT 106 #endif 107 108 #endif /* CONFIG_RAMBOOT_PBL */ 109 110 #ifndef CONFIG_SYS_TEXT_BASE 111 #define CONFIG_SYS_TEXT_BASE 0xeff40000 112 #endif 113 114 #ifndef CONFIG_RESET_VECTOR_ADDRESS 115 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 116 #endif 117 118 #ifndef CONFIG_SYS_NO_FLASH 119 #define CONFIG_FLASH_CFI_DRIVER 120 #define CONFIG_SYS_FLASH_CFI 121 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 122 #endif 123 124 /* PCIe Boot - Master */ 125 #define CONFIG_SRIO_PCIE_BOOT_MASTER 126 /* 127 * for slave u-boot IMAGE instored in master memory space, 128 * PHYS must be aligned based on the SIZE 129 */ 130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 132 #ifdef CONFIG_PHYS_64BIT 133 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 135 #else 136 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 137 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 138 #endif 139 /* 140 * for slave UCODE and ENV instored in master memory space, 141 * PHYS must be aligned based on the SIZE 142 */ 143 #ifdef CONFIG_PHYS_64BIT 144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 145 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 146 #else 147 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 148 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 149 #endif 150 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 151 /* slave core release by master*/ 152 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 153 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 154 155 /* PCIe Boot - Slave */ 156 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 157 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 158 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 159 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 160 /* Set 1M boot space for PCIe boot */ 161 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 162 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 163 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 164 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 165 #define CONFIG_SYS_NO_FLASH 166 #endif 167 168 #if defined(CONFIG_SPIFLASH) 169 #define CONFIG_SYS_EXTRA_ENV_RELOC 170 #define CONFIG_ENV_IS_IN_SPI_FLASH 171 #define CONFIG_ENV_SPI_BUS 0 172 #define CONFIG_ENV_SPI_CS 0 173 #define CONFIG_ENV_SPI_MAX_HZ 10000000 174 #define CONFIG_ENV_SPI_MODE 0 175 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 176 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 177 #define CONFIG_ENV_SECT_SIZE 0x10000 178 #elif defined(CONFIG_SDCARD) 179 #define CONFIG_SYS_EXTRA_ENV_RELOC 180 #define CONFIG_ENV_IS_IN_MMC 181 #define CONFIG_SYS_MMC_ENV_DEV 0 182 #define CONFIG_ENV_SIZE 0x2000 183 #define CONFIG_ENV_OFFSET (512 * 0x800) 184 #elif defined(CONFIG_NAND) 185 #define CONFIG_SYS_EXTRA_ENV_RELOC 186 #define CONFIG_ENV_IS_IN_NAND 187 #define CONFIG_ENV_SIZE 0x2000 188 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 189 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 190 #define CONFIG_ENV_IS_IN_REMOTE 191 #define CONFIG_ENV_ADDR 0xffe20000 192 #define CONFIG_ENV_SIZE 0x2000 193 #elif defined(CONFIG_ENV_IS_NOWHERE) 194 #define CONFIG_ENV_SIZE 0x2000 195 #else 196 #define CONFIG_ENV_IS_IN_FLASH 197 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 198 #define CONFIG_ENV_SIZE 0x2000 199 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 200 #endif 201 202 #ifndef __ASSEMBLY__ 203 unsigned long get_board_sys_clk(void); 204 unsigned long get_board_ddr_clk(void); 205 #endif 206 207 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 208 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 209 210 /* 211 * These can be toggled for performance analysis, otherwise use default. 212 */ 213 #define CONFIG_SYS_CACHE_STASHING 214 #define CONFIG_BACKSIDE_L2_CACHE 215 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 216 #define CONFIG_BTB /* toggle branch predition */ 217 #define CONFIG_DDR_ECC 218 #ifdef CONFIG_DDR_ECC 219 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 220 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 221 #endif 222 223 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 224 #define CONFIG_SYS_MEMTEST_END 0x00400000 225 #define CONFIG_SYS_ALT_MEMTEST 226 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 227 228 /* 229 * Config the L3 Cache as L3 SRAM 230 */ 231 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 232 #define CONFIG_SYS_L3_SIZE (256 << 10) 233 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 234 #ifdef CONFIG_RAMBOOT_PBL 235 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 236 #endif 237 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 238 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 239 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 240 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 241 242 #ifdef CONFIG_PHYS_64BIT 243 #define CONFIG_SYS_DCSRBAR 0xf0000000 244 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 245 #endif 246 247 /* EEPROM */ 248 #define CONFIG_ID_EEPROM 249 #define CONFIG_SYS_I2C_EEPROM_NXID 250 #define CONFIG_SYS_EEPROM_BUS_NUM 0 251 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 252 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 253 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 254 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 255 256 /* 257 * DDR Setup 258 */ 259 #define CONFIG_VERY_BIG_RAM 260 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 261 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 262 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 263 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 264 #define CONFIG_DDR_SPD 265 #ifndef CONFIG_SYS_FSL_DDR4 266 #define CONFIG_SYS_FSL_DDR3 267 #endif 268 269 #define CONFIG_SYS_SPD_BUS_NUM 0 270 #define SPD_EEPROM_ADDRESS 0x51 271 272 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 273 274 /* 275 * IFC Definitions 276 */ 277 #define CONFIG_SYS_FLASH_BASE 0xe0000000 278 #ifdef CONFIG_PHYS_64BIT 279 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 280 #else 281 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 282 #endif 283 284 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 285 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 286 + 0x8000000) | \ 287 CSPR_PORT_SIZE_16 | \ 288 CSPR_MSEL_NOR | \ 289 CSPR_V) 290 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 291 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 292 CSPR_PORT_SIZE_16 | \ 293 CSPR_MSEL_NOR | \ 294 CSPR_V) 295 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 296 /* NOR Flash Timing Params */ 297 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 298 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 299 FTIM0_NOR_TEADC(0x5) | \ 300 FTIM0_NOR_TEAHC(0x5)) 301 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 302 FTIM1_NOR_TRAD_NOR(0x1A) |\ 303 FTIM1_NOR_TSEQRAD_NOR(0x13)) 304 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 305 FTIM2_NOR_TCH(0x4) | \ 306 FTIM2_NOR_TWPH(0x0E) | \ 307 FTIM2_NOR_TWP(0x1c)) 308 #define CONFIG_SYS_NOR_FTIM3 0x0 309 310 #define CONFIG_SYS_FLASH_QUIET_TEST 311 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 312 313 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 314 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 315 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 316 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 317 318 #define CONFIG_SYS_FLASH_EMPTY_INFO 319 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 320 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 321 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 322 #define QIXIS_BASE 0xffdf0000 323 #ifdef CONFIG_PHYS_64BIT 324 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 325 #else 326 #define QIXIS_BASE_PHYS QIXIS_BASE 327 #endif 328 #define QIXIS_LBMAP_SWITCH 0x06 329 #define QIXIS_LBMAP_MASK 0x0f 330 #define QIXIS_LBMAP_SHIFT 0 331 #define QIXIS_LBMAP_DFLTBANK 0x00 332 #define QIXIS_LBMAP_ALTBANK 0x04 333 #define QIXIS_RST_CTL_RESET 0x31 334 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 335 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 336 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 337 #define QIXIS_RST_FORCE_MEM 0x01 338 339 #define CONFIG_SYS_CSPR3_EXT (0xf) 340 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 341 | CSPR_PORT_SIZE_8 \ 342 | CSPR_MSEL_GPCM \ 343 | CSPR_V) 344 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 345 #define CONFIG_SYS_CSOR3 0x0 346 /* QIXIS Timing parameters for IFC CS3 */ 347 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 348 FTIM0_GPCM_TEADC(0x0e) | \ 349 FTIM0_GPCM_TEAHC(0x0e)) 350 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 351 FTIM1_GPCM_TRAD(0x3f)) 352 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 353 FTIM2_GPCM_TCH(0x8) | \ 354 FTIM2_GPCM_TWP(0x1f)) 355 #define CONFIG_SYS_CS3_FTIM3 0x0 356 357 #define CONFIG_NAND_FSL_IFC 358 #define CONFIG_SYS_NAND_BASE 0xff800000 359 #ifdef CONFIG_PHYS_64BIT 360 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 361 #else 362 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 363 #endif 364 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 365 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 366 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 367 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 368 | CSPR_V) 369 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 370 371 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 372 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 373 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 374 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 375 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 376 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 377 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 378 379 #define CONFIG_SYS_NAND_ONFI_DETECTION 380 381 /* ONFI NAND Flash mode0 Timing Params */ 382 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 383 FTIM0_NAND_TWP(0x18) | \ 384 FTIM0_NAND_TWCHT(0x07) | \ 385 FTIM0_NAND_TWH(0x0a)) 386 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 387 FTIM1_NAND_TWBE(0x39) | \ 388 FTIM1_NAND_TRR(0x0e) | \ 389 FTIM1_NAND_TRP(0x18)) 390 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 391 FTIM2_NAND_TREH(0x0a) | \ 392 FTIM2_NAND_TWHRE(0x1e)) 393 #define CONFIG_SYS_NAND_FTIM3 0x0 394 395 #define CONFIG_SYS_NAND_DDR_LAW 11 396 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 397 #define CONFIG_SYS_MAX_NAND_DEVICE 1 398 #define CONFIG_CMD_NAND 399 400 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 401 402 #if defined(CONFIG_NAND) 403 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 404 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 405 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 406 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 407 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 408 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 409 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 410 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 411 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 412 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 413 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 414 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 415 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 416 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 417 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 418 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 419 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 420 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 421 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 422 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 423 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 424 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 425 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 426 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 427 #else 428 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 429 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 430 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 431 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 432 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 433 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 434 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 435 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 436 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 437 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 438 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 439 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 440 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 441 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 442 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 443 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 444 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 445 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 446 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 447 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 448 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 449 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 450 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 451 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 452 #endif 453 454 #ifdef CONFIG_SPL_BUILD 455 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 456 #else 457 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 458 #endif 459 460 #if defined(CONFIG_RAMBOOT_PBL) 461 #define CONFIG_SYS_RAMBOOT 462 #endif 463 464 #define CONFIG_BOARD_EARLY_INIT_R 465 #define CONFIG_MISC_INIT_R 466 467 #define CONFIG_HWCONFIG 468 469 /* define to use L1 as initial stack */ 470 #define CONFIG_L1_INIT_RAM 471 #define CONFIG_SYS_INIT_RAM_LOCK 472 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 473 #ifdef CONFIG_PHYS_64BIT 474 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 475 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 476 /* The assembler doesn't like typecast */ 477 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 478 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 479 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 480 #else 481 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 482 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 483 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 484 #endif 485 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 486 487 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 488 GENERATED_GBL_DATA_SIZE) 489 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 490 491 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 492 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 493 494 /* Serial Port */ 495 #define CONFIG_CONS_INDEX 1 496 #define CONFIG_SYS_NS16550_SERIAL 497 #define CONFIG_SYS_NS16550_REG_SIZE 1 498 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 499 500 #define CONFIG_SYS_BAUDRATE_TABLE \ 501 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 502 503 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 504 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 505 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 506 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 507 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 508 509 /* Video */ 510 #ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */ 511 #define CONFIG_FSL_DIU_FB 512 #ifdef CONFIG_FSL_DIU_FB 513 #define CONFIG_FSL_DIU_CH7301 514 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 515 #define CONFIG_VIDEO 516 #define CONFIG_CMD_BMP 517 #define CONFIG_CFB_CONSOLE 518 #define CONFIG_VIDEO_SW_CURSOR 519 #define CONFIG_VGA_AS_SINGLE_DEVICE 520 #define CONFIG_VIDEO_LOGO 521 #define CONFIG_VIDEO_BMP_LOGO 522 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 523 /* 524 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 525 * disable empty flash sector detection, which is I/O-intensive. 526 */ 527 #undef CONFIG_SYS_FLASH_EMPTY_INFO 528 #endif 529 #endif 530 531 /* I2C */ 532 #define CONFIG_SYS_I2C 533 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 534 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 535 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 536 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 537 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 538 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 539 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 540 541 #define I2C_MUX_PCA_ADDR 0x77 542 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 543 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 544 #define I2C_RETIMER_ADDR 0x18 545 546 /* I2C bus multiplexer */ 547 #define I2C_MUX_CH_DEFAULT 0x8 548 #define I2C_MUX_CH_DIU 0xC 549 #define I2C_MUX_CH5 0xD 550 #define I2C_MUX_CH7 0xF 551 552 /* LDI/DVI Encoder for display */ 553 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 554 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 555 556 /* 557 * RTC configuration 558 */ 559 #define RTC 560 #define CONFIG_RTC_DS3231 1 561 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 562 563 /* 564 * eSPI - Enhanced SPI 565 */ 566 #ifndef CONFIG_SPL_BUILD 567 #endif 568 #define CONFIG_SPI_FLASH_BAR 569 #define CONFIG_SF_DEFAULT_SPEED 10000000 570 #define CONFIG_SF_DEFAULT_MODE 0 571 572 /* 573 * General PCIe 574 * Memory space is mapped 1-1, but I/O space must start from 0. 575 */ 576 #define CONFIG_PCI /* Enable PCI/PCIE */ 577 #define CONFIG_PCIE1 /* PCIE controller 1 */ 578 #define CONFIG_PCIE2 /* PCIE controller 2 */ 579 #define CONFIG_PCIE3 /* PCIE controller 3 */ 580 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 581 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 582 #define CONFIG_PCI_INDIRECT_BRIDGE 583 584 #ifdef CONFIG_PCI 585 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 586 #ifdef CONFIG_PCIE1 587 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 588 #ifdef CONFIG_PHYS_64BIT 589 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 590 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 591 #else 592 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 593 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 594 #endif 595 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 596 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 597 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 598 #ifdef CONFIG_PHYS_64BIT 599 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 600 #else 601 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 602 #endif 603 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 604 #endif 605 606 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 607 #ifdef CONFIG_PCIE2 608 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 609 #ifdef CONFIG_PHYS_64BIT 610 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 611 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 612 #else 613 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 614 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 615 #endif 616 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 617 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 618 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 619 #ifdef CONFIG_PHYS_64BIT 620 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 621 #else 622 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 623 #endif 624 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 625 #endif 626 627 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 628 #ifdef CONFIG_PCIE3 629 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 630 #ifdef CONFIG_PHYS_64BIT 631 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 632 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 633 #else 634 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 635 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 636 #endif 637 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 638 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 639 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 640 #ifdef CONFIG_PHYS_64BIT 641 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 642 #else 643 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 644 #endif 645 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 646 #endif 647 648 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 649 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 650 #define CONFIG_DOS_PARTITION 651 #endif /* CONFIG_PCI */ 652 653 /* 654 *SATA 655 */ 656 #define CONFIG_FSL_SATA_V2 657 #ifdef CONFIG_FSL_SATA_V2 658 #define CONFIG_LIBATA 659 #define CONFIG_FSL_SATA 660 #define CONFIG_SYS_SATA_MAX_DEVICE 1 661 #define CONFIG_SATA1 662 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 663 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 664 #define CONFIG_LBA48 665 #define CONFIG_CMD_SATA 666 #define CONFIG_DOS_PARTITION 667 #endif 668 669 /* 670 * USB 671 */ 672 #define CONFIG_HAS_FSL_DR_USB 673 674 #ifdef CONFIG_HAS_FSL_DR_USB 675 #define CONFIG_USB_EHCI 676 #define CONFIG_USB_EHCI_FSL 677 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 678 #endif 679 680 /* 681 * SDHC 682 */ 683 #define CONFIG_MMC 684 #ifdef CONFIG_MMC 685 #define CONFIG_FSL_ESDHC 686 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 687 #define CONFIG_GENERIC_MMC 688 #define CONFIG_DOS_PARTITION 689 #endif 690 691 /* Qman/Bman */ 692 #ifndef CONFIG_NOBQFMAN 693 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 694 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 695 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 696 #ifdef CONFIG_PHYS_64BIT 697 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 698 #else 699 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 700 #endif 701 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 702 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 703 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 704 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 705 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 706 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 707 CONFIG_SYS_BMAN_CENA_SIZE) 708 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 709 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 710 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 711 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 712 #ifdef CONFIG_PHYS_64BIT 713 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 714 #else 715 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 716 #endif 717 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 718 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 719 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 720 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 721 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 722 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 723 CONFIG_SYS_QMAN_CENA_SIZE) 724 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 725 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 726 727 #define CONFIG_SYS_DPAA_FMAN 728 729 #define CONFIG_QE 730 #define CONFIG_U_QE 731 /* Default address of microcode for the Linux FMan driver */ 732 #if defined(CONFIG_SPIFLASH) 733 /* 734 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 735 * env, so we got 0x110000. 736 */ 737 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 738 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 739 #define CONFIG_SYS_QE_FW_ADDR 0x130000 740 #elif defined(CONFIG_SDCARD) 741 /* 742 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 743 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 744 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 745 */ 746 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 747 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 748 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 749 #elif defined(CONFIG_NAND) 750 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 751 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 752 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 753 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 754 /* 755 * Slave has no ucode locally, it can fetch this from remote. When implementing 756 * in two corenet boards, slave's ucode could be stored in master's memory 757 * space, the address can be mapped from slave TLB->slave LAW-> 758 * slave SRIO or PCIE outbound window->master inbound window-> 759 * master LAW->the ucode address in master's memory space. 760 */ 761 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 762 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 763 #else 764 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 765 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 766 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 767 #endif 768 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 769 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 770 #endif /* CONFIG_NOBQFMAN */ 771 772 #ifdef CONFIG_SYS_DPAA_FMAN 773 #define CONFIG_FMAN_ENET 774 #define CONFIG_PHYLIB_10G 775 #define CONFIG_PHY_VITESSE 776 #define CONFIG_PHY_REALTEK 777 #define CONFIG_PHY_TERANETICS 778 #define RGMII_PHY1_ADDR 0x1 779 #define RGMII_PHY2_ADDR 0x2 780 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 781 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 782 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 783 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 784 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 785 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 786 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 787 #endif 788 789 #ifdef CONFIG_FMAN_ENET 790 #define CONFIG_MII /* MII PHY management */ 791 #define CONFIG_ETHPRIME "FM1@DTSEC4" 792 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 793 #endif 794 795 /* 796 * Dynamic MTD Partition support with mtdparts 797 */ 798 #ifndef CONFIG_SYS_NO_FLASH 799 #define CONFIG_MTD_DEVICE 800 #define CONFIG_MTD_PARTITIONS 801 #define CONFIG_CMD_MTDPARTS 802 #define CONFIG_FLASH_CFI_MTD 803 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 804 "spi0=spife110000.0" 805 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 806 "128k(dtb),96m(fs),-(user);"\ 807 "fff800000.flash:2m(uboot),9m(kernel),"\ 808 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 809 "2m(uboot),9m(kernel),128k(dtb),-(user)" 810 #endif 811 812 /* 813 * Environment 814 */ 815 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 816 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 817 818 /* 819 * Command line configuration. 820 */ 821 #define CONFIG_CMD_DATE 822 #define CONFIG_CMD_EEPROM 823 #define CONFIG_CMD_ERRATA 824 #define CONFIG_CMD_IRQ 825 #define CONFIG_CMD_REGINFO 826 827 #ifdef CONFIG_PCI 828 #define CONFIG_CMD_PCI 829 #endif 830 831 /* 832 * Miscellaneous configurable options 833 */ 834 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 835 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 836 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 837 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 838 #ifdef CONFIG_CMD_KGDB 839 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 840 #else 841 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 842 #endif 843 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 844 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 845 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 846 847 /* 848 * For booting Linux, the board info and command line data 849 * have to be in the first 64 MB of memory, since this is 850 * the maximum mapped by the Linux kernel during initialization. 851 */ 852 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 853 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 854 855 #ifdef CONFIG_CMD_KGDB 856 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 857 #endif 858 859 /* 860 * Environment Configuration 861 */ 862 #define CONFIG_ROOTPATH "/opt/nfsroot" 863 #define CONFIG_BOOTFILE "uImage" 864 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 865 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 866 #define CONFIG_BAUDRATE 115200 867 #define __USB_PHY_TYPE utmi 868 869 #define CONFIG_EXTRA_ENV_SETTINGS \ 870 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 871 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 872 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 873 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 874 "fdtfile=t1024qds/t1024qds.dtb\0" \ 875 "netdev=eth0\0" \ 876 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 877 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 878 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 879 "tftpflash=tftpboot $loadaddr $uboot && " \ 880 "protect off $ubootaddr +$filesize && " \ 881 "erase $ubootaddr +$filesize && " \ 882 "cp.b $loadaddr $ubootaddr $filesize && " \ 883 "protect on $ubootaddr +$filesize && " \ 884 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 885 "consoledev=ttyS0\0" \ 886 "ramdiskaddr=2000000\0" \ 887 "fdtaddr=d00000\0" \ 888 "bdev=sda3\0" 889 890 #define CONFIG_LINUX \ 891 "setenv bootargs root=/dev/ram rw " \ 892 "console=$consoledev,$baudrate $othbootargs;" \ 893 "setenv ramdiskaddr 0x02000000;" \ 894 "setenv fdtaddr 0x00c00000;" \ 895 "setenv loadaddr 0x1000000;" \ 896 "bootm $loadaddr $ramdiskaddr $fdtaddr" 897 898 #define CONFIG_NFSBOOTCOMMAND \ 899 "setenv bootargs root=/dev/nfs rw " \ 900 "nfsroot=$serverip:$rootpath " \ 901 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 902 "console=$consoledev,$baudrate $othbootargs;" \ 903 "tftp $loadaddr $bootfile;" \ 904 "tftp $fdtaddr $fdtfile;" \ 905 "bootm $loadaddr - $fdtaddr" 906 907 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 908 909 /* Hash command with SHA acceleration supported in hardware */ 910 #ifdef CONFIG_FSL_CAAM 911 #define CONFIG_CMD_HASH 912 #define CONFIG_SHA_HW_ACCEL 913 #endif 914 915 #include <asm/fsl_secure_boot.h> 916 917 #endif /* __T1024QDS_H */ 918